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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-elf-or1ksim).  The OpenRISC 1000 Architectural
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                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 460 jeremybenn
     tar jxf or1ksim-2011-01-05.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
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default to OpenRISC 1000 32-bit with a warning
83
 
84 460 jeremybenn
     ../or1ksim-2011-01-05/configure --target=or32-elf ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 385 jeremybenn
For testing (using `make check'), the `--target' parameter may be
92
specified, to allow the target tool chain to be selected.  If not
93
specified, it will default to `or32-elf', which is the same prefix used
94
with the standard OpenRISC toolchain installation script.
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96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
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     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
115 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
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119
    `--enable-execution=dynamic'
120 82 jeremybenn
          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
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     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
134 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140 346 jeremybenn
     Historically, `l.xori', has sign extended its operand.  This is
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     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
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`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 346 jeremybenn
because they led to invalid behavior of Or1ksim.  Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194 346 jeremybenn
     If set, this caused incorrect behavior.  Whether or not flags are
195 124 jeremybenn
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
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223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242 442 julius
`or32-elf-sim', `or32-elf-psim' and `or32-elf-mpsim', the Or1ksim
243
library, `libsim', the header file, `or1ksim.h' and this documentation
244
in `info' format.
245 19 jeremybenn
 
246
The documentation may be created and installed in alternative formats
247
(PDF, Postscript, DVI, HTML) with for example:
248
 
249
     make pdf
250
     make install-pdf
251
 
252

253
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
254
 
255
1.4 Known Problems and Issues
256
=============================
257
 
258 346 jeremybenn
Full details of outstanding issues may be found in the `NEWS' file in
259
the main directory of the distribution.  The OpenRISC tracker may be
260
used to see the current state of these issues and to raise new problems
261
and feature requests.  It may be found at bugtracker.
262 19 jeremybenn
 
263 346 jeremybenn
The following issues are long standing and unlikely to be fixed in
264
Or1ksim in the near future.
265
 
266 19 jeremybenn
   * The Supervision Register Little Endian Enable (LEE) bit is
267 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
268 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
269
 
270
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
271 82 jeremybenn
     instances using the library.  This is clearly a problem when
272
     considering multi-core applications.  However it stems from the
273
     original design, and can only be fixed by a complete rewrite.  The
274 19 jeremybenn
     entire source code uses static global constants liberally!
275
 
276
 
277

278
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
279
 
280
2 Usage
281
*******
282
 
283
* Menu:
284
 
285
* Standalone Simulator::
286
* Profiling Utility::
287
* Memory Profiling Utility::
288 442 julius
* Trace Generation::
289 19 jeremybenn
* Simulator Library::
290 440 jeremybenn
* Ethernet TUN/TAP Interface::
291 460 jeremybenn
* l.nop Support::
292 19 jeremybenn
 
293

294
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
295
 
296
2.1 Standalone Simulator
297
========================
298
 
299
The general form the standalone command is:
300
 
301 442 julius
     or32-elf-sim [-vhiqVt] [-f FILE] [--nosrv] [--srv=[N]]
302 346 jeremybenn
                      [-m ][-d STR]
303 19 jeremybenn
                      [--enable-profile] [--enable-mprofile] [FILE]
304
 
305 82 jeremybenn
Many of the options have both a short and a long form.  For example
306
`-h' or `--help'.
307 19 jeremybenn
 
308
`-v'
309
`--version'
310
     Print out the version and copyright notice for Or1ksim and exit.
311
 
312
`-h'
313
`--help'
314
     Print out help about the command line options and what they mean.
315
 
316 346 jeremybenn
`-i'
317
`--interactive'
318
     After starting, drop into the Or1ksim interactive command shell.
319
 
320
`-q'
321
`--quiet'
322
     Do not generate any information messages, only error messages.
323
 
324
`-V'
325
`--verbose'
326
     Generate extra output messages (equivalent of specifying the
327
     "verbose" option in the simulator configuration section (see *note
328
     Simulator Behavior: Simulator Behavior.).
329
 
330 385 jeremybenn
`-t'
331
`--trace'
332 420 jeremybenn
     Dump instruction just executed and any register/memory location
333
     chaged after each instruction (one line per instruction).
334 385 jeremybenn
 
335 19 jeremybenn
`-f FILE'
336 385 jeremybenn
`--file=FILE'
337 19 jeremybenn
     Read configuration commands from the specified file, looking first
338
     in the current directory, and otherwise in the `$HOME/.or1k'
339 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
340
     in those two locations is used.  Failure to find the file is a
341
     fatal error.  *Note Configuration: Configuration, for detailed
342
     information on configuring Or1ksim.
343 19 jeremybenn
 
344
`--nosrv'
345 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
346
     overrides any setting specified in the configuration file.  This
347
     option may not be specified with `--srv'.  If it is, a rude
348
     message is printed and the `--nosrv' option is ignored.
349 19 jeremybenn
 
350
`--srv'
351
 
352
`--srv=N'
353 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
354
     overrides any setting specified in the configuration file.  If the
355
     parameter, N, is specified, use that as the TCP/IP port for the
356
     server, otherwise a random value from the private port range
357
     (41920-65535) will be used.  This option may not be specified with
358
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
359
     option is ignored.
360 19 jeremybenn
 
361 385 jeremybenn
`-m SIZE'
362 346 jeremybenn
`--memory=SIZE'
363
     Configure a memory block of SIZE bytes, starting at address zero.
364
     The size may be followed by `k', `K', `m', `M', `g', `G', to
365
     indicate kilobytes (2^10 bytes), megabytes (2^20 bytes) and
366
     gigabytes (2^30 bytes).
367
 
368
     This is mainly intended for use when Or1ksim is used without a
369
     configuration file, to allow just the processor and memory to be
370
     set up.  This is the equivalent of specifying a configuration
371
     memory section with `baseaddr = 0' and `size = SIZE' and all other
372
     parameters taking their default value.
373
 
374
     If a configuration file is also used, it should be sure not to
375
     specify an overlapping memory block.
376
 
377 385 jeremybenn
`-d CONFIG_STRING'
378 19 jeremybenn
`--debug-config=CONFIG_STRING'
379 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
380
     use by developers only, and is not covered further here.  See the
381 19 jeremybenn
     source code for more details.
382
 
383 346 jeremybenn
`--report-memory-errors'
384
     By default all exceptions are now handled silently.  If this
385
     option is specified, bus exceptions will be reported with a
386
     message to standard error indicating the address at which the
387
     exception occurred.
388 19 jeremybenn
 
389 346 jeremybenn
     This was the default behaviour up to Or1ksim 0.4.0.  This flag is
390
     provided for those who wish to keep that behavior.
391
 
392 19 jeremybenn
`--strict-npc'
393
     In real hardware, setting the next program counter (NPC, SPR 16),
394 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
395
     until the pipeline refills, reading the NPC will return zero.
396
     This is typically the case when debugging, since the processor is
397 19 jeremybenn
     stalled.
398
 
399
     Historically, Or1ksim has always returned the value of the NPC,
400 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
401
     is used, then Or1ksim will mirror real hardware more accurately.
402
     If the NPC is changed while the processor is stalled, subsequent
403 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
404
 
405
     This is not currently the default behavior, since tools such as
406
     GDB have been implemented assuming the historic Or1ksim behavior.
407
     However at some time in the future it will become the default.
408
 
409
`--enable-profile'
410
     Enable instruction profiling.
411
 
412
`--enable-mprofile'
413
     Enable memory profiling.
414
 
415
 
416

417
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
418
 
419
2.2 Profiling Utility
420
=====================
421
 
422 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
423
It may be invoked as a standalone command, or from the Or1ksim CLI.
424
The general form the standalone command is:
425 19 jeremybenn
 
426 442 julius
     or32-elf-profile [-vhcq] [-g=FILE]
427 19 jeremybenn
 
428 82 jeremybenn
Many of the options have both a short and a long form.  For example
429
`-h' or `--help'.
430 19 jeremybenn
 
431
`-v'
432
`--version'
433
     Print out the version and copyright notice for the Or1ksim
434
     profiling utility and exit.
435
 
436
`-h'
437
`--help'
438
     Print out help about the command line options and what they mean.
439
 
440
`-c'
441
`--cumulative'
442
     Show cumulative sum of cycles in functions
443
 
444
`-q'
445
`--quiet'
446
     Suppress messages
447
 
448
`-g=FILE'
449
`--generate=FILE'
450 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
451 19 jeremybenn
     `sim.profile' is used.
452
 
453
 
454

455 442 julius
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Trace Generation,  Prev: Profiling Utility,  Up: Usage
456 19 jeremybenn
 
457
2.3 Memory Profiling Utility
458
============================
459
 
460 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
461
be invoked as a standalone command, or from the Or1ksim CLI.  The
462 19 jeremybenn
general form the standalone command is:
463
 
464 442 julius
     or32-elf-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
465 19 jeremybenn
 
466 82 jeremybenn
Many of the options have both a short and a long form.  For example
467
`-h' or `--help'.
468 19 jeremybenn
 
469
`-v'
470
`--version'
471
     Print out the version and copyright notice for the Or1ksim memory
472
     profiling utility and exit.
473
 
474
`-h'
475
`--help'
476
     Print out help about the command line options and what they mean.
477
 
478
`-m=M'
479
`--mode=M'
480 82 jeremybenn
     Specify the mode out output.  Permitted options are
481 19 jeremybenn
 
482
    `detailed'
483
    `d'
484 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
485 19 jeremybenn
 
486
    `pretty'
487
    `p'
488
          Pretty printed output.
489
 
490
    `access'
491
    `a'
492
          Memory accesses only.
493
 
494
    `width'
495
    `w'
496
          Access width only.
497
 
498
 
499
`-g=N'
500
`--group=N'
501
     Group 2^n bits of successive addresses together.
502
 
503
`-f=FILE'
504
`--filename=FILE'
505 82 jeremybenn
     The data file to analyse.  If not specified, the default,
506 19 jeremybenn
     `sim.profile' is used.
507
 
508
`FROM'
509
`TO'
510
     FROM and TO are respectively the start and end address of the
511
     region of memory to be analysed.
512
 
513
 
514

515 442 julius
File: or1ksim.info,  Node: Trace Generation,  Next: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
516 19 jeremybenn
 
517 442 julius
2.4 Trace Generation
518
====================
519
 
520
An execution trace can be generated at run time with options passed by
521
the command line, or via the operating system's signal passing
522
mechanism.
523
 
524 450 jeremybenn
The following, passed at run time, can be used to create an execution
525
dump.
526
 
527 442 julius
`-t'
528
`--trace'
529
     Dump instruction just executed and any register/memory location
530
     chaged after each instruction (one line per instruction).
531
 
532 450 jeremybenn
Passing a signal `SIGUSR1' while the simulator is running toggles trace
533
generation. This can be done with the following command, assuming
534
Or1ksim's executable name is `or32-elf-sim':
535
 
536
     pkill -SIGUSR1 or32-elf-sim
537
 
538
This is useful in the case where trace output is desired after a
539
significant amount of simulation time, where it would be inconvenient to
540
generate trace up to that point.
541
 
542
If the `pkill' utility is not available, the `kill' utility can be used
543
if Or1ksim's process number is known. Use the following to determine
544
the process ID of the `or32-elf-sim' and then send the `SIGUSR1'
545
command to toggle execution trace generation:
546
 
547
     ps a | grep or32-elf-sim
548
     kill -SIGUSR1 _process-number_
549
 
550 442 julius

551
File: or1ksim.info,  Node: Simulator Library,  Next: Ethernet TUN/TAP Interface,  Prev: Trace Generation,  Up: Usage
552
 
553
2.5 Simulator Library
554 19 jeremybenn
=====================
555
 
556
Or1ksim may be used as a static of dynamic library, `libsim.a' or
557 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
558 19 jeremybenn
should be added to the link command.
559
 
560
The header file `or1ksim.h' contains appropriate declarations of the
561 82 jeremybenn
functions exported by the Or1ksim library.  These are:
562 19 jeremybenn
 
563 346 jeremybenn
 -- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
564 432 jeremybenn
          *CLASS_PTR, int (*UPR)(void *CLASS_PTR, unsigned long int
565
          ADDR, unsigned char MASK[], unsigned char RDATA[], int
566
          DATA_LEN), int (*UPW)(void *CLASS_PTR, unsigned long int
567
          ADDR, unsigned char MASK[], unsigned char WDATA[], int
568
          DATA_LEN))
569 346 jeremybenn
     The initialization function is supplied with a vector of arguments,
570
     which are interpreted as arguments to the standalone version (see
571
     *note Standalone Simulator: Standalone Simulator.), a pointer to
572
     the calling class, CLASS_PTR (since the library may be used from
573
     C++) and two up-call functions, one for reads, UPR, and one for
574
     writes, UPW.
575 19 jeremybenn
 
576
     UPW is called for any write to an address external to the model
577 82 jeremybenn
     (determined by a `generic' section in the configuration file).
578
     UPR is called for any reads to an external address.  The CLASS_PTR
579
     is passed back with these upcalls, allowing the function to
580
     associate the call with the class which originally initialized the
581 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
582
     non-zero otherwise.  At the present time the meaning of non-zero
583
     values is not defined but this may change in the future.
584 19 jeremybenn
 
585 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
586 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
587 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
588
     address, since the upcall function must handle all generic
589
     devices, using the full address for decoding.
590 19 jeremybenn
 
591 346 jeremybenn
     Endianness is not a concern, since Or1ksim is transferring byte
592
     vectors, not multi-byte values.
593 19 jeremybenn
 
594 346 jeremybenn
     The result indicates whether the initialization was successful.
595
     The integer values are available as an `enum or1ksim', with
596
     possible values `OR1KSIM_RC_OK' and `OR1KSIM_RC_BADINIT'.
597 19 jeremybenn
 
598 346 jeremybenn
          Caution: This is a change from versions 0.3.0 and 0.4.0.  It
599
          further simplifies the interface, and makes Or1ksim more
600
          consistent with payload representation in SystemC TLM 2.0.
601
 
602 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
603
          single words (4 bytes), using masks if smaller values are
604
          required.  In this it mimcs the behavior of the WishBone bus.
605
 
606
 
607 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
608
     Run the simulator for the simulated duration specified (in
609 346 jeremybenn
     seconds).  A duration of -1 indicates `run forever'
610 19 jeremybenn
 
611 346 jeremybenn
     The result indicates how the run terminated.  The integer values
612
     are available as an `enum or1ksim', with possible values
613
     `OR1KSIM_RC_OK' (ran for the full duration), `OR1KSIM_RC_BRKPT'
614
     (terminated early due to hitting a breakpoint) and
615
     `OR1KSIM_RC_HALTED' (terminated early due to hitting `l.nop 1').
616 19 jeremybenn
 
617 346 jeremybenn
 
618 19 jeremybenn
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
619
     Change the duration of a run specified in an earlier call to
620 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
621 19 jeremybenn
     realizes it needs to change the duration of the run specified in
622
     the call to `or1ksim_run' that has been interrupted by the upcall.
623
 
624
     The time specified is the amount of time that the run must continue
625
     for (i.e the duration from _now_, not the duration from the
626
     original call to `or1ksim_run').
627
 
628
 
629
 -- `or1ksim.h': void or1ksim_set_time_point ()
630 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
631 19 jeremybenn
 
632
 
633
 -- `or1ksim.h': double or1ksim_get_time_period ()
634
     Return the simulated time (in seconds) that has elapsed since the
635
     last call to `or1ksim_set_time_point'.
636
 
637
 
638
 -- `or1ksim.h': int or1ksim_is_le ()
639
     Return 1 (logical true) if the Or1ksim simulation is
640
     little-endian, 0 otherwise.
641
 
642
 
643
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
644 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
645
     specified in the configuration file.
646 19 jeremybenn
 
647
 
648
 -- `or1ksim.h': void or1ksim_interrupt (int I)
649 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
650 432 jeremybenn
     interrupt must be cleared separately by clearing the corresponding
651
     bit in the PICSR SPR.  Until the interrupt is cleared, any further
652
     interrupts on the same line will be ignored with a warning.  A
653
     warning will be generated and the interrupt request ignored if
654
     level sensitive interrupts have been configured with the
655
     programmable interrupt controller (*note Interrupt Configuration:
656
     Interrupt Configuration.).
657 19 jeremybenn
 
658
 
659
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
660 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
661 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
662 432 jeremybenn
     `or1ksim_interrupt_clear'.  Until the interrupt is cleared, any
663
     further setting of interrupts on the same line will be ignored
664
     with a warning.  A warning will be generated, and the interrupt
665
     request ignored if edge sensitive interrupts have been configured
666
     with the programmable interrupt controller (*note Interrupt
667
     Configuration: Interrupt Configuration.).
668 19 jeremybenn
 
669
 
670
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
671
     Clear a level-triggered interrupt on interrupt line I, which was
672 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
673 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
674
     edge sensitive interrupts have been configured with the
675
     programmable interrupt controller (*note Interrupt Configuration:
676
     Interrupt Configuration.).
677
 
678
 
679 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
680 346 jeremybenn
     Drive a reset sequence through the JTAG interface.  Return the
681 104 jeremybenn
     (model) time taken for this action.  Remember that the JTAG has
682
     its own clock, which can be an order of magnitude slower than the
683
     main clock, so even a reset (5 JTAG cycles) could take 50
684
     processor clock cycles to complete.
685
 
686
 
687 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned char *JREG, int
688
          NUM_BITS)
689 104 jeremybenn
     Shift the supplied register through the JTAG instruction register.
690 346 jeremybenn
     Return the (model) time taken for this action.  The register is
691 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
692
     least significant byte.  If the total number of bits is not an
693
     exact number of bytes, then the odd bits are found in the least
694
     significant end of the highest numbered byte.
695
 
696
     For example a 12-bit register would have bits 0-7 in byte 0 and
697
     bits 11-8 in the least significant 4 bits of byte 1.
698
 
699
 
700 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned char *JREG, int
701
          NUM_BITS)
702 104 jeremybenn
     Shift the supplied register through the JTAG data register.
703 346 jeremybenn
     Return the (model) time taken for this action.  The register is
704 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
705
     least significant byte.  If the total number of bits is not an
706
     exact number of bytes, then the odd bits are found in the least
707
     significant end of the highest numbered byte.
708
 
709
     For example a 12-bit register would have bits 0-7 in byte 0 and
710
     bits 11-8 in the least significant 4 bits of byte 1.
711
 
712
 
713 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_mem (unsigned long int ADDR, unsigned
714
          char *BUF, int LEN)
715 346 jeremybenn
     Read LEN bytes from ADDR, placing the result in BUF.  Return LEN
716
     on success and 0 on failure.
717
 
718
          Note: This function was added in Or1ksim 0.5.0.
719
 
720
 
721 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_mem (unsigned long int ADDR, const
722
          unsigned char *BUF, int LEN)
723 346 jeremybenn
     Write LEN bytes to ADDR, taking the data from BUF.  Return LEN on
724
     success and 0 on failure.
725
 
726
          Note: This function was added in Or1ksim 0.5.0.
727
 
728
 
729 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned long int
730
          *SPRVAL_PTR)
731 346 jeremybenn
     Read the SPR specified by SPRNUM, placing the result in
732
     SPRVAL_PTR.  Return non-zero on success and 0 on failure.
733
 
734
          Note: This function was added in Or1ksim 0.5.0.
735
 
736
 
737 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned long int
738
          SPRVA)
739 346 jeremybenn
     Write SPRVAL to the SPR specified by SPRNUM.  Return non-zero on
740
     success and 0 on failure.
741
 
742
          Note: This function was added in Or1ksim 0.5.0.
743
 
744
 
745 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned long int
746
          *REGVAL_PTR)
747 346 jeremybenn
     Read the general purpose register specified by REGNUM, placing the
748
     result in REGVAL_PTR.  Return non-zero on success and 0 on failure.
749
 
750
          Note: This function was added in Or1ksim 0.5.0.
751
 
752
 
753 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned long int
754
          REGVA)
755 346 jeremybenn
     Write REGVAL to the general purpose register specified by REGNUM.
756
     Return non-zero on success and 0 on failure.
757
 
758
          Note: This function was added in Or1ksim 0.5.0.
759
 
760
 
761 432 jeremybenn
 -- `or1ksim.h': void or1ksim_set_stall_state (int STATE)
762 346 jeremybenn
     Set the processor's state according to STATE (1 = stalled, 0 = not
763
     stalled).
764
 
765
          Note: This function was added in Or1ksim 0.5.0.
766
 
767
 
768 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
769
installation directory (as specified with the `--prefix' option to the
770
`configure' script).
771
 
772
For example if the main installation directory is `/opt/or1ksim', the
773 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
774 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
775
(`libsim.so').
776
 
777
To link against the library add the `-lsim' flag when linking and do
778
one of the following:
779
 
780
   * Add the library directory to the `LD_LIBRARY_PATH' environment
781 82 jeremybenn
     variable during execution.  For example:
782 19 jeremybenn
 
783
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
784
 
785
   * Add the library directory to the `LD_RUN_PATH' environment
786 82 jeremybenn
     variable during linking.  For example:
787 19 jeremybenn
 
788
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
789
 
790
   * Use the linker `--rpath' option and specify the library directory
791 82 jeremybenn
     when linking your program.  For example
792 19 jeremybenn
 
793 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
794 19 jeremybenn
 
795
   * Add the library directory to `/etc/ld.so.conf'
796
 
797
 
798

799 460 jeremybenn
File: or1ksim.info,  Node: Ethernet TUN/TAP Interface,  Next: l.nop Support,  Prev: Simulator Library,  Up: Usage
800 440 jeremybenn
 
801 442 julius
2.6 Ethernet TUN/TAP Interface
802 440 jeremybenn
==============================
803
 
804
When an Ethernet peripheral is configured (*note Ethernet
805
Configuration: Ethernet Configuration.), one option is to tunnel
806
traffic through a TUN/TAP interface.  The low level TAP interface is
807
used to tunnel raw Ethernet datagrams.
808
 
809
The TAP interface can then be connected to a physical Ethernet through a
810
bridge, allowing the Or1ksim model to connect to a physical network.
811
This is particularly when Or1ksim is running the OpenRISC Linux kernel
812
image.
813
 
814
This section explains how to set up a bridge for use by Or1ksim. It does
815
require superuser access to the host machine (or at least the relevant
816
network capabilities). A system administrator can modify these
817
guidelines so they are executed on reboot if appropriate.
818
 
819
* Menu:
820
 
821
* Setting Up a Persistent TAP device::
822
* Establishing a Bridge::
823
* Opening the Firewall::
824
* Disabling Ethernet Filtering::
825
* Networking from OpenRISC Linux and BusyBox::
826
* Tearing Down a Bridge::
827
 
828

829
File: or1ksim.info,  Node: Setting Up a Persistent TAP device,  Next: Establishing a Bridge,  Up: Ethernet TUN/TAP Interface
830
 
831 442 julius
2.6.1 Setting Up a Persistent TAP device
832 440 jeremybenn
----------------------------------------
833
 
834
TUN/TAP devices can be created dynamically, but this requires superuser
835
privileges (or at least `CAP_NET_ADMIN' capability).  The solution is
836
to create a persistent TAP device.  This can be done using either
837
`openvpn' or `tunctl'.  In either case the package must be installed on
838
the host system.  Using `openvpn', the following would set up a TAP
839
interface for a specified user and group.
840
 
841
     openvpn --mktun --dev tap_n_ --user _username_ --group _groupname_
842
 
843

844
File: or1ksim.info,  Node: Establishing a Bridge,  Next: Opening the Firewall,  Prev: Setting Up a Persistent TAP device,  Up: Ethernet TUN/TAP Interface
845
 
846 442 julius
2.6.2 Establishing a Bridge
847 440 jeremybenn
---------------------------
848
 
849
A bridge is a "virtual" local area network interfaces, subsuming two or
850
more existing network interfaces.  In this case we will bridge the
851
physical Ethernet interface of the host with the TAP interface that
852
will be used by Or1ksim.
853
 
854
The Ethernet and TAP must lose their own individual IP addresses (by
855
setting them to 0.0.0.0) and are replaced by the IP address of the
856
bridge interface. To do this we use the `bridge-utils' package, which
857
must be installed on the host system. These commands are require
858
superuser privileges or `CAP_NET_ADMIN' capability. To create a new
859
interface `br_n_' the following commands are appropriate.
860
 
861
     brctl addbr br_n_
862
     brctl addif br_n_ eth_x_
863
     brctl addif br_n_ tap_y_
864
 
865
     ifconfig eth_x_ 0.0.0.0 promisc up
866
     ifconfig tap_y_ 0.0.0.0 promisc up
867
 
868
     dhclient br_n_
869
 
870
The last command instructs the bridge to obtain its IP address, netmask,
871
broadcast address, gateway and nameserver information using DHCP.  In a
872
network without DHCP it should be replaced by `ifconfig' to set a
873
static IP address, netmask and broadcast address.
874
 
875
     Note: This will leave a spare dhclient process running in the
876
     background, which should be killed for tidiness. There is a
877
     technique to avoid this using `omshell', but that is beyond the
878
     scope of this guide.
879
 
880
     Note: It is not clear to the author why the existing interfaces
881
     need to be brought up in promiscuous mode, but it seems to cure
882
     various problems.
883
 
884

885
File: or1ksim.info,  Node: Opening the Firewall,  Next: Disabling Ethernet Filtering,  Prev: Establishing a Bridge,  Up: Ethernet TUN/TAP Interface
886
 
887 442 julius
2.6.3 Opening the Firewall
888 440 jeremybenn
--------------------------
889
 
890
Firewall rules should be added to ensure traffic flows freely through
891
the TAP and bridge interfaces. As superuser the following commands are
892
appropriate.
893
 
894
     iptables -A INPUT -i tap_y_ -j ACCEPT
895
     iptables -A INPUT -i br_n_ -j ACCEPT
896
     iptables -A FORWARD -i br_n_ -j ACCEPT
897
 
898

899
File: or1ksim.info,  Node: Disabling Ethernet Filtering,  Next: Networking from OpenRISC Linux and BusyBox,  Prev: Opening the Firewall,  Up: Ethernet TUN/TAP Interface
900
 
901 442 julius
2.6.4 Disabling Ethernet Filtering
902 440 jeremybenn
----------------------------------
903
 
904
Some systems may have ethernet filtering enabled (`ebtables',
905
`bridge-nf', `arptables') which will stop traffic flowing through the
906
bridge.
907
 
908
The easiest way to disable this is by writing zero to all `bridge-nf-*'
909
entries in `/proc/sys/net/bridge'. As superuser the following commands
910
will achieve this.
911
 
912
     cd /proc/sys/net/bridge
913
     for f in bridge-nf-*; do echo 0 > $f; done
914
 
915

916
File: or1ksim.info,  Node: Networking from OpenRISC Linux and BusyBox,  Next: Tearing Down a Bridge,  Prev: Disabling Ethernet Filtering,  Up: Ethernet TUN/TAP Interface
917
 
918 442 julius
2.6.5 Networking from OpenRISC Linux and BusyBox
919 440 jeremybenn
------------------------------------------------
920
 
921
The main use of this style of Ethernet interface to Or1ksim is when
922
running the OpenRISC Linux kernel with BusyBox. The following commands
923
in the BusyBox console window will configure the Ethernet interface
924
(assumed to be `eth0') and bring it up with a DHCP assigned address.
925
 
926
     ifconfig eth0
927
     ifup eth0
928
 
929
At this stage interface to IP addresses will work correctly.
930
 
931
For DNS to work the BusyBox system needs to know where to find a
932
nameserver.  Under BusyBox, `udhcp' does not configure
933
`/etc/resolv.conf' automatically.
934
 
935
The solution is to duplicate the nameserver entry from the
936
`/etc/resolv.conf' file of the host on the BusyBox system. A typical
937
file might be as follows:
938
 
939
     `nameserver 192.168.0.1'
940
 
941
It is convenient to make this permanent within the Linux initramfs. Add
942
the file as `arch/openrisc/support/initramfs/etc/resolv.conf' within
943
the Linux source tree and rebuild `vmlinux'. It will then be present
944
automatically.
945
 
946
One of the most useful functions that is possible is to mount the host
947
file system through NFS. For example, from the BusyBox console:
948
 
949
     mount -t nfs -o nolock 192.168.0.60:/home /mnt
950
 
951
Another useful technique is to telnet into the BusyBox system from the
952
host. This is particularly valuable when a console process locks up,
953
since the `xterm' console will not recognize ctrl-C. Instead the rogue
954
process can be killed from a telnet connection.
955
 
956

957
File: or1ksim.info,  Node: Tearing Down a Bridge,  Prev: Networking from OpenRISC Linux and BusyBox,  Up: Ethernet TUN/TAP Interface
958
 
959 442 julius
2.6.6 Tearing Down a Bridge
960 440 jeremybenn
---------------------------
961
 
962
There is little reason why a bridge should ever need to be torn down,
963
but if desired, the following commands will achieve the effect.
964
 
965
     ifconfig br_n_ down
966
     brctl delbr br_n_
967
 
968
     dhclient eth_x_
969
 
970
As before this will leave a spare `dhclient' process in the background
971
which should be killed.
972
 
973
If desired the TAP interface can be deleted using
974
 
975
     openvpn --rmtun -dev tap_y_
976
 
977
     Caution: The TAP interface should not be in use when running this
978
     command. For example any OpenRISC Linux/BusyBox sessions should be
979
     closed first.
980
 
981

982 460 jeremybenn
File: or1ksim.info,  Node: l.nop Support,  Prev: Ethernet TUN/TAP Interface,  Up: Usage
983
 
984
2.7 l.nop Opcode Support
985
========================
986
 
987
The OpenRISC `l.nop' opcode can take a parameter.  This has no effect
988
on the semantics of the opcode, but can be used to trigger side effect
989
behavior in a simulator.  Within Or1ksim, the following parameters are
990
supported.
991
 
992
`l.nop 0'
993
     The equivalent to `l.nop' with no parameter. Has no side effects.
994
 
995
`l.nop 1'
996
     Execution of Or1ksim is terminated. This is used to implement the
997
     library `exit' functions.
998
 
999
`l.nop 2'
1000
     Report the value in `r3' on the console as a 32-bit hex value.
1001
 
1002
`l.nop 3'
1003
     In earlier versions of Or1ksim this treated `r3' as a pointer to a
1004
     `printf' style format string, and regsiters `r4' through `r8' as
1005
     parameters for that format string.
1006
 
1007
     This opcode is no longer supported, and has no effect if used.
1008
 
1009
`l.nop 4'
1010
     The value in `r3' is printed to standard output as an ASCII
1011
     character.  All library output routines are implemented using this
1012
     opcode.
1013
 
1014
`l.nop 5'
1015
     The statistics counters are reset.
1016
 
1017
`l.nop 6'
1018
     The number of clock ticks since start of execution (a 64-bit
1019
     value) is returned in `r11' (low 32 bits) and `r12' (high 32 bits).
1020
 
1021
`l.nop 7'
1022
     The number of picoseconds per clock cycle is returned in `r11'.
1023
     This is used with `l.nop 6' to implement timing functions.
1024
 
1025
`l.nop 8'
1026
     Instruction tracing is turned on.
1027
 
1028
`l.nop 9'
1029
     Instruction tracing is turned off.
1030
 
1031
 
1032

1033 19 jeremybenn
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
1034
 
1035
3 Configuration
1036
***************
1037
 
1038 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
1039 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
1040 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
1041
the default `sim.cfg' is used.  The file is looked for first in the
1042 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
1043 19 jeremybenn
 
1044
* Menu:
1045
 
1046
* Configuration File Format::
1047
* Simulator Configuration::
1048
* Core OpenRISC Configuration::
1049
* Peripheral Configuration::
1050
 
1051

1052
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
1053
 
1054
3.1 Configuration File Format
1055
=============================
1056
 
1057 346 jeremybenn
The configuration file is a plain text file.  A reference example,
1058
`sim.cfg', is included in the top level directory of the distribution.
1059 19 jeremybenn
 
1060
* Menu:
1061
 
1062
* Configuration File Preprocessing::
1063
* Configuration File Syntax::
1064
 
1065

1066
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
1067
 
1068
3.1.1 Configuration File Preprocessing
1069
--------------------------------------
1070
 
1071 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
1072 19 jeremybenn
`/*' and `*/').
1073
 
1074

1075
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
1076
 
1077
3.1.2 Configuration File Syntax
1078
-------------------------------
1079
 
1080
The configuration file is divided into a series of sections, with the
1081
general form:
1082
 
1083
     section SECTION_NAME
1084
 
1085
       ...
1086
 
1087
     end
1088
 
1089
Sections may also have sub-sections within them (currently only the
1090
ATA/ATAPI disc interface uses this).
1091
 
1092
Within a section, or sub-section are a series of parameter assignments,
1093
one per line, withe the general form
1094
 
1095
       PARAMETER = VALUE
1096
 
1097
Depending on the parameter, the value may be a named value (an
1098
enumeration), an integer (specified in any format acceptable in C) or a
1099 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
1100
mean "true" or "on" and the value "0" to mean "false" or "off".  An
1101 19 jeremybenn
example from a memory section shows each of these
1102
 
1103
     section memory
1104
       type    = random
1105
       pattern = 0x00
1106
       name    = "FLASH"
1107
       ...
1108
     end
1109
 
1110
Many parameters are optional and take reasonable default values if not
1111 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
1112 19 jeremybenn
parameter in `section memory') _must_ be specified.
1113
 
1114
Subsections are introduced by a keyword, with a parameter value (no `='
1115 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
1116 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
1117
 
1118
     section ata
1119
       ...
1120
       device 0
1121
         type    = 1
1122
         file = "FILENAME"
1123
         ...
1124
       enddevice
1125
       ...
1126
     end
1127
 
1128
Some sections (for example `section sim') should appear only once.
1129
Others (for example `section memory' may appear multiple times.
1130
 
1131
Sections may be omitted, _unless they contain parameters which are
1132 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
1133 19 jeremybenn
is optional (for example whether it has a UART), then that
1134 82 jeremybenn
functionality will not be provided.  If the section describes a part of
1135 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
1136
parameters of that section will take their default values.
1137
 
1138
All optional parts of the functionality are always described by
1139
sections including a `enabled' parameter, which can be set to 0 to
1140
ensure that functionality is explicitly omitted.
1141
 
1142
Even if a section is disabled, all its parameters will be read and
1143 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
1144
the Or1ksim command line (*note Interactive Command Line: Interactive
1145 19 jeremybenn
Command Line.).
1146
 
1147
     Tip: It generally clearer to have sections describing _all_
1148
     components, with omitted functionality explicitly indicated by
1149
     setting the `enabled' parameter to 0
1150
 
1151
The following sections describe the various configuration sections and
1152
the parameters which may be set in each.
1153
 
1154

1155
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
1156
 
1157
3.2 Simulator Configuration
1158
===========================
1159
 
1160
* Menu:
1161
 
1162
* Simulator Behavior::
1163
* Verification API Configuration::
1164
* CUC Configuration::
1165
 
1166

1167
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
1168
 
1169
3.2.1 Simulator Behavior
1170
------------------------
1171
 
1172 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
1173
appear only once.  The following parameters may be specified.
1174 19 jeremybenn
 
1175
`verbose = 0|1'
1176 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
1177 19 jeremybenn
 
1178
`debug = 0-9'
1179 82 jeremybenn
 
1180
     higher the value the greater the number of messages.  Default 0.
1181
     Negative values will be treated as 0 (with a warning).  Values
1182
     that are too large will be treated as 9 (with a warning).
1183 19 jeremybenn
 
1184
`profile = 0|1'
1185
     If 1 (true) generate a profiling file using the file specified in
1186 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
1187 19 jeremybenn
 
1188
`prof_file = ``FILENAME'''
1189 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
1190
     Default `sim.profile'.  For backwards compatibility, the
1191
     alternative name `prof_fn' is supported for this parameter, but
1192 346 jeremybenn
     deprecated.  Default `sim.profile'.
1193 19 jeremybenn
 
1194
`mprofile = 0|1'
1195
     If 1 (true) generate a memory profiling file using the file
1196
     specified in the `mprof_file' parameter or otherwise
1197 82 jeremybenn
     `sim.mprofile'.  Default 0.
1198 19 jeremybenn
 
1199 346 jeremybenn
`mprof_file = ``FILENAME'''
1200 19 jeremybenn
     Specifies the file to be used with the `mprofile' parameter.
1201 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
1202 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
1203 346 jeremybenn
     deprecated.  Default `sim.mprofile'.
1204 19 jeremybenn
 
1205
`history = 0|1'
1206 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
1207 19 jeremybenn
 
1208
          Note: Setting this parameter seriously degrades performance.
1209
 
1210
          Note: If this execution flow tracking is enabled, then
1211
          `dependstats' must be enabled in the CPU configuration
1212
          section (*note CPU Configuration: CPU Configuration.).
1213
 
1214
`exe_log = 0|1'
1215 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
1216
     file specified in parameter `exe_log_file'.  Default 0.
1217 19 jeremybenn
 
1218
          Note: Setting this parameter seriously degrades performance.
1219
 
1220
`exe_log_type = default|hardware|simple|software'
1221
     Type of execution log to produce.
1222
 
1223
    `default'
1224 82 jeremybenn
          Produce default output for the execution log.  In the current
1225 19 jeremybenn
          implementation this is the equivalent of `hardware'.
1226
 
1227
    `hardware'
1228
          After each instruction execution, log the number of
1229
          instructions executed so far, the next instruction to execute
1230
          (in hex), the general purpose registers (GPRs), status
1231
          register, exception program counter, exception, effective
1232
          address register and exception status register.
1233
 
1234
    `simple'
1235
          After each instruction execution, log the number of
1236
          instructions executed so far and the next instruction to
1237
          execute, symbolically disassembled.
1238
 
1239
    `software'
1240
          After each instruction execution, log the number of
1241
          instructions executed so far and the next instruction to
1242 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
1243 19 jeremybenn
          each operand to the instruction.
1244
 
1245
 
1246 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
1247 19 jeremybenn
     insensitive) will be treated as the default with a warning.
1248
 
1249
          Note: Execution logs can be _very_ big.
1250
 
1251
`exe_log_start = VALUE'
1252 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
1253 19 jeremybenn
 
1254
`exe_log_end = VALUE'
1255 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
1256
     once started logging will continue until the simulator exits).
1257 19 jeremybenn
 
1258
`exe_log_marker = VALUE'
1259
     Specifies the number of instructions between printing horizontal
1260 82 jeremybenn
     markers.  Default is to produce no markers.
1261 19 jeremybenn
 
1262
`exe_log_file = FILENAME'
1263
     Filename for the execution log filename if `exe_log' is enabled.
1264 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
1265 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
1266
     deprecated.
1267
 
1268 202 julius
`exe_bin_insn_log = 0|1'
1269 346 jeremybenn
     Enable logging of executed instructions to a file in binary format.
1270
     This is helpful for off-line dynamic execution analysis.
1271 202 julius
 
1272 346 jeremybenn
          Note: Execution logs can be _very_ big.  For example, while
1273 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
1274
          size was generated.
1275 202 julius
 
1276
`exe_bin_insn_log_file = FILENAME'
1277
     Filename for the binary execution log filename if
1278
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
1279
 
1280 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
1281 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
1282
     specified, `ps' is assumed.  Default 4000ps (250MHz).
1283 19 jeremybenn
 
1284
 
1285

1286
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
1287
 
1288
3.2.2 Verification API (VAPI) Configuration
1289
-------------------------------------------
1290
 
1291
The Verification API (VAPI) provides a TCP/IP interface to allow
1292 82 jeremybenn
components of the simulation to be controlled externally.  *Note
1293 19 jeremybenn
Verification API: Verification API, for more details.
1294
 
1295 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
1296
section may appear at most once.  The following parameters may be
1297 19 jeremybenn
specified.
1298
 
1299
`enabled = 0|1'
1300
     If 1 (true), verification API is enabled and its server started.
1301
     If 0 (the default), it is disabled.
1302
 
1303
`server_port = VALUE'
1304
     When VAPI is enabled, communication will be via TCP/IP on the port
1305 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
1306 19 jeremybenn
     The default value is 50000.
1307
 
1308 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
1309 19 jeremybenn
          practice suggests users should adopt port values in the
1310 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
1311 19 jeremybenn
 
1312
`log_enabled = 0|1'
1313
     If 1 (true), all VAPI requests and sent commands will be logged.
1314 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
1315 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
1316
 
1317
          Caution: This can generate a substantial amount of file I/O
1318
          and seriously degrade simulator performance.
1319
 
1320
`hide_device_id = 0|1'
1321 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
1322
     device ID.  This feature (when set to 1) is provided for backwards
1323 19 jeremybenn
     compatibility with an old version of VAPI.
1324
 
1325
`vapi_log_file = "FILENAME"'
1326
     Use `filename' as the file for logged data is logging is enabled
1327 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
1328 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
1329
     supported for this parameter, but deprecated.
1330
 
1331
 
1332

1333
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
1334
 
1335
3.2.3 Custom Unit Compiler (CUC) Configuration
1336
----------------------------------------------
1337
 
1338
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1339 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1340
beyond the initial prototype phase.  The configuration parameters are
1341 19 jeremybenn
described here for the record.
1342
 
1343 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1344
appear at most once.  The following parameters may be specified.
1345 19 jeremybenn
 
1346
`memory_order = none|weak|strong|exact'
1347
     This parameter specifies the memory ordering required:
1348
 
1349
    `memory_order=none'
1350
          Different memory ordering, even if there are dependencies.
1351
          Bursts can be made, width can change.
1352
 
1353 346 jeremybenn
    `memory_order=weak'
1354 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1355 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1356
          change.
1357
 
1358 346 jeremybenn
    `memory_order=strong'
1359 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1360 19 jeremybenn
 
1361 346 jeremybenn
    `memory_order=exact'
1362 19 jeremybenn
          Exactly the same memory ordering and widths.
1363
 
1364
 
1365 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1366 19 jeremybenn
     orderings are ignored with a warning.
1367
 
1368
`calling_convention = 0|1'
1369 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1370 19 jeremybenn
     (the default), they may use other convenitions.
1371
 
1372
`enable_bursts = 0 | 1'
1373 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1374 19 jeremybenn
     not detected.
1375
 
1376
`no_multicycle = 0 | 1'
1377 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1378
     (the default), multicycle logic paths will be generated.
1379 19 jeremybenn
 
1380
`timings_file = "FILENAME"'
1381 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1382
     default value is `"virtex.tim"'.  For backwards compatibility, the
1383 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1384
     deprecated.
1385
 
1386
 
1387

1388
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1389
 
1390
3.3 Configuring the OpenRISC Architectural Components
1391
=====================================================
1392
 
1393
* Menu:
1394
 
1395
* CPU Configuration::
1396
* Memory Configuration::
1397
* Memory Management Configuration::
1398
* Cache Configuration::
1399
* Interrupt Configuration::
1400
* Power Management Configuration::
1401
* Branch Prediction Configuration::
1402
* Debug Interface Configuration::
1403
 
1404

1405
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1406
 
1407
3.3.1 CPU Configuration
1408
-----------------------
1409
 
1410 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1411
appear only once.  At present Or1ksim does not model multi-CPU systems.
1412 19 jeremybenn
The following parameters may be specified.
1413
 
1414
`ver = VALUE'
1415
 
1416
`cfg = VALUE'
1417
 
1418
`rev = VALUE'
1419
     The values are used to form the corresponding fields in the `VR'
1420 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1421 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1422
     and `cfg', 6 bits for `rev').
1423
 
1424
`upr = VALUE'
1425
     Used as the value of the Unit Present Register (UPR) Special
1426 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1427 19 jeremybenn
     i.e.
1428
        * UPR present (0x00000001)
1429
 
1430
        * Data cache present (0x00000002)
1431
 
1432
        * Instruction cache present (0x00000004)
1433
 
1434
        * Data MMY present (0x00000008)
1435
 
1436
        * Instruction MMU present (0x00000010)
1437
 
1438
        * Debug unit present (0x00000040)
1439
 
1440
        * Power management unit present (0x00000100)
1441
 
1442
        * Programmable interrupt controller present (0x00000200)
1443
 
1444
        * Tick timer present (0x00000400)
1445
 
1446
     However, with the exection of the UPR present (0x00000001) and tick
1447
     timer present, the various fields will be modified with the values
1448
     specified in their corresponding configuration sections.
1449
 
1450
`cfgr = VALUE'
1451
     Sets the CPU configuration register (Special Purpose Register 2) to
1452 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1453
     instruction set.  Attempts to set any other value are accepted, but
1454 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1455
 
1456
`sr = VALUE'
1457
     Sets the supervision register Special Purpose Register (SPR 0x11)
1458 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1459 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1460
 
1461 98 jeremybenn
          Note: This is particularly useful when an image is held in
1462
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1463
          so that interrupt vectors are basedf at 0xf0000000, rather
1464
          than 0x0.
1465
 
1466 19 jeremybenn
`superscalar = 0|1'
1467 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1468 19 jeremybenn
     0.
1469
 
1470
     In the current simulator, the only functional effect of superscalar
1471
     mode is to affect the calculation of the number of cycles taken to
1472
     execute an instruction.
1473
 
1474
          Caution: The code for this does not appear to be complete or
1475
          well tested, so users are advised not to use this option.
1476
 
1477
`hazards = 0|1'
1478 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1479
     value is 0.
1480 19 jeremybenn
 
1481
     In the current simulator, the only functional effect is to cause
1482
     logging of hazard waiting information if the CPU is superscalar.
1483
     However nowhere in the simulator is this data actually computed,
1484
     so the net result is probably to have no effect.
1485
 
1486
     if harzards are tracked, current hazards can be displayed using the
1487
     simulator's `r' command.
1488
 
1489
          Caution: The code for this does not appear to be complete or
1490
          well tested, so users are advised not to use this option.
1491
 
1492
`dependstats = 0|1'
1493 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1494
     value 0.
1495 19 jeremybenn
 
1496
     If these values are calculated, the depencies can be displayed
1497
     using the simulator's `stat' command.
1498
 
1499
          Note: This field must be enabled, if execution execution flow
1500
          tracking (field `history') has been requested in the simulator
1501
          configuration section (*note Simulator Behavior: Simulator
1502
          Behavior.).
1503
 
1504
`sbuf_len = VALUE'
1505
     The length of the store buffer is set to VALUE, which must be no
1506 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1507
     warning.  Negative values will be treated as 0 with a warning.
1508
     Use 0 to disable the store buffer.
1509 19 jeremybenn
 
1510
     When the store buffer is active, stores are accumulated and
1511
     committed when I/O is idle.
1512
 
1513 100 julius
`hardfloat = 0|1'
1514 346 jeremybenn
     If 1, hardfloat instructions are enabled.  Default value 0.
1515 19 jeremybenn
 
1516 104 jeremybenn
 
1517 19 jeremybenn

1518
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1519
 
1520
3.3.2 Memory Configuration
1521
--------------------------
1522
 
1523 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1524 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1525 19 jeremybenn
 
1526 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1527 385 jeremybenn
     controller.  If a memory controller is enabled, then appropriate
1528
     initalization code must be provided.  The section describing
1529
     memory controller configuration describes the steps necessary for
1530
     using smaller or larger memory sections (*note Memory Controller
1531
     Configuration: Memory Controller Configuration.).
1532 98 jeremybenn
 
1533 385 jeremybenn
     The "uClibc" startup code initalizes a memory controller, assumed
1534
     to be mapped at 0x93000000.  If a memory controller is _not_
1535
     enabled, then the standard C library code will generate memory
1536
     access errors.  The solution is to declare an additional writable
1537
     memory block, mimicing the memory controller's register bank as
1538
     follows.
1539 98 jeremybenn
 
1540
          section memory
1541
            pattern = 0x00
1542
            type = unknown
1543
            name = "MC shadow"
1544
            baseaddr = 0x93000000
1545
            size     = 0x00000080
1546
            delayr = 2
1547
            delayw = 4
1548
          end
1549
 
1550
 
1551
The following parameters may be specified.
1552
 
1553 418 julius
`type=random|pattern|unknown|zero|exitnops'
1554 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1555 19 jeremybenn
     default value is `unknown'.
1556
 
1557
    `random'
1558 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1559 19 jeremybenn
          random generator may be set using the `random_seed' field in
1560
          this section (see below), thus ensuring the same "random"
1561
          values are used each time.
1562
 
1563
    `pattern'
1564
          Set the memory values to be a pattern value, which is set
1565
          using the `pattern' field in this section (see below).
1566
 
1567
    `unknown'
1568 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1569 240 julius
          This option will yield faster initialization of the
1570 346 jeremybenn
          simulator.  This is the default.
1571 19 jeremybenn
 
1572
    `zero'
1573 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1574 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1575
          such.
1576
 
1577 420 jeremybenn
               Note: As a consequence, if the `pattern' field is
1578
               _subsequently_ specified in this section, the value in
1579
               that field will be used instead of zero to initialize
1580
               the memory.
1581
 
1582 418 julius
    `exitnops'
1583
          Set the memory values to be an instruction used to signal end
1584
          of simulation. This is useful for causing immediate end of
1585
          simulation when PC corruption occurs.
1586
 
1587 19 jeremybenn
 
1588
`random_seed = VALUE'
1589 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1590 19 jeremybenn
     has any effect for memory type `random'.
1591
 
1592
     The default value is -1, which means the seed will be set from a
1593
     call to the `time' function, thus ensuring different random values
1594 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1595 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1596
     values used in any particular run.
1597
 
1598
`pattern = VALUE'
1599 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1600
     default value is 0.  This only has any effect for memory type
1601
     `pattern'.  The least significant 8 bits of this value is used to
1602
     initialize each byte.  More than 8 bits can be specified, but will
1603 19 jeremybenn
     ignored with a warning.
1604
 
1605
          Tip: The default value, is equivalent to setting the memory
1606 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1607 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1608
          and not specifying a value for `pattern'.
1609
 
1610
`baseaddr = VALUE'
1611 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1612 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1613
     The default value is 0.
1614
 
1615
`size = VALUE'
1616 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1617
     be a multiple of 4 (i.e.  word aligned).  The default value is
1618
     1024.
1619 19 jeremybenn
 
1620
          Note: When allocating memory, the simulator will allocate the
1621
          nearest 2^n bytes greater than or equal to VALUE, and will not
1622
          notice memory misses in any part of the memory between VALUE
1623
          and the amount allocated.
1624
 
1625
          As a consequence users are strongly recommended to specify
1626 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1627 19 jeremybenn
          amount of memory is required, it should be specified as
1628
          separate, contiguous blocks, each of which is a power of 2 in
1629
          size.
1630
 
1631
`name = "TEXT"'
1632 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1633
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1634 19 jeremybenn
     `"anonymous memory block"'.
1635
 
1636
          Note: It is not clear that this information is currently ever
1637 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1638 19 jeremybenn
          command of the simulator ignores it.
1639
 
1640
`ce = VALUE'
1641 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1642 19 jeremybenn
     instance should have a unique chip enable index, which should be
1643 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1644 19 jeremybenn
     controller when identifying different memory instances.
1645
 
1646 346 jeremybenn
     There is no requirement to set `ce' if a memory controller is not
1647
     enabled.  The default value is -1 (invalid).
1648 19 jeremybenn
 
1649
`mc = VALUE'
1650 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1651 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1652
     for a memory controller (*note Memory Controller Configuration:
1653
     Memory Controller Configuration.).
1654
 
1655 346 jeremybenn
     There is no requirement to set `mc' if a memory controller is not
1656
     enabled.  Default value is 0, which is also the default value of a
1657 98 jeremybenn
     memory controller `index' field.  This is suitable therefore for
1658
     designs with just one memory controller.
1659 19 jeremybenn
 
1660
`delayr = VALUE'
1661 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1662
     memory does not support reading.  Default value 1.  The simulator
1663 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1664
     count when reading from main memory.
1665
 
1666
`delayw = VALUE'
1667 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1668
     memory does not support writing.  Default value 1.  The simulator
1669 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1670
     count when writing to main memory.
1671
 
1672
`log = "FILE"'
1673
     If specified, `file' names a file for all memory accesses to be
1674 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1675 19 jeremybenn
     that the memory is not logged.
1676
 
1677
 
1678

1679
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1680
 
1681
3.3.3 Memory Management Configuration
1682
-------------------------------------
1683
 
1684
Memory Management Unit (MMU) configuration is described in `section
1685
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1686 82 jeremybenn
Each section should appear at most once.  The following parameters may
1687 19 jeremybenn
be specified.
1688
 
1689
`enabled = 0|1'
1690
     If 1 (true), the data or instruction (as appropriate) MMU is
1691 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1692 19 jeremybenn
 
1693
`nsets = VALUE'
1694
     Sets the number of data or instruction (as appropriate) TLB sets to
1695 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1696
     which do not fit these criteria are ignored with a warning.  The
1697 19 jeremybenn
     default value is 1.
1698
 
1699
`nways = VALUE'
1700
     Sets the number of data or instruction (as appropriate) TLB ways to
1701 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1702
     this range are ignored with a warning.  The default value is 1.
1703 19 jeremybenn
 
1704
`pagesize = VALUE'
1705
     The data or instruction (as appropriate) MMU page size is set to
1706 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1707
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1708 19 jeremybenn
 
1709
`entrysize = VALUE'
1710
     The data or instruction (as appropriate) MMU entry size is set to
1711 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1712
     of 2 are ignored with a warning.  The default value is 1.
1713 19 jeremybenn
 
1714
          Note: Or1ksim does not appear to use the `entrysize' parameter
1715 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1716 19 jeremybenn
          not seem to matter.
1717
 
1718
`ustates = VALUE'
1719
     The number of instruction usage states for the data or instruction
1720
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1721 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1722 19 jeremybenn
     value is 2.
1723
 
1724
          Note: Or1ksim does not appear to use the `ustates' parameter
1725 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1726 19 jeremybenn
          not seem to matter.
1727
 
1728
`hitdelay = VALUE'
1729
     Set the number of cycles a data or instruction (as appropriate) MMU
1730 82 jeremybenn
     hit costs.  Default value 1.
1731 19 jeremybenn
 
1732
`missdelay = VALUE'
1733
     Set the number of cycles a data or instruction (as appropriate) MMU
1734 82 jeremybenn
     miss costs.  Default value 1.
1735 19 jeremybenn
 
1736
 
1737

1738
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1739
 
1740
3.3.4 Cache Configuration
1741
-------------------------
1742
 
1743
Cache configuration is described in `section dc' (for the data cache)
1744 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1745
appear at most once.  The following parameters may be specified.
1746 19 jeremybenn
 
1747
`enabled = 0|1'
1748
     If 1 (true), the data or instruction (as appropriate) cache is
1749 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1750 19 jeremybenn
 
1751
`nsets = VALUE'
1752
     Sets the number of data or instruction (as appropriate) cache sets
1753
     to VALUE, which must be a power of two, not exceeding
1754
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1755 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1756
     both defined in the code to be 1024).  The default value is 1.
1757 19 jeremybenn
 
1758
`nways = VALUE'
1759
     Sets the number of data or instruction (as appropriate) cache ways
1760
     to VALUE, which must be a power of two, not exceeding
1761
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1762 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1763
     both defined in the code to be 32).  The default value is 1.
1764 19 jeremybenn
 
1765
`blocksize = VALUE'
1766
     The data or instruction (as appropriate) cache block size is set to
1767 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1768 19 jeremybenn
 
1769
`ustates = VALUE'
1770
     The number of instruction usage states for the data or instruction
1771
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1772
     The default value is 2.
1773
 
1774
`hitdelay = VALUE'
1775 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1776
     cache hit costs.  Default value 1.
1777 19 jeremybenn
 
1778
`missdelay = VALUE'
1779 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1780
     cache miss costs.  Default value 1.
1781 19 jeremybenn
 
1782
`load_hitdelay = VALUE'
1783 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1784
     costs.  Default value 2.
1785 19 jeremybenn
 
1786
`load_missdelay = VALUE'
1787 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1788
     miss costs.  Default value 2.
1789 19 jeremybenn
 
1790
`store_hitdelay = VALUE'
1791 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1792
     costs.  Default value 0.
1793 19 jeremybenn
 
1794
`store_missdelay = VALUE'
1795 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1796
     miss costs.  Default value 0.
1797 19 jeremybenn
 
1798
 
1799

1800
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1801
 
1802
3.3.5 Interrupt Configuration
1803
-----------------------------
1804
 
1805
Programmable Interrupt Controller (PIC) configuration is described in
1806 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1807
mechanism for handling multiple interrupt controllers.  The following
1808 19 jeremybenn
parameters may be specified.
1809
 
1810
`enabled = 0|1'
1811 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1812
 
1813 19 jeremybenn
 
1814
`edge_trigger = 0|1'
1815
     If 1 (true, the default), the programmable interrupt controller is
1816 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1817 19 jeremybenn
 
1818 432 jeremybenn
     The library interface (*note Simulator Library: Simulator Library.)
1819
     provides different functions for setting the different types of
1820
     interrupt, and a function to clear level sensitive interrupts. Edge
1821
     sensitive interrupts must be cleared by clearing the corresponding
1822
     bit in the PICSR SPR.
1823 19 jeremybenn
 
1824 432 jeremybenn
     Internal functions to set and clear interrupts are also provided
1825
     for peripherals implemented within Or1ksim. *Note Interrupts
1826
     Internal: Interrupts Internal for more details.
1827 430 julius
 
1828 432 jeremybenn
`use_nmi = 0|1'
1829
     If 1 (true, the default), interrupt lines 0 and 1 are
1830
     non-maskable. In other words the least significant 2 bits of the
1831
     PICMR SPR are hard-wired to 1.  If 0 (false), all interrupt lines
1832
     are treated as equivalent.
1833 430 julius
 
1834 432 jeremybenn
          Note: These are not non-maskable in the true sense that they
1835
          will pre-empt other interrupts.  Rather they can never be
1836
          masked out using the PICMR register. It is up the interrupt
1837
          exception handler to give these interrupt lines priority, and
1838
          indeed to decide on the priority order in general.
1839 430 julius
 
1840 432 jeremybenn
 
1841 19 jeremybenn

1842
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1843
 
1844
3.3.6 Power Management Configuration
1845
------------------------------------
1846
 
1847 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1848 19 jeremybenn
(which only happens when the power management unit is enabled) of
1849
setting the different bits in the power management Special Purpose
1850
Register (PMR, SPR 0x4000) is
1851
 
1852
`SDF (bit mask 0x0000000f)'
1853
     No effect - these bits are ignored
1854
 
1855
`DME (bit mask 0x00000010)'
1856
`SME (bit mask 0x00000020)'
1857
     Both these bits cause the processor to stop executing
1858 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1859 19 jeremybenn
     VAPI etc) carry on as normal.
1860
 
1861
`DCGE (bit mask 0x00000004)'
1862
     No effect - this bit is ignored
1863
 
1864
`SUME (bit mask 0x00000008)'
1865
     Enabling this bit causes a message to be printed, advising that the
1866
     processor is suspending and the simulator exits.
1867
 
1868
 
1869
On reset all bits are cleared.
1870
 
1871 82 jeremybenn
Power management configuration is described in `section pm'.  This
1872
section may appear at most once.  The following parameter may be
1873 19 jeremybenn
specified.
1874
 
1875
`enabled = 0|1'
1876 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1877
     is disabled.
1878 19 jeremybenn
 
1879
 
1880

1881
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1882
 
1883
3.3.7 Branch Prediction Configuration
1884
-------------------------------------
1885
 
1886
From examining the code base, it seems the branch prediction function
1887 82 jeremybenn
is not fully implemented.  At present the functionality seems
1888
restricted to collection of statistics.
1889 19 jeremybenn
 
1890 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1891
section may appear at most once.  The following parameters may be
1892 19 jeremybenn
specified.
1893
 
1894
`enabled = 0|1'
1895 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1896 19 jeremybenn
     is disabled.
1897
 
1898
`btic = 0|1'
1899
     If 1 (true), the branch target instruction cache model is enabled.
1900
     If 0 (the default), it is disabled.
1901
 
1902
`sbp_bf_fwd = 0|1'
1903 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1904 19 jeremybenn
 
1905
     instruction.
1906
 
1907
`sbp_bnf_fwd = 0|1'
1908 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1909
     If 0 (the default), do not use forward prediction for this
1910 19 jeremybenn
     instruction.
1911
 
1912
`hitdelay = VALUE'
1913 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1914 19 jeremybenn
     value 0.
1915
 
1916
`missdelay = VALUE'
1917 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1918 19 jeremybenn
     value 0.
1919
 
1920
 
1921

1922
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1923
 
1924
3.3.8 Debug Interface Configuration
1925
-----------------------------------
1926
 
1927
The debug unit and debug interface configuration is described in
1928 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1929 19 jeremybenn
parameters may be specified.
1930
 
1931
`enabled = 0|1'
1932 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1933 19 jeremybenn
     disabled.
1934
 
1935
          Note: This enables the functionality of the debug unit (its
1936 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1937
          external interface to the debug unit.  For that, see
1938 235 jeremybenn
          `rsp_enabled' below.
1939 19 jeremybenn
 
1940
`rsp_enabled = 0|1'
1941
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1942
     provding an interface to an external GNU debugger, using the port
1943
     specified in the `rsp_port' field (see below), or the
1944 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1945 19 jeremybenn
     not started, and no external interface is provided.
1946
 
1947
     For more detailed information on the interface to the GNU Debugger
1948
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1949
     Practical Experience with the OpenRISC 1000 Architecture', by
1950
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1951
 
1952
`rsp_port = VALUE'
1953
     VALUE specifies the port to be used for the GDB "Remote Serial
1954 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1955
     51000.  If the value 0 is specified, Or1ksim will instead look for
1956 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1957
 
1958
          Tip: There is no registered port for Or1ksim "Remote Serial
1959 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1960
          users should adopt port values in the "Dynamic" or "Private"
1961
          port range, i.e.  49152-65535.
1962 19 jeremybenn
 
1963
`vapi_id = VALUE'
1964
     VALUE specifies the value of the Verification API (VAPI) base
1965 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1966 19 jeremybenn
     Verification API, for more details.
1967
 
1968
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1969
     JTAG protocol transactions will be logged to the VAPI log file, if
1970 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1971
     the debug unit.  No VAPI commands are sent, nor requests handled.
1972 19 jeremybenn
 
1973
 
1974

1975
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1976
 
1977
3.4 Configuring Memory Mapped Peripherals
1978
=========================================
1979
 
1980 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1981 19 jeremybenn
(unlike other components) by default they are enabled.
1982
 
1983
* Menu:
1984
 
1985
* Memory Controller Configuration::
1986
* UART Configuration::
1987
* DMA Configuration::
1988
* Ethernet Configuration::
1989
* GPIO Configuration::
1990
* Display Interface Configuration::
1991
* Frame Buffer Configuration::
1992
* Keyboard Configuration::
1993
* Disc Interface Configuration::
1994
* Generic Peripheral Configuration::
1995
 
1996

1997
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1998
 
1999
3.4.1 Memory Controller Configuration
2000
-------------------------------------
2001
 
2002
The memory controller used in Or1ksim is the component implemented at
2003 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
2004 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
2005 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
2006
memory mapped component, which resides on the main OpenRISC Wishbone
2007
data bus.
2008 19 jeremybenn
 
2009 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
2010 19 jeremybenn
section may appear multiple times, specifying multiple memory
2011 98 jeremybenn
controllers.
2012 19 jeremybenn
 
2013 385 jeremybenn
     Warning: There are known to be problems with the current memory
2014
     controller, which currently is not included in the regression test
2015
     suite. Users are advised not to use the memory controller in the
2016
     current release.
2017 98 jeremybenn
 
2018 385 jeremybenn
     Caution: There is no initialization code in the standard "newlib"
2019
     library.
2020
 
2021
     The standard "uClibc" library assumes a memory controller mapped
2022
     at 0x93000000 and will initialize the memory controller to expect
2023
     64MB memory blocks, and any memory declarations _must_ reflect
2024
     this.
2025
 
2026 98 jeremybenn
     If smaller memory blocks are declared with a memory controller,
2027
     then sufficient memory will not be allocated by Or1ksim, but out of
2028 346 jeremybenn
     range memory accesses will not be trapped.  For example declaring a
2029 98 jeremybenn
     memory section from 0-4MB with a memory controller enabled would
2030
     mean that accesses between 4MB and 64MB would be permitted, but
2031
     having no allocated memory would likely cause a segmentation fault.
2032
 
2033
     If the user is determined to use smaller memories with the memory
2034
     controller, then custom initialization code must be provided, to
2035
     ensure the memory controller traps out-of-memory accesses.
2036
 
2037
The following parameters may be specified.
2038
 
2039 19 jeremybenn
`enabled = 0|1'
2040 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
2041
     0, it is disabled.
2042 19 jeremybenn
 
2043
          Note: The memory controller can effectively also be disabled
2044
          by setting an appropriate power on control register value
2045 82 jeremybenn
          (see below).  However this should only be used if it is
2046 19 jeremybenn
          desired to specifically model this behavior of the memory
2047
          controller, not as a way of disabling the memory controller
2048
          in general.
2049
 
2050
`baseaddr = VALUE'
2051
     Set the base address of the memory controller's memory mapped
2052 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2053 19 jeremybenn
     sensible value.
2054
 
2055
     The memory controller has a 7 bit address bus, with a total of 19
2056
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
2057
     addresses 0x50 through 0x7c are not used).
2058
 
2059
`poc = VALUE'
2060
     Specifies the value of the power on control register, The least
2061
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
2062
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
2063
     the type of memory connected (use 0 for a disabled interface, 1
2064
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
2065
     devices).
2066
 
2067
     If other bits are specified, they are ignored with a warning.
2068
 
2069
          Caution: The default value, 0, corresponds to a disabled
2070
          8-bit bus, and is likely not the most suitable value
2071
 
2072
`index = VALUE'
2073
     Specify the index of this memory controller amongst all the memory
2074 82 jeremybenn
     controllers.  This value should be unique for each memory
2075 19 jeremybenn
     controller, and is used to associate specific memories with the
2076
     controller, through the `mc' field in the `section memory'
2077
     configuration (*note Memory Configuration: Memory Configuration.).
2078
 
2079
     The default value, 0, is suitable when there is only one memory
2080
     controller.
2081
 
2082
 
2083

2084
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
2085
 
2086
3.4.2 UART Configuration
2087
------------------------
2088
 
2089
The UART implemented in Or1ksim follows the specification of the
2090 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
2091 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
2092
 
2093
The component provides a number of interfaces to emulate the behavior
2094
of an external terminal connected to the UART.
2095
 
2096 82 jeremybenn
UART configuration is described in `section uart'.  This section may
2097
appear multiple times, specifying multiple UARTs.  The following
2098 19 jeremybenn
parameters may be specified.
2099
 
2100
`enabled = 0|1'
2101 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
2102 19 jeremybenn
     disabled.
2103
 
2104
`baseaddr = VALUE'
2105
     Set the base address of the UART's memory mapped registers to
2106 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2107 19 jeremybenn
 
2108
     The UART has a 3 bit address bus, with a total of 8 8-bit
2109
     registers, at addresses 0x0 through 0x7.
2110
 
2111
`channel = "TYPE:ARGS"'
2112
     Specify the channel representing the terminal connected to the UART
2113
     Rx & Tx pins.
2114
 
2115
    `channel="file:`rxfile',`txfile'"'
2116
          Read input characters from the file `rxfile' and write output
2117
          characters to the file `txfile' (which will be created if
2118
          required).
2119
 
2120
    `channel="xterm:ARGS"'
2121
          Create an xterm on startup, write UART Tx traffic to the
2122
          xterm and take Rx traffic from the keyboard when the xterm
2123 82 jeremybenn
          window is selected.  Additional arguments to the xterm
2124
          command (for example specifying window size may be specified
2125
          in ARGS, or this may be left blank.
2126 19 jeremybenn
 
2127
    `channel="tcp:VALUE"'
2128
          Open the TCP/IP port specified by VALUE and read and write
2129
          UART traffic from and to it.
2130
 
2131
          Typically a telnet session is connected to the other end of
2132
          this port.
2133
 
2134
               Tip: There is no registered port for Or1ksim telnet UART
2135 82 jeremybenn
               connection.  Priviledged access is required to read
2136 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
2137 346 jeremybenn
               Instead users should use port values in the "Dynamic" or
2138
               "Private" port range, i.e.  49152-65535.
2139 19 jeremybenn
 
2140
    `channel="fd:`rxfd',`txfd'"'
2141
          Read and write characters from and to the existing open
2142
          numerical file descriptors, file `rxfd' and `txfd'.
2143
 
2144
    `channel="tty:device=/dev/ttyS0,baud=9600"'
2145
          Read and write characters from and to a physical serial port.
2146 346 jeremybenn
          The precise device (shown here as `/dev/ttyS0') may vary from
2147
          machine to machine.
2148 19 jeremybenn
 
2149
 
2150
     The default value for this field is `"xterm:"'.
2151
 
2152
`irq = VALUE'
2153 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
2154 19 jeremybenn
 
2155
`16550 = 0|1'
2156 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
2157
     default), it has the functionality of a 16450.  The principal
2158 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
2159
 
2160
`jitter = VALUE'
2161
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
2162 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
2163 19 jeremybenn
 
2164
          Note: This functionality has yet to be implemented, so this
2165
          parameter has no effect.
2166
 
2167
`vapi_id = VALUE'
2168
     VALUE specifies the value of the Verification API (VAPI) base
2169 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
2170 19 jeremybenn
     Verification API, for more details, which details the use of the
2171
     VAPI with the UART.
2172
 
2173
 
2174

2175
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
2176
 
2177
3.4.3 DMA Configuration
2178
-----------------------
2179
 
2180
The DMA controller used in Or1ksim is the component implemented at
2181 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
2182 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
2183 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
2184
memory mapped component, which resides on the main OpenRISC Wishbone
2185
data bus.  The present implementation is incomplete, intended only to
2186
support the Ethernet interface (*note Ethernet Configuration::),
2187
although the Ethernet interface is not yet completed.
2188 19 jeremybenn
 
2189 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
2190
appear multiple times, specifying multiple DMA controllers.  The
2191 19 jeremybenn
following parameters may be specified.
2192
 
2193
`enabled = 0|1'
2194 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
2195
     it is disabled.
2196 19 jeremybenn
 
2197
`baseaddr = VALUE'
2198
     Set the base address of the DMA's memory mapped registers to
2199 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2200 19 jeremybenn
 
2201
     The DMA controller has a 10 bit address bus, with a total of 253
2202 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
2203
     0x010 control the overall behavior of the DMA controller.  There
2204
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
2205
     channels available.  Addresses 0x014 through 0x01c are not used.
2206 19 jeremybenn
 
2207
`irq = VALUE'
2208 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
2209 19 jeremybenn
     0.
2210
 
2211
`vapi_id = VALUE'
2212
     VALUE specifies the value of the Verification API (VAPI) base
2213 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
2214 19 jeremybenn
     API: Verification API, for more details, which details the use of
2215
     the VAPI with the DMA controller.
2216
 
2217
 
2218

2219
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
2220
 
2221
3.4.4 Ethernet Configuration
2222
----------------------------
2223
 
2224 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
2225
section may appear multiple times, specifying multiple Ethernet
2226
interfaces.  The following parameters may be specified.
2227 19 jeremybenn
 
2228 440 jeremybenn
The Ethernet MAC used in Or1ksim corresponds to the Verilog
2229
implementation in project "ethmac". It's source code can be found in
2230
the top level SVN directory, `ethmac'.  It also forms part of the
2231
OpenRISC reference SoC, ORPSoC.  It is described in the document
2232
`Ethernet IP Core Specification' by Igor Mohor, which can be found in
2233
the `doc' subdirectory.  It is a memory mapped component, which resides
2234
on the main OpenRISC Wishbone data bus.
2235
 
2236 19 jeremybenn
`enabled = 0|1'
2237 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
2238
     is disabled.
2239 19 jeremybenn
 
2240
`baseaddr = VALUE'
2241
     Set the base address of the MAC's memory mapped registers to
2242 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2243 19 jeremybenn
 
2244
     The Ethernet MAC has a 7-bit address bus, with a total of 21
2245 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
2246 19 jeremybenn
 
2247
          Note: The Ethernet specification describes a Tx control
2248 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
2249
          is not implemented in the Or1ksim model.
2250 19 jeremybenn
 
2251
`dma = VALUE'
2252
     VALUE specifies the DMA controller with which this Ethernet is
2253 82 jeremybenn
     associated.  The default value is 0.
2254 19 jeremybenn
 
2255
          Note: Support for external DMA is not provided in the current
2256 82 jeremybenn
          implementation, and this value is ignored.  In any case there
2257 19 jeremybenn
          is no equivalent field to which this can be matched in the
2258
          current DMA component implementation (*note DMA
2259
          Configuration: DMA Configuration.).
2260
 
2261
`irq = VALUE'
2262 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
2263 19 jeremybenn
 
2264 440 jeremybenn
`rtx_type = "file"|"tap"'
2265
     Specifies whether to use a TUN/TAP interface or file interface
2266
     (the default) to model the external connection of the Ethernet.
2267 19 jeremybenn
 
2268 440 jeremybenn
     If a TUN/TAP interface is requested, Ethernet packets will be sent
2269
     and received through the pesistent TAP interface specified in
2270
     parameter `tap_dev' (see below).
2271 19 jeremybenn
 
2272 440 jeremybenn
     More details on configuring the TUN/TAP interface are given in the
2273
     Usage section (*note Ethernet TUN/TAP Interface: Ethernet TUN/TAP
2274
     Interface.).
2275 19 jeremybenn
 
2276 440 jeremybenn
     If a file interface (the default), is requested, the Ethernet will
2277
     be modelled by reading and writing from and to the files specified
2278
     in the `rxfile' and `txfile' parameters (see below).
2279
 
2280
          Caution: If a file interface is specified, Or1ksim will
2281
          terminate once the receive file specified by `rxfile' is
2282
          exhausted.
2283
 
2284 19 jeremybenn
`rx_channel = RXVALUE'
2285
`tx_channel = TXVALUE'
2286
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
2287 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
2288 19 jeremybenn
 
2289
          Note: As noted above, support for external DMA is not
2290
          provided in the current implementation, and so these values
2291
          are ignored.
2292
 
2293
`rxfile = "RXFILE"'
2294
`txfile = "TXFILE"'
2295
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
2296
     as input and TXFILE specifies the fie to use as output.
2297
 
2298 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
2299
     packet length (32 bits), followed by that many bytes of data.
2300
     Once the input file is empty, the Ethernet MAC behaves as though
2301
     there were no data on the Ethernet.  The default values of these
2302 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
2303
 
2304 82 jeremybenn
     The input file must exist and be readable.  The output file must be
2305
     writable and will be created if necessary.  If either of these
2306 19 jeremybenn
     conditions is not met, a warning will be given.
2307
 
2308 440 jeremybenn
          Caution: Or1ksim will terminate once the RXFILE is exhausted.
2309 19 jeremybenn
 
2310 440 jeremybenn
`tap_dev = "TAP"'
2311
     When `rtx_type' is `"tap"' (see above), TAP_DEV specifies the TAP
2312
     device to use for communication.  This should be a persistent TAP
2313
     device configured for the system (*note Ethernet TUN/TAP
2314
     Interface: Ethernet TUN/TAP Interface.)
2315
 
2316 451 jeremybenn
`phy_addr = VALUE'
2317
     VALUE specifies the address for emulated ethernet PHY (default 0).
2318
     If there are multiple Ethernet peripherals, they should each have a
2319
     different PHY value.
2320
 
2321
`dummy_crc = 0|1'
2322
     If 1 (true, the default), the length of the data transferred to
2323
     the core will be increased by 4 bytes, as though the CRC were
2324
     included.
2325
 
2326
          Note: This is for historical consistency with the OpenRISC
2327
          Ethernet hardware MAC, which passes on the CRC in the data
2328
          packet. This is unusual behavior for a MAC, but the OpenRISC
2329
          Linux device drivers have been written to expect it.
2330
 
2331
`phy_addr = VALUE'
2332
     VALUE specifies the address for emulated ethernet PHY (default 0).
2333
     If there are multiple Ethernet peripherals, they should each have a
2334
     different PHY value.
2335
 
2336 19 jeremybenn
`vapi_id = VALUE'
2337
     VALUE specifies the value of the Verification API (VAPI) base
2338 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
2339 19 jeremybenn
     Verification API, for more details, which details the use of the
2340
     VAPI with the DMA controller.
2341
 
2342
 
2343

2344
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
2345
 
2346
3.4.5 GPIO Configuration
2347
------------------------
2348
 
2349
The GPIO used in Or1ksim is the component implemented at OpenCores, and
2350 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
2351 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
2352 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
2353 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
2354
 
2355 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
2356
appear multiple times, specifying multiple GPIO devices.  The following
2357 19 jeremybenn
parameters may be specified.
2358
 
2359
`enabled = 0|1'
2360 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
2361 19 jeremybenn
     disabled.
2362
 
2363
`baseaddr = VALUE'
2364
     Set the base address of the GPIO's memory mapped registers to
2365 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2366 19 jeremybenn
 
2367
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
2368
     registers, although the number of bits that are actively used
2369 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
2370 19 jeremybenn
 
2371
`irq = VALUE'
2372 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
2373 19 jeremybenn
 
2374
`vapi_id = VALUE'
2375
     VALUE specifies the value of the Verification API (VAPI) base
2376 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2377 19 jeremybenn
     Verification API, for more details, which details the use of the
2378 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2379 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2380
     but deprecated.
2381
 
2382
 
2383

2384
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2385
 
2386
3.4.6 Display Interface Configuration
2387
-------------------------------------
2388
 
2389
Or1ksim models a VGA interface to an external monitor.  The VGA
2390
controller used in Or1ksim is the component implemented at OpenCores,
2391 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2392 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2393 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2394 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2395
which resides on the main OpenRISC Wishbone data bus.
2396 19 jeremybenn
 
2397
The current implementation provides only functionality to dump the
2398
screen to a file at intervals.
2399
 
2400 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2401 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2402
The following parameters may be specified.
2403
 
2404
`enabled = 0|1'
2405 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2406 19 jeremybenn
     disabled.
2407
 
2408
`baseaddr = VALUE'
2409
     Set the base address of the VGA controller's memory mapped
2410 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2411 19 jeremybenn
     sensible value.
2412
 
2413
     The VGA controller has a 12-bit address bus, with 7 32-bit
2414
     registers, at addresses 0x000 through 0x018, and two color lookup
2415 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2416 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2417
     are not used.
2418
 
2419
`irq = VALUE'
2420 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2421 19 jeremybenn
     0.
2422
 
2423
`refresh_rate = VALUE'
2424 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2425 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2426
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2427
     50 times per simulated second.
2428
 
2429
`txfile = "FILE"'
2430
     FILE specifies the base of the filename for screen dumps.
2431
     Successive screen dumps will be in BMP format, in files with the
2432
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2433 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2434 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2435
     supported for this parameter, but deprecated.
2436
 
2437
 
2438

2439
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2440
 
2441
3.4.7 Frame Buffer Configuration
2442
--------------------------------
2443
 
2444 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2445 19 jeremybenn
     configuration fields are described here, but the component should
2446 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2447 19 jeremybenn
     to make screen dumps to file.
2448
 
2449 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2450
may appear multiple times, specifying multiple frame buffers.  The
2451 19 jeremybenn
following parameters may be specified.
2452
 
2453
`enabled = 0|1'
2454 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2455 19 jeremybenn
     is disabled.
2456
 
2457
`baseaddr = VALUE'
2458
     Set the base address of the frame buffer's memory mapped registers
2459 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2460
     value.
2461 19 jeremybenn
 
2462
     The frame buffer has an 121-bit address bus, with 4 32-bit
2463
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2464 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2465 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2466
 
2467
`refresh_rate = VALUE'
2468 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2469 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2470
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2471
     50 times per simulated second.
2472
 
2473
`txfile = "FILE"'
2474
     FILE specifies the base of the filename for screen dumps.
2475
     Successive screen dumps will be in BMP format, in files with the
2476
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2477 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2478 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2479
     supported for this parameter, but deprecated.
2480
 
2481
 
2482

2483
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2484
 
2485
3.4.8 Keyboard Configuration (PS2)
2486
----------------------------------
2487
 
2488 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2489 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2490 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2491
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2492 19 jeremybenn
standard, this is presumably what is expected with this device.
2493
 
2494
The implementation only provides for keyboard support, which is
2495 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2496 19 jeremybenn
 
2497
     Caution: A standard i8042 device has two registers at addresses
2498 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2499
     suggests that the Or1ksim component places these registers at
2500
     addresses 0x00 and 0x04.
2501 19 jeremybenn
 
2502
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2503
     implements the i8042 device driver, anticipating these registers
2504 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2505 19 jeremybenn
     code will work.
2506
 
2507
     This component should be used with caution.
2508
 
2509 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2510
appear multiple times, specifying multiple keyboard interfaces.  The
2511 19 jeremybenn
following parameters may be specified.
2512
 
2513
`enabled = 0|1'
2514 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2515 19 jeremybenn
     disabled.
2516
 
2517
`baseaddr = VALUE'
2518
     Set the base address of the keyboard's memory mapped registers to
2519 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2520 19 jeremybenn
 
2521
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2522
     registers, at addresses 0x000 and 0x004.
2523
 
2524
          Caution: As noted above, a standard Intel 8042 interface
2525
          would expect to find these registers at locations 0x60 and
2526
          0x64, thus requiring at least a 7-bit bus.
2527
 
2528
`irq = VALUE'
2529 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2530 19 jeremybenn
     value 0.
2531
 
2532
`rxfile = "FILE"'
2533
     `file' specifies a file containing raw key stroke data, which
2534 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2535 19 jeremybenn
     `"kbd_in"'.
2536
 
2537
 
2538

2539
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2540
 
2541
3.4.9 Disc Interface Configuration
2542
----------------------------------
2543
 
2544
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2545
IDE Controller) component implemented at OpenCores, and found in the
2546 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2547 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2548 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2549
which resides on the main OpenRISC Wishbone data bus.
2550 19 jeremybenn
 
2551 385 jeremybenn
     Warning: In the current release of Or1ksim, parsing of the ATA
2552
     section is broken. Users should not configure the disc interface
2553
     in this release.
2554
 
2555 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2556
may appear multiple times, specifying multiple disc controllers.  The
2557 19 jeremybenn
following parameters may be specified.
2558
 
2559
`enabled = 0|1'
2560 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2561 19 jeremybenn
     0, it is disabled.
2562
 
2563
`baseaddr = VALUE'
2564
     Set the base address of the ATA/ATAPI interface's memory mapped
2565 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2566 19 jeremybenn
     sensible value.
2567
 
2568
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2569 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2570
     ATA/ATAPI interface selected (see `dev_id' below), not all
2571
     registers will be available.
2572 19 jeremybenn
 
2573
`irq = VALUE'
2574 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2575 19 jeremybenn
     value 0.
2576
 
2577
`dev_id = 1|2|3'
2578
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2579 82 jeremybenn
     interface to model.  The default value is 1.
2580 19 jeremybenn
 
2581
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2582
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2583
     registers and the `RXD'/`TXD' registers.
2584
 
2585
`rev = VALUE'
2586
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2587 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2588
     be in the range 0-15.  Larger values are truncated with a warning.
2589 346 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2590
     forms bits 24-27.
2591 19 jeremybenn
 
2592
`pio_mode0_t1 = VALUE'
2593
`pio_mode0_t2 = VALUE'
2594
`pio_mode0_t4 = VALUE'
2595
`pio_mode0_teoc = VALUE'
2596
     These parameters specify the timings for use with Programmed
2597 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2598 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2599 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2600 19 jeremybenn
     they do, they will be ignored with a warning.
2601
 
2602
     See the ATA/ATAPI-5 specification for explanations of each of these
2603 82 jeremybenn
     timing parameters.  The default values are:
2604 19 jeremybenn
 
2605
          pio_mode0_t1   =  6
2606
          pio_mode0_t2   = 28
2607
          pio_mode0_t4   =  2
2608
          pio_mode0_teoc = 23
2609
 
2610
`dma_mode0_tm = VALUE'
2611
`dma_mode0_td = VALUE'
2612
`dma_mode0_teoc = VALUE'
2613
     These parameters specify the timings for use with DMA transfers.
2614
     They are specified as the number of clock cycles - 2, rounded up
2615
     to the next highest integer, or zero if that would be negative.
2616 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2617
     ignored with a warning.
2618 19 jeremybenn
 
2619
     See the ATA/ATAPI-5 specification for explanations of each of these
2620 82 jeremybenn
     timing parameters.  The default values are:
2621 19 jeremybenn
 
2622
          dma_mode0_tm   =  4
2623
          dma_mode0_td   = 21
2624
          dma_mode0_teoc = 21
2625
 
2626
 
2627
3.4.9.1 ATA/ATAPI Device Configuration
2628
......................................
2629
 
2630 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2631 19 jeremybenn
device subsection is introduced by
2632
 
2633
     device VALUE
2634
 
2635 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2636
ends with `enddevice'.  Note that if the same device number is
2637
specified more than once, the previous values will be overwritten.
2638
Within the `device' subsection, the following parameters may appear:
2639 19 jeremybenn
 
2640
`type = VALUE'
2641
     VALUEspecifies the type of device: 0 (the default) for "not
2642
     connected", 1 for hard disk simulated in a file and 2 for local
2643
     system hard disk.
2644
 
2645
`file = "FILENAME"'
2646
     `filename' specifies the file to be used for a simulated ATA
2647 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2648 346 jeremybenn
     `"ata_fileN"', where N is the device number.
2649 19 jeremybenn
 
2650
`size = VALUE'
2651
     VALUE specifies the size of a simulated ATA device if the file
2652 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2653 19 jeremybenn
 
2654
`packet = 0|1'
2655 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2656 19 jeremybenn
     default), do not implement the PACKET command feature set.
2657
 
2658
`firmware = "STR"'
2659
     Firmware to report in response to the "Identify Device" command.
2660
     Default `"02207031"'.
2661
 
2662
`heads = VALUE'
2663 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2664 19 jeremybenn
     heads.
2665
 
2666
`sectors = VALUE'
2667 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2668 19 jeremybenn
 
2669
`mwdma = 0|1|2|-1'
2670 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2671 19 jeremybenn
     disable.
2672
 
2673
`pio = 0|1|2|3|4'
2674 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2675 19 jeremybenn
 
2676
 
2677

2678
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2679
 
2680
3.4.10 Generic Peripheral Configuration
2681
---------------------------------------
2682
 
2683
When used as a library (*note Simulator Library: Simulator Library.),
2684
Or1ksim makes provision for any additional peripheral to be implemented
2685 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2686
generates "upcall"s to an external handler.  This interface can support
2687 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2688
for OSCI SystemC (see `http://www.systemc.org').
2689
 
2690
Generic peripheral configuration is described in `section generic'.
2691
This section may appear multiple times, specifying multiple external
2692 82 jeremybenn
peripherals.  The following parameters may be specified.
2693 19 jeremybenn
 
2694
`enabled = 0|1'
2695 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2696 19 jeremybenn
     0, it is disabled.
2697
 
2698
`baseaddr = VALUE'
2699
     Set the base address of the generic peripheral's memory mapped
2700 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2701 19 jeremybenn
     sensible value.
2702
 
2703
     The size of the memory mapped register space is controlled by the
2704
     `size' paramter, described below.
2705
 
2706
`size = VALUE'
2707
     Set the size of the generic peripheral's memory mapped register
2708 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2709 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2710
     parameter `baseaddr' (see above) will be directed to the external
2711
     interface.
2712
 
2713 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2714
     value is zero.  If VALUE is not an exact power of two, accesses to
2715 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2716
     generate a warning, and have no effect (reads will return zero).
2717
 
2718
`name = "STR"'
2719 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2720 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2721 82 jeremybenn
     reporting its status.  The default value is
2722 19 jeremybenn
     `"anonymous external peripheral"'.
2723
 
2724
`byte_enabled = 0|1'
2725
`hw_enabled = 0|1'
2726
`word_enabled = 0|1'
2727
     If 1 (true, the default), these parameters respectively enable the
2728 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2729 19 jeremybenn
     accesses of that width will fail.
2730
 
2731
 
2732

2733
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2734
 
2735
4 Interactive Command Line
2736
**************************
2737
 
2738
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2739 82 jeremybenn
provides the user with an interactive command line.  The commands
2740 19 jeremybenn
available, which may not be abbreviated, are:
2741
 
2742
`q'
2743
     Exit the simulator
2744
 
2745
`r'
2746 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2747 19 jeremybenn
     just executed and next to be executed instructions symbolically
2748
     and the state of the flag in the Supervision Register.
2749
 
2750
`t'
2751
     Execute the next instruction and then display register/instruction
2752
     information as with the `r' command (see above).
2753
 
2754
`run NUM [ hush ]'
2755 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2756 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2757
     above) _unless_ `hush' is specified.
2758
 
2759
`pr REG VALUE'
2760
     Patch register REG with VALUE.
2761
 
2762
`dm FROMADDR [ TOADDR ]'
2763 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2764
     not given, 64 bytes are displayed, starting at FROMADDR.
2765 19 jeremybenn
 
2766
          Caution: The output from this command is broken (a bug).
2767 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2768 19 jeremybenn
          instead of printing out the address at the start of each row,
2769
          it prints the address (of the first of the 16 bytes) before
2770
          _each_ byte.
2771
 
2772
`de FROMADDR [ TOADDR ]'
2773 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2774 19 jeremybenn
     given, 16 instructions are disassembled.
2775
 
2776
     The disassembly is entirely numerical, and gives no symbolic
2777
     information.
2778
 
2779
`pm ADDR VALUE'
2780
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2781
 
2782
`pc VALUE'
2783
     Patch the program counter with VALUE.
2784
 
2785
`cm FROMADDR TOADDR SIZE'
2786
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2787
 
2788
`break ADDR'
2789
     Toggle the breakpoint set at ADDR.
2790
 
2791
`breaks'
2792
     List all set breakpoints
2793
 
2794
`reset'
2795 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2796
     so execution will restart from the reset vector location, 0x100.
2797 19 jeremybenn
 
2798
`hist'
2799
     If saving the execution history has been configured (*note
2800
     Simulator Behavior: Simulator Behavior.), display the execution
2801
     history.
2802
 
2803
`stall'
2804
     Stall the processor, so that control is passed to the debug unit.
2805 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2806 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2807
     debuggers such as GDB.
2808
 
2809
`unstall'
2810 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2811
     This command is useful when debugging the JTAG interface, used by
2812 19 jeremybenn
     debuggers such as GDB.
2813
 
2814
`stats CATEGORY | clear'
2815
     Print the statistics for the given CATEGORY, if available, or
2816 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2817 19 jeremybenn
 
2818
    1
2819
          Miscellaneous statistics: branch predictions (if branch
2820
          predictions are enabled), branch target cache model (if
2821
          enabled), cache (if enbaled), MMU (if enabled) and number of
2822
          addtional load & store cycles.
2823
 
2824
          *Note Configuring the OpenRisc Achitectural Components: Core
2825
          OpenRISC Configuration, for details of how to enable these
2826
          various features.
2827
 
2828
    2
2829 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2830 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2831
 
2832
    3
2833 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2834 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2835
 
2836
    4
2837 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2838 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2839
          Configuration.).
2840
 
2841
    5
2842 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2843 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2844
 
2845
    6
2846 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2847 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2848
 
2849
 
2850
`info'
2851
     Display detailed information about the simulator configuration.
2852
     This is quite a lengthy about, because all MMU TLB information is
2853
     displayed.
2854
 
2855
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2856
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2857 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2858 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2859 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2860 19 jeremybenn
 
2861
     To save to a file, use the redirection function (described after
2862
     this table, below).
2863
 
2864
`dh FROMADDR [ TOADDR ]'
2865
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2866 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2867 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2868
 
2869
     To save to a file, use the redirection function (described after
2870
     this table, below).
2871
 
2872
`setdbch'
2873 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2874 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2875
     channels on the command line.
2876
 
2877
`set SECTION PARAM = VALUE'
2878
     Set the configuration parameter PARA in section SECTION to VALUE.
2879
     *Note Configuration: Configuration, for details of configuration
2880
     parameters and their settings.
2881
 
2882
`debug'
2883 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2884 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2885
     this parameter.
2886
 
2887
          Caution: This is effectively enabling or disabling the debug
2888 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2889 19 jeremybenn
          However using the remote debug interface while the debug unit
2890
          is disabled will lead to undefined behavior and likely crash
2891
          Or1ksim
2892
 
2893
`cuc'
2894
     Enter the the Custom Unit Compiler command prompt (*note CUC
2895
     Configuration: CUC Configuration.).
2896
 
2897
          Caution: The CUC must be properly configured, for this to
2898 82 jeremybenn
          succeed.  In particular a timing file must be available and
2899
          readable.  Otherwise Or1ksim will crash.
2900 19 jeremybenn
 
2901
`help'
2902
     Print out brief information about each command available.
2903
 
2904
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2905 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2906 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2907
     Profiling Utility.).
2908
 
2909
`profile [-vhcq] [-g FILE]'
2910 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2911
     usage as the standalone command (*note Profiling Utility:
2912
     Profiling Utility.).
2913 19 jeremybenn
 
2914
 
2915
For all commands, it is possible to redirect the output to a file, by
2916
using the redirection operator, `>'.
2917
 
2918
     COMMAND > FILENAME
2919
 
2920
This is particularly useful for commands dumping a large amount of
2921
output, such as `dv'.
2922
 
2923
     Caution: Unfortunately there is a serious bug with the redirection
2924 82 jeremybenn
     operator.  It does not return output to standard output after the
2925
     command completes.  Until this bug is fixed, file redirection
2926 19 jeremybenn
     should not be used.
2927
 
2928

2929
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2930
 
2931
5 Verification API (VAPI)
2932
*************************
2933
 
2934
The Verification API (VAPI) provides a TCP/IP interface to allow
2935 82 jeremybenn
components of the simulation to be controlled externally.  The
2936
interface is polled for new requests on each simulated clock cycle.
2937
Components within the simulator may send responses to such requests.
2938 19 jeremybenn
 
2939 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2940
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2941
with a single piece of data (also a 32 bit integer).  On the send side,
2942
it provides for sending a single VAPI ID and data.  However there is no
2943
explicit command-response structure.  Some components just accept
2944
requests (e.g.  to set values), some just generate sends (to report
2945 19 jeremybenn
values), and some do both.
2946
 
2947
Each component has a base ID (32 bit) and its commands will start from
2948 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2949
amongst components.  Request commands will be directed to the component
2950 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2951
 
2952
Thus if there are two components with base IDs of 0x200 and 0x300, and
2953
a request with VAPI ID of 0x203 is received, it will be directed to the
2954
first component as its command #3.
2955
 
2956
The results of VAPI interactions are logged (by default in `vapi.log'
2957
unless an alternative is specified in `section vapi').
2958
 
2959
Currently the following components support VAPI:
2960
 
2961
Debug Unit
2962
     Although the Debug Unit can specify a base VAPI ID, it is not used
2963
     to send commands or receive requests.
2964
 
2965
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2966
     exchanges are logged in the VAPI log file.
2967
 
2968
UART
2969
     If a base VAPI ID is specified, the UART sends details of any
2970
     chars or break characters sent, with dteails of the line control
2971
     register etc encoded in the data packet sent.
2972
 
2973
     This supports a single VAPI command request, but encodes a
2974
     sub-command in the top 8 bits of the associated data.
2975
 
2976
    `0x00'
2977
          This stuffs the least significant 8 bits of the data into the
2978
          serial register of the UART and the next 8 bits into the line
2979
          control register, effectively providing control of the next
2980
          character to be sent or received.
2981
 
2982
    `0x01'
2983
          The divisor latch bytes are set from the least significant 16
2984
          bits of the data.
2985
 
2986
    `0x02'
2987
          The line control register is set from bits 15-8 of the data.
2988
 
2989
    `0x03'
2990
          The UART skew is set from the least significant 16 bits of
2991
          the data
2992
 
2993
    `0x04'
2994
          If the 16th most significant bit of the data is 1, start
2995 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2996
          are sent or cleared after the number of UART clock divider
2997
          ticks specified by the data (immediately if the data is zero).
2998 19 jeremybenn
 
2999
 
3000
DMA
3001
     Although the DMA unit supports a base VAPI ID in its configuration
3002
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
3003
     implemented.
3004
 
3005
Ethernet
3006 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
3007 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
3008 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
3009 19 jeremybenn
     VAPI requests.
3010
 
3011
    `ETH_VAPI_DATA (0)'
3012
 
3013
    `ETH_VAPI_CTRL (0)'
3014
 
3015
GPIO
3016
     If a base VAPI ID is specified, the GPIO sends out on its base
3017
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
3018
     VAPI ID) any changes in outputs.
3019
 
3020 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
3021 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
3022
     GPIO.
3023
 
3024
    `GPIO_VAPI_DATA (0)'
3025
          Set the next input to the commands data field
3026
 
3027
    `GPIO_VAPI_AUX (1)'
3028
          Set the GPIO auxiliary inputs to the data field
3029
 
3030
    `GPIO_VAPI_CLOCK (2)'
3031
          Add an external GPIO clock trigger of period specified in the
3032
          data field.
3033
 
3034
    `GPIO_VAPI_RGPIO_OE (3)'
3035
          Set the GPIO output enable to the data field
3036
 
3037
    `GPIO_VAPI_RGPIO_INTE (4)'
3038
          Set the next interrupt to the data field
3039
 
3040
    `GPIO_VAPI_RGPIO_PTRIG (5)'
3041
          Set the next trigger to the data field
3042
 
3043
    `GPIO_VAPI_RGPIO_AUX (6)'
3044
          Set the next auxiliary input to the data field
3045
 
3046
    `GPIO_VAPI_RGPIO_CTRL (7)'
3047
          Set th next control input to the data field
3048
 
3049
 
3050
 
3051

3052
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
3053
 
3054
6 A Guide to Or1ksim Internals
3055
******************************
3056
 
3057 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
3058 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
3059 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
3060
Linux manual page for `etags'.  A tag file can be created with:
3061 19 jeremybenn
 
3062
     make tags
3063
 
3064
* Menu:
3065
 
3066
* Coding Conventions::
3067
* Global Data Structures::
3068
* Concepts::
3069
* Internal Debugging::
3070 104 jeremybenn
* Regression Testing::
3071 19 jeremybenn
 
3072

3073
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
3074
 
3075
6.1 Coding Conventions for Or1ksim
3076
==================================
3077
 
3078
This chapter provides some guidelines for coding, to facilitate
3079
extensions to Or1ksim
3080
 
3081
_GNU Coding Standard_
3082
     Code should follow the GNU coding standard for C
3083 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
3084 19 jeremybenn
     through the `indent' program.
3085
 
3086
_`#include' headers_
3087
     All C source code files should include `config.h' before any other
3088
     file.
3089
 
3090
     This should be followed by inclusion of any system headers (but see
3091
     the comments about portability and `port.h' below) and then by any
3092
     Or1ksim package headers.
3093
 
3094
     If `port.h' is required, it should be the first package header to
3095
     be included after the system headers.
3096
 
3097
     All C source code and header files should directly include any
3098 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
3099
     other header having already included it.  The two exceptions are
3100 19 jeremybenn
 
3101
       1. All header files may assume that `config.h' has already been
3102
          included.
3103
 
3104
       2. System headers which impose portability problems should be
3105
          included by using the package header `port.h', rather than
3106 82 jeremybenn
          the system headers themselves.  This is the case for code
3107 19 jeremybenn
          requiring
3108
 
3109
             * `strndup' (from `string.h')
3110
 
3111
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
3112
 
3113
             * `isblank' (from `ctype.h')
3114
 
3115
 
3116
 
3117
_`#include' files once only_
3118
     All include files should be protected by `#ifndef' to ensure their
3119 82 jeremybenn
     definitions are only included once.  For instance a header file
3120 19 jeremybenn
     `X-Y.H' should surround its contents with:
3121
 
3122
          #ifndef X_Y__H
3123
          #define X_Y__H
3124
 
3125
          
3126
 
3127
          #endif  /* X_Y__H */
3128
 
3129
_Avoid `typedef'_
3130
     The GNU coding style for C does not have a clear way to distinguish
3131 82 jeremybenn
     between user type name and user variables.  For this reason
3132 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
3133 82 jeremybenn
     defined types.  This makes the code much easier to read.
3134 19 jeremybenn
 
3135
     There are some `typedef' declarations in the `argtable2' library
3136
     and the ELF and COFF headers, because this code is taken from
3137
     other places.
3138
 
3139
     Within Or1ksim legacy uses of `typedef' have largely been purged,
3140
     except in the Custom Unit Compiler (*note Custom Unit Compiler
3141
     (CUC) Configuration: CUC Configuration.).
3142
 
3143
     The remaining uses of `typedef' occur in two places:
3144
 
3145
        * `port/port.h' defines types to replace those in header files
3146
          that are not available (character functions, string
3147
          duplication, integer types).
3148
 
3149
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
3150
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
3151
          and signed register (`orreg_t') values.
3152
 
3153
 
3154
     Where new types are defined, they should appear in one of these two
3155 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
3156
     `arch.h' should always have the suffix `_h'.
3157 19 jeremybenn
 
3158
_Don't begin names with underscore_
3159
     Names beginning with `_' are intended to be part of the C
3160 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
3161 19 jeremybenn
 
3162
_Keep Non-global top level entities static_
3163
     All top level entities (functions, variables), which are not
3164
     explicitly part of a global interface should be declared static.
3165
     This ensures that unwanted connections are not inadvertently built
3166
     across the program.
3167
 
3168
_Use of `inline'_
3169 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
3170 19 jeremybenn
     out for themselves what is best in this respect.
3171
 
3172
_Initialization_
3173 82 jeremybenn
     All data structures should be explicitly initialized.  In
3174
     particular code should not rely on static data structures being
3175
     initialized to zero.
3176 19 jeremybenn
 
3177
     The rationale is that in future static data structures may become
3178 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
3179 19 jeremybenn
     historically.
3180
 
3181
     A specific case is with new peripherals, which should always
3182
     include a `start' function to pre-initialize all configuration
3183
     parameters to sensible defaults
3184
 
3185
_Configuration Validation_
3186
     All configuration values should be validated, preferably when
3187
     encountered, if not when the `section' is closed, or otherwise at
3188
     run time when the parameter is first used.
3189
 
3190
 
3191

3192
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
3193
 
3194
6.2 Global Data Structures
3195
==========================
3196
 
3197
`config'
3198
     The global variable `config' of type `struct config' holds the
3199
     configuration data for some of the Or1ksim components which are
3200 82 jeremybenn
     always present.  At present the components are:
3201 19 jeremybenn
 
3202
        * The simulator defined in `section sim' (*note Simulator
3203
          Configuration: Simulator Configuration.).
3204
 
3205
        * The Verification API (VAPI) defined  in `section vapi' (*note
3206
          Verification API (VAPI) Configuration: Verification API
3207
          Configuration.).
3208
 
3209
        * The Custom Unit Compiler (CUC), defined in `section cuc'
3210
          (*note Custom Unit Compiler (CUC) Configuration: CUC
3211
          Configuration.).
3212
 
3213
        * The CPU, defined in `section cpu' (*note CPU Configuration:
3214
          CPU Configuration.).
3215
 
3216
        * The data cache (but not the instruction cache), defined in
3217
          `section dc' (*note Cache Configuration: Cache
3218
          Configuration.).
3219
 
3220
        * The power management unit, defined in `section pm' (*note
3221
          Power Management Configuration: Power Management
3222
          Configuration.).
3223
 
3224
        * The programmable interrupt controller, defined in
3225
          `section pic' (*note Interrupt Configuration: Interrupt
3226
          Configuration.).
3227
 
3228
        * Branch prediciton, defined in `section bpb' (*note Branch
3229
          Prediction Configuration: Branch Prediction Configuration.).
3230
 
3231
        * The debug unit, defined in `section debug' (*note Debug
3232
          Interface Configuration: Debug Interface Configuration.).
3233
 
3234
 
3235
     This struct is made of a collection of structs, one for each
3236 82 jeremybenn
     component.  For example the simulator configuration is held in
3237 19 jeremybenn
     `config.sim'.
3238
 
3239
`config'
3240
     This is a linked list of data structures holding configuration data
3241
     for all sections which are not held in the main `config' data
3242 82 jeremybenn
     structure.  In general these are components (such as peripherals
3243
     and memory) which may occur multiple times.  However it also
3244
     handles some architectural components which may occur only once,
3245
     such as the memory management units, the instruction cache, the
3246
     interrupt controller and branch prediction.
3247 19 jeremybenn
 
3248
`runtime'
3249
     The global variable `runtime' of type `struct runtime' holds all
3250 82 jeremybenn
     the runtime information about the simulation.  To access this
3251 19 jeremybenn
     variable, `sim-config.h' must be included.
3252
 
3253
     This struct is itself made of 3 other structs, `cpu' (for CPU run
3254
     time state), `vapi' (for Verification API state) and `cuc' (for
3255
     Custom Unit Compiler state).
3256
 
3257
 
3258

3259
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
3260
 
3261
6.3 Concepts
3262
============
3263
 
3264
_Output Redirection_
3265 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
3266 19 jeremybenn
     should be explicitly written to this stream, or may use the
3267
     `PRINTF' macro, which will write its arguments to this output
3268
     stream.
3269
 
3270
_Reset Hooks_
3271
     Any peripheral may register a routine to be called when the the
3272
     processor is reset by calling `reg_sim_reset', providing a
3273 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
3274 19 jeremybenn
     that function will be called with the data stucture pointer as
3275
     argument.
3276
 
3277 432 jeremybenn
_Interrupts_
3278
     An internal peripheral can model the effect of an interrupt being
3279
     asserted by calling `report_interrupt'.  This is used for both edge
3280
     and level sensitive interrupts.
3281 19 jeremybenn
 
3282 432 jeremybenn
     The effect is to set the corresponding bit in the PICSR SPR and to
3283
     queue an interrupt exception to take place after the current
3284
     instruction completes execution.
3285
 
3286
     Externally, the different interrupts require different mechanisms
3287
     for clearing.  Level sensitive interrupts should be cleared by
3288
     deasserting the interrupt line, edge sensitive interrupts by
3289
     clearing the corresponding bit in the PICSR SPR.
3290
 
3291
     Internally this amounts to the same thing (clearing the PICSPR
3292
     bit), so a single function is provided, `clear_interrupt'.  Note
3293
     however that when level sensitive interrupts are configured, PICSR
3294
     is read only, and can only be cleared by calling
3295
     `clear_interrupt'.  Using the two functions provided will ensure
3296
     the peripheral works correctly whichever type of interrupt is used.
3297
 
3298
          Note: Until an interrupt is cleared, all subsequent
3299
          interrupts are ignored with a warning.
3300
 
3301
 
3302 19 jeremybenn

3303 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
3304 19 jeremybenn
 
3305
6.4 Internal Debugging
3306
======================
3307
 
3308
The function `debug' is like `printf', but with an extra first
3309 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
3310
the simulator configuration (*note Simulator Behavior: Simulator
3311
Behavior.) is greater than or equal to this value, the remaining
3312
arguments are printed to the current output stream (*note Output
3313
Redirection: Output Redirection.).
3314 19 jeremybenn
 
3315

3316 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
3317
 
3318
6.5 Regression Testing
3319
======================
3320
 
3321
Or1ksim now includes a regression test suite for both standalone and
3322
library usage as described earlier (*note Building and Installing:
3323
Build and Install.).  Running the tests requires that the OpenRISC
3324
toolchain and DejaGNU are both installed.
3325
 
3326
Tests are written using `expect', a derivative of TCL.  Documentation
3327
of DejaGnu, `expect' and TCL are freely available on the Web.  The
3328
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
3329
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
3330
provides a concise introduction.
3331
 
3332
All test code is found in the `testsuite' directory.  The key files and
3333
directories used are as follows.
3334
 
3335
`global-conf.exp'
3336
     This is the global DejaGNU configuration file used to set up
3337
     parameters common to all tests.  If the user has the environment
3338
     varialbe `DEJAGNU' defined, it will be used instead, but this is
3339
     not recommended.
3340
 
3341
`Makefile.am'
3342
     This is the top level `automake' file for the testsuite.  The only
3343
     changes likely to be needed here is additional local cleanup of
3344
     files created by new tests.
3345
 
3346
`README'
3347
     This contains details of all the tests
3348
 
3349
`config'
3350
     This contains DejaGnu board configurations.  Since the tests are
3351
     generally run on a Unix host, this should just contain `Unix.exp'.
3352
 
3353
`lib'
3354
     This contains DejaGnu tool specific configurations.  "Tool" has a
3355
     specific meaning in DejaGNU, referring just to a grouping of
3356
     tests.  In this case there are two such "tools", "or1ksim" and
3357
     "libsim" for tests of the standalone tool and tests of the library.
3358
 
3359
     Corresponding to this, there are two tool specific configuration
3360
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
3361
     procedures for common use among the tests.
3362
 
3363
`libsim.tests'
3364
`or1ksim.tests'
3365
     These are the directories of tests of the Or1ksim library.  They
3366
     also include Or1ksim configuration files and each has a
3367
     `Makefile.am' file.  `Makefile.am' should be updated whenever
3368
     files are added to this directory, to ensure they are included in
3369
     the distribution.
3370
 
3371
`test-code'
3372
     These are all the test programs to be compiled on the host (each
3373
     in its own directory).  In general these are programs to support
3374
     testing of the library, and build various programs linking in the
3375
     library.
3376
 
3377
`test-code'
3378
     These are all the test programs to be compiled with the OpenRISC
3379
     tool chain to run with either standalone Or1ksim or the library.
3380
     This directory includes its own `configure.ac', since it must set
3381
     up a separate tool chain based on the target, not the host.
3382
 
3383
 
3384
To add a new test needs the following steps.
3385
 
3386 346 jeremybenn
   * Put new host C code in its own directory within `test-code'.  Add
3387 104 jeremybenn
     the directory to the existing `Makefile.am' in the `test-code'
3388
     directory and create a `Makefile.am' in the new directory to drive
3389 346 jeremybenn
     building the test program(s).  Don't forget to add the new
3390 104 jeremybenn
     `Makefile' to the top level `configure.ac' so it gets generated.
3391
     Not all tests require code here.
3392
 
3393 346 jeremybenn
   * Put new target C code in its own directory within `test-code-or1k'.
3394
     Once again modify & create `Makefile.am'.  This time modify the
3395
     `configure.ac' in the `test-code-or1k' so the `Makefile' gets
3396
     generated.  The existing programs provide examples to start from,
3397
     including custom linker scripts where needed.
3398 104 jeremybenn
 
3399
   * Add one or more tests and configuration files to the relevant
3400 346 jeremybenn
     "tool" test directory.  Use the existing tests as templates.  They
3401 104 jeremybenn
     make heavy use of the `expect'/TCL procedures in the `config'
3402
     directory to facilitate driving the tests.
3403
 
3404
 
3405

3406 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3407
 
3408
7 GNU Free Documentation License
3409
********************************
3410
 
3411
                      Version 1.2, November 2002
3412
 
3413
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3414
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3415
 
3416
     Everyone is permitted to copy and distribute verbatim copies
3417
     of this license document, but changing it is not allowed.
3418
 
3419
  0. PREAMBLE
3420
 
3421
     The purpose of this License is to make a manual, textbook, or other
3422
     functional and useful document "free" in the sense of freedom: to
3423
     assure everyone the effective freedom to copy and redistribute it,
3424
     with or without modifying it, either commercially or
3425
     noncommercially.  Secondarily, this License preserves for the
3426
     author and publisher a way to get credit for their work, while not
3427
     being considered responsible for modifications made by others.
3428
 
3429
     This License is a kind of "copyleft", which means that derivative
3430
     works of the document must themselves be free in the same sense.
3431
     It complements the GNU General Public License, which is a copyleft
3432
     license designed for free software.
3433
 
3434
     We have designed this License in order to use it for manuals for
3435
     free software, because free software needs free documentation: a
3436
     free program should come with manuals providing the same freedoms
3437
     that the software does.  But this License is not limited to
3438
     software manuals; it can be used for any textual work, regardless
3439
     of subject matter or whether it is published as a printed book.
3440
     We recommend this License principally for works whose purpose is
3441
     instruction or reference.
3442
 
3443
  1. APPLICABILITY AND DEFINITIONS
3444
 
3445
     This License applies to any manual or other work, in any medium,
3446
     that contains a notice placed by the copyright holder saying it
3447
     can be distributed under the terms of this License.  Such a notice
3448
     grants a world-wide, royalty-free license, unlimited in duration,
3449
     to use that work under the conditions stated herein.  The
3450
     "Document", below, refers to any such manual or work.  Any member
3451
     of the public is a licensee, and is addressed as "you".  You
3452
     accept the license if you copy, modify or distribute the work in a
3453
     way requiring permission under copyright law.
3454
 
3455
     A "Modified Version" of the Document means any work containing the
3456
     Document or a portion of it, either copied verbatim, or with
3457
     modifications and/or translated into another language.
3458
 
3459
     A "Secondary Section" is a named appendix or a front-matter section
3460
     of the Document that deals exclusively with the relationship of the
3461
     publishers or authors of the Document to the Document's overall
3462
     subject (or to related matters) and contains nothing that could
3463
     fall directly within that overall subject.  (Thus, if the Document
3464
     is in part a textbook of mathematics, a Secondary Section may not
3465
     explain any mathematics.)  The relationship could be a matter of
3466
     historical connection with the subject or with related matters, or
3467
     of legal, commercial, philosophical, ethical or political position
3468
     regarding them.
3469
 
3470
     The "Invariant Sections" are certain Secondary Sections whose
3471
     titles are designated, as being those of Invariant Sections, in
3472
     the notice that says that the Document is released under this
3473
     License.  If a section does not fit the above definition of
3474
     Secondary then it is not allowed to be designated as Invariant.
3475
     The Document may contain zero Invariant Sections.  If the Document
3476
     does not identify any Invariant Sections then there are none.
3477
 
3478
     The "Cover Texts" are certain short passages of text that are
3479
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3480
     that says that the Document is released under this License.  A
3481
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3482
     be at most 25 words.
3483
 
3484
     A "Transparent" copy of the Document means a machine-readable copy,
3485
     represented in a format whose specification is available to the
3486
     general public, that is suitable for revising the document
3487
     straightforwardly with generic text editors or (for images
3488
     composed of pixels) generic paint programs or (for drawings) some
3489
     widely available drawing editor, and that is suitable for input to
3490
     text formatters or for automatic translation to a variety of
3491
     formats suitable for input to text formatters.  A copy made in an
3492
     otherwise Transparent file format whose markup, or absence of
3493
     markup, has been arranged to thwart or discourage subsequent
3494
     modification by readers is not Transparent.  An image format is
3495
     not Transparent if used for any substantial amount of text.  A
3496
     copy that is not "Transparent" is called "Opaque".
3497
 
3498
     Examples of suitable formats for Transparent copies include plain
3499
     ASCII without markup, Texinfo input format, LaTeX input format,
3500
     SGML or XML using a publicly available DTD, and
3501
     standard-conforming simple HTML, PostScript or PDF designed for
3502
     human modification.  Examples of transparent image formats include
3503
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3504
     can be read and edited only by proprietary word processors, SGML or
3505
     XML for which the DTD and/or processing tools are not generally
3506
     available, and the machine-generated HTML, PostScript or PDF
3507
     produced by some word processors for output purposes only.
3508
 
3509
     The "Title Page" means, for a printed book, the title page itself,
3510
     plus such following pages as are needed to hold, legibly, the
3511
     material this License requires to appear in the title page.  For
3512
     works in formats which do not have any title page as such, "Title
3513
     Page" means the text near the most prominent appearance of the
3514
     work's title, preceding the beginning of the body of the text.
3515
 
3516
     A section "Entitled XYZ" means a named subunit of the Document
3517
     whose title either is precisely XYZ or contains XYZ in parentheses
3518
     following text that translates XYZ in another language.  (Here XYZ
3519
     stands for a specific section name mentioned below, such as
3520
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3521
     To "Preserve the Title" of such a section when you modify the
3522
     Document means that it remains a section "Entitled XYZ" according
3523
     to this definition.
3524
 
3525
     The Document may include Warranty Disclaimers next to the notice
3526
     which states that this License applies to the Document.  These
3527
     Warranty Disclaimers are considered to be included by reference in
3528
     this License, but only as regards disclaiming warranties: any other
3529
     implication that these Warranty Disclaimers may have is void and
3530
     has no effect on the meaning of this License.
3531
 
3532
  2. VERBATIM COPYING
3533
 
3534
     You may copy and distribute the Document in any medium, either
3535
     commercially or noncommercially, provided that this License, the
3536
     copyright notices, and the license notice saying this License
3537
     applies to the Document are reproduced in all copies, and that you
3538
     add no other conditions whatsoever to those of this License.  You
3539
     may not use technical measures to obstruct or control the reading
3540
     or further copying of the copies you make or distribute.  However,
3541
     you may accept compensation in exchange for copies.  If you
3542
     distribute a large enough number of copies you must also follow
3543
     the conditions in section 3.
3544
 
3545
     You may also lend copies, under the same conditions stated above,
3546
     and you may publicly display copies.
3547
 
3548
  3. COPYING IN QUANTITY
3549
 
3550
     If you publish printed copies (or copies in media that commonly
3551
     have printed covers) of the Document, numbering more than 100, and
3552
     the Document's license notice requires Cover Texts, you must
3553
     enclose the copies in covers that carry, clearly and legibly, all
3554
     these Cover Texts: Front-Cover Texts on the front cover, and
3555
     Back-Cover Texts on the back cover.  Both covers must also clearly
3556
     and legibly identify you as the publisher of these copies.  The
3557
     front cover must present the full title with all words of the
3558
     title equally prominent and visible.  You may add other material
3559
     on the covers in addition.  Copying with changes limited to the
3560
     covers, as long as they preserve the title of the Document and
3561
     satisfy these conditions, can be treated as verbatim copying in
3562
     other respects.
3563
 
3564
     If the required texts for either cover are too voluminous to fit
3565
     legibly, you should put the first ones listed (as many as fit
3566
     reasonably) on the actual cover, and continue the rest onto
3567
     adjacent pages.
3568
 
3569
     If you publish or distribute Opaque copies of the Document
3570
     numbering more than 100, you must either include a
3571
     machine-readable Transparent copy along with each Opaque copy, or
3572
     state in or with each Opaque copy a computer-network location from
3573
     which the general network-using public has access to download
3574
     using public-standard network protocols a complete Transparent
3575
     copy of the Document, free of added material.  If you use the
3576
     latter option, you must take reasonably prudent steps, when you
3577
     begin distribution of Opaque copies in quantity, to ensure that
3578
     this Transparent copy will remain thus accessible at the stated
3579
     location until at least one year after the last time you
3580
     distribute an Opaque copy (directly or through your agents or
3581
     retailers) of that edition to the public.
3582
 
3583
     It is requested, but not required, that you contact the authors of
3584
     the Document well before redistributing any large number of
3585
     copies, to give them a chance to provide you with an updated
3586
     version of the Document.
3587
 
3588
  4. MODIFICATIONS
3589
 
3590
     You may copy and distribute a Modified Version of the Document
3591
     under the conditions of sections 2 and 3 above, provided that you
3592
     release the Modified Version under precisely this License, with
3593
     the Modified Version filling the role of the Document, thus
3594
     licensing distribution and modification of the Modified Version to
3595
     whoever possesses a copy of it.  In addition, you must do these
3596
     things in the Modified Version:
3597
 
3598
       A. Use in the Title Page (and on the covers, if any) a title
3599
          distinct from that of the Document, and from those of
3600
          previous versions (which should, if there were any, be listed
3601
          in the History section of the Document).  You may use the
3602
          same title as a previous version if the original publisher of
3603
          that version gives permission.
3604
 
3605
       B. List on the Title Page, as authors, one or more persons or
3606
          entities responsible for authorship of the modifications in
3607
          the Modified Version, together with at least five of the
3608
          principal authors of the Document (all of its principal
3609
          authors, if it has fewer than five), unless they release you
3610
          from this requirement.
3611
 
3612
       C. State on the Title page the name of the publisher of the
3613
          Modified Version, as the publisher.
3614
 
3615
       D. Preserve all the copyright notices of the Document.
3616
 
3617
       E. Add an appropriate copyright notice for your modifications
3618
          adjacent to the other copyright notices.
3619
 
3620
       F. Include, immediately after the copyright notices, a license
3621
          notice giving the public permission to use the Modified
3622
          Version under the terms of this License, in the form shown in
3623
          the Addendum below.
3624
 
3625
       G. Preserve in that license notice the full lists of Invariant
3626
          Sections and required Cover Texts given in the Document's
3627
          license notice.
3628
 
3629
       H. Include an unaltered copy of this License.
3630
 
3631
       I. Preserve the section Entitled "History", Preserve its Title,
3632
          and add to it an item stating at least the title, year, new
3633
          authors, and publisher of the Modified Version as given on
3634
          the Title Page.  If there is no section Entitled "History" in
3635
          the Document, create one stating the title, year, authors,
3636
          and publisher of the Document as given on its Title Page,
3637
          then add an item describing the Modified Version as stated in
3638
          the previous sentence.
3639
 
3640
       J. Preserve the network location, if any, given in the Document
3641
          for public access to a Transparent copy of the Document, and
3642
          likewise the network locations given in the Document for
3643
          previous versions it was based on.  These may be placed in
3644
          the "History" section.  You may omit a network location for a
3645
          work that was published at least four years before the
3646
          Document itself, or if the original publisher of the version
3647
          it refers to gives permission.
3648
 
3649
       K. For any section Entitled "Acknowledgements" or "Dedications",
3650
          Preserve the Title of the section, and preserve in the
3651
          section all the substance and tone of each of the contributor
3652
          acknowledgements and/or dedications given therein.
3653
 
3654
       L. Preserve all the Invariant Sections of the Document,
3655
          unaltered in their text and in their titles.  Section numbers
3656
          or the equivalent are not considered part of the section
3657
          titles.
3658
 
3659
       M. Delete any section Entitled "Endorsements".  Such a section
3660
          may not be included in the Modified Version.
3661
 
3662
       N. Do not retitle any existing section to be Entitled
3663
          "Endorsements" or to conflict in title with any Invariant
3664
          Section.
3665
 
3666
       O. Preserve any Warranty Disclaimers.
3667
 
3668
     If the Modified Version includes new front-matter sections or
3669
     appendices that qualify as Secondary Sections and contain no
3670
     material copied from the Document, you may at your option
3671
     designate some or all of these sections as invariant.  To do this,
3672
     add their titles to the list of Invariant Sections in the Modified
3673
     Version's license notice.  These titles must be distinct from any
3674
     other section titles.
3675
 
3676
     You may add a section Entitled "Endorsements", provided it contains
3677
     nothing but endorsements of your Modified Version by various
3678
     parties--for example, statements of peer review or that the text
3679
     has been approved by an organization as the authoritative
3680
     definition of a standard.
3681
 
3682
     You may add a passage of up to five words as a Front-Cover Text,
3683
     and a passage of up to 25 words as a Back-Cover Text, to the end
3684
     of the list of Cover Texts in the Modified Version.  Only one
3685
     passage of Front-Cover Text and one of Back-Cover Text may be
3686
     added by (or through arrangements made by) any one entity.  If the
3687
     Document already includes a cover text for the same cover,
3688
     previously added by you or by arrangement made by the same entity
3689
     you are acting on behalf of, you may not add another; but you may
3690
     replace the old one, on explicit permission from the previous
3691
     publisher that added the old one.
3692
 
3693
     The author(s) and publisher(s) of the Document do not by this
3694
     License give permission to use their names for publicity for or to
3695
     assert or imply endorsement of any Modified Version.
3696
 
3697
  5. COMBINING DOCUMENTS
3698
 
3699
     You may combine the Document with other documents released under
3700
     this License, under the terms defined in section 4 above for
3701
     modified versions, provided that you include in the combination
3702
     all of the Invariant Sections of all of the original documents,
3703
     unmodified, and list them all as Invariant Sections of your
3704
     combined work in its license notice, and that you preserve all
3705
     their Warranty Disclaimers.
3706
 
3707
     The combined work need only contain one copy of this License, and
3708
     multiple identical Invariant Sections may be replaced with a single
3709
     copy.  If there are multiple Invariant Sections with the same name
3710
     but different contents, make the title of each such section unique
3711
     by adding at the end of it, in parentheses, the name of the
3712
     original author or publisher of that section if known, or else a
3713
     unique number.  Make the same adjustment to the section titles in
3714
     the list of Invariant Sections in the license notice of the
3715
     combined work.
3716
 
3717
     In the combination, you must combine any sections Entitled
3718
     "History" in the various original documents, forming one section
3719
     Entitled "History"; likewise combine any sections Entitled
3720
     "Acknowledgements", and any sections Entitled "Dedications".  You
3721
     must delete all sections Entitled "Endorsements."
3722
 
3723
  6. COLLECTIONS OF DOCUMENTS
3724
 
3725
     You may make a collection consisting of the Document and other
3726
     documents released under this License, and replace the individual
3727
     copies of this License in the various documents with a single copy
3728
     that is included in the collection, provided that you follow the
3729
     rules of this License for verbatim copying of each of the
3730
     documents in all other respects.
3731
 
3732
     You may extract a single document from such a collection, and
3733
     distribute it individually under this License, provided you insert
3734
     a copy of this License into the extracted document, and follow
3735
     this License in all other respects regarding verbatim copying of
3736
     that document.
3737
 
3738
  7. AGGREGATION WITH INDEPENDENT WORKS
3739
 
3740
     A compilation of the Document or its derivatives with other
3741
     separate and independent documents or works, in or on a volume of
3742
     a storage or distribution medium, is called an "aggregate" if the
3743
     copyright resulting from the compilation is not used to limit the
3744
     legal rights of the compilation's users beyond what the individual
3745
     works permit.  When the Document is included in an aggregate, this
3746
     License does not apply to the other works in the aggregate which
3747
     are not themselves derivative works of the Document.
3748
 
3749
     If the Cover Text requirement of section 3 is applicable to these
3750
     copies of the Document, then if the Document is less than one half
3751
     of the entire aggregate, the Document's Cover Texts may be placed
3752
     on covers that bracket the Document within the aggregate, or the
3753
     electronic equivalent of covers if the Document is in electronic
3754
     form.  Otherwise they must appear on printed covers that bracket
3755
     the whole aggregate.
3756
 
3757
  8. TRANSLATION
3758
 
3759
     Translation is considered a kind of modification, so you may
3760
     distribute translations of the Document under the terms of section
3761
     4.  Replacing Invariant Sections with translations requires special
3762
     permission from their copyright holders, but you may include
3763
     translations of some or all Invariant Sections in addition to the
3764
     original versions of these Invariant Sections.  You may include a
3765
     translation of this License, and all the license notices in the
3766
     Document, and any Warranty Disclaimers, provided that you also
3767
     include the original English version of this License and the
3768
     original versions of those notices and disclaimers.  In case of a
3769
     disagreement between the translation and the original version of
3770
     this License or a notice or disclaimer, the original version will
3771
     prevail.
3772
 
3773
     If a section in the Document is Entitled "Acknowledgements",
3774
     "Dedications", or "History", the requirement (section 4) to
3775
     Preserve its Title (section 1) will typically require changing the
3776
     actual title.
3777
 
3778
  9. TERMINATION
3779
 
3780
     You may not copy, modify, sublicense, or distribute the Document
3781
     except as expressly provided for under this License.  Any other
3782
     attempt to copy, modify, sublicense or distribute the Document is
3783
     void, and will automatically terminate your rights under this
3784
     License.  However, parties who have received copies, or rights,
3785
     from you under this License will not have their licenses
3786
     terminated so long as such parties remain in full compliance.
3787
 
3788
 10. FUTURE REVISIONS OF THIS LICENSE
3789
 
3790
     The Free Software Foundation may publish new, revised versions of
3791
     the GNU Free Documentation License from time to time.  Such new
3792
     versions will be similar in spirit to the present version, but may
3793
     differ in detail to address new problems or concerns.  See
3794
     `http://www.gnu.org/copyleft/'.
3795
 
3796
     Each version of the License is given a distinguishing version
3797
     number.  If the Document specifies that a particular numbered
3798
     version of this License "or any later version" applies to it, you
3799
     have the option of following the terms and conditions either of
3800
     that specified version or of any later version that has been
3801
     published (not as a draft) by the Free Software Foundation.  If
3802
     the Document does not specify a version number of this License,
3803
     you may choose any version ever published (not as a draft) by the
3804
     Free Software Foundation.
3805
 
3806
ADDENDUM: How to use this License for your documents
3807
====================================================
3808
 
3809
To use this License in a document you have written, include a copy of
3810
the License in the document and put the following copyright and license
3811
notices just after the title page:
3812
 
3813
       Copyright (C)  YEAR  YOUR NAME.
3814
       Permission is granted to copy, distribute and/or modify this document
3815
       under the terms of the GNU Free Documentation License, Version 1.2
3816
       or any later version published by the Free Software Foundation;
3817
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3818
       Texts.  A copy of the license is included in the section entitled ``GNU
3819
       Free Documentation License''.
3820
 
3821
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3822
replace the "with...Texts." line with this:
3823
 
3824
         with the Invariant Sections being LIST THEIR TITLES, with
3825
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3826
         being LIST.
3827
 
3828
If you have Invariant Sections without Cover Texts, or some other
3829
combination of the three, merge those two alternatives to suit the
3830
situation.
3831
 
3832
If your document contains nontrivial examples of program code, we
3833
recommend releasing these examples in parallel under your choice of
3834
free software license, such as the GNU General Public License, to
3835
permit their use in free software.
3836
 
3837

3838
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3839
 
3840
Index
3841
*****
3842
 
3843
 
3844
* Menu:
3845
3846
* --cumulative:                          Profiling Utility.   (line  26)
3847
* --debug-config:                        Standalone Simulator.
3848 385 jeremybenn
                                                              (line  86)
3849 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3850 127 jeremybenn
                                                              (line 105)
3851 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3852 127 jeremybenn
                                                              (line 118)
3853 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3854 127 jeremybenn
                                                              (line  98)
3855 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3856 104 jeremybenn
                                                              (line  59)
3857 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3858 127 jeremybenn
                                                              (line 133)
3859 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3860 104 jeremybenn
                                                              (line  30)
3861 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3862 127 jeremybenn
                                                              (line  92)
3863
* --disable-unsigned-xori:               Configuring the Build.
3864 104 jeremybenn
                                                              (line  69)
3865 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3866 127 jeremybenn
                                                              (line 104)
3867 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3868 127 jeremybenn
                                                              (line 117)
3869 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3870 127 jeremybenn
                                                              (line  97)
3871 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3872 104 jeremybenn
                                                              (line  58)
3873 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3874 104 jeremybenn
                                                              (line  37)
3875 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3876 385 jeremybenn
                                                              (line 120)
3877 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3878 127 jeremybenn
                                                              (line 132)
3879 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3880 385 jeremybenn
                                                              (line 117)
3881 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3882 104 jeremybenn
                                                              (line  29)
3883 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3884 127 jeremybenn
                                                              (line  91)
3885
* --enable-unsigned-xori:                Configuring the Build.
3886 104 jeremybenn
                                                              (line  68)
3887 19 jeremybenn
* --file:                                Standalone Simulator.
3888 385 jeremybenn
                                                              (line  44)
3889 19 jeremybenn
* --filename:                            Memory Profiling Utility.
3890
                                                              (line  51)
3891
* --generate:                            Profiling Utility.   (line  34)
3892
* --group:                               Memory Profiling Utility.
3893
                                                              (line  47)
3894
* --help:                                Standalone Simulator.
3895 346 jeremybenn
                                                              (line  21)
3896 19 jeremybenn
* --help (memory profiling utility):     Memory Profiling Utility.
3897
                                                              (line  22)
3898
* --help (profiling utility):            Profiling Utility.   (line  22)
3899
* --interactive:                         Standalone Simulator.
3900 346 jeremybenn
                                                              (line  25)
3901
* --memory:                              Standalone Simulator.
3902 385 jeremybenn
                                                              (line  70)
3903 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3904
                                                              (line  26)
3905
* --nosrv:                               Standalone Simulator.
3906 385 jeremybenn
                                                              (line  52)
3907 346 jeremybenn
* --quiet <1>:                           Profiling Utility.   (line  30)
3908
* --quiet:                               Standalone Simulator.
3909
                                                              (line  29)
3910
* --report-memory-errors:                Standalone Simulator.
3911 385 jeremybenn
                                                              (line  91)
3912 19 jeremybenn
* --srv:                                 Standalone Simulator.
3913 385 jeremybenn
                                                              (line  60)
3914 19 jeremybenn
* --strict-npc:                          Standalone Simulator.
3915 385 jeremybenn
                                                              (line 100)
3916 450 jeremybenn
* --trace <1>:                           Trace Generation.    (line  15)
3917 420 jeremybenn
* --trace:                               Standalone Simulator.
3918
                                                              (line  39)
3919 346 jeremybenn
* --verbose:                             Standalone Simulator.
3920
                                                              (line  33)
3921 19 jeremybenn
* --version:                             Standalone Simulator.
3922 346 jeremybenn
                                                              (line  17)
3923 19 jeremybenn
* --version (memory profiling utility):  Memory Profiling Utility.
3924
                                                              (line  17)
3925
* --version (profiling utility):         Profiling Utility.   (line  17)
3926
* -c:                                    Profiling Utility.   (line  26)
3927
* -d:                                    Standalone Simulator.
3928 385 jeremybenn
                                                              (line  86)
3929 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3930
                                                              (line  51)
3931
* -f:                                    Standalone Simulator.
3932 385 jeremybenn
                                                              (line  44)
3933 346 jeremybenn
* -g <1>:                                Memory Profiling Utility.
3934 19 jeremybenn
                                                              (line  47)
3935 346 jeremybenn
* -g:                                    Profiling Utility.   (line  34)
3936 19 jeremybenn
* -h:                                    Standalone Simulator.
3937 346 jeremybenn
                                                              (line  21)
3938 19 jeremybenn
* -h (memory profiling utility):         Memory Profiling Utility.
3939
                                                              (line  22)
3940
* -h (profiling utility):                Profiling Utility.   (line  22)
3941
* -i:                                    Standalone Simulator.
3942 346 jeremybenn
                                                              (line  25)
3943
* -m <1>:                                Memory Profiling Utility.
3944 19 jeremybenn
                                                              (line  26)
3945 346 jeremybenn
* -m:                                    Standalone Simulator.
3946 385 jeremybenn
                                                              (line  70)
3947 346 jeremybenn
* -q <1>:                                Profiling Utility.   (line  30)
3948
* -q:                                    Standalone Simulator.
3949
                                                              (line  29)
3950 450 jeremybenn
* -t <1>:                                Trace Generation.    (line  15)
3951 420 jeremybenn
* -t:                                    Standalone Simulator.
3952
                                                              (line  39)
3953 346 jeremybenn
* -V:                                    Standalone Simulator.
3954
                                                              (line  33)
3955 19 jeremybenn
* -v:                                    Standalone Simulator.
3956 346 jeremybenn
                                                              (line  17)
3957 19 jeremybenn
* -v (memory profiling utility):         Memory Profiling Utility.
3958
                                                              (line  17)
3959
* -v (profiling utility):                Profiling Utility.   (line  17)
3960
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3961
                                                              (line  49)
3962
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3963
                                                              (line  55)
3964
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3965
                                                              (line  59)
3966
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3967
                                                              (line  62)
3968
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3969
                                                              (line  66)
3970
* 16550 (UART configuration):            UART Configuration.  (line  73)
3971 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3972 127 jeremybenn
                                                              (line 105)
3973 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3974 127 jeremybenn
                                                              (line  98)
3975 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3976
                                                              (line   6)
3977
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3978 385 jeremybenn
                                                              (line  92)
3979 19 jeremybenn
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3980
                                                              (line  32)
3981
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3982 385 jeremybenn
                                                              (line  26)
3983 19 jeremybenn
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3984
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3985 440 jeremybenn
                                                              (line  23)
3986 19 jeremybenn
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3987
                                                              (line  20)
3988
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3989
                                                              (line  22)
3990
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3991
* baseaddr (keyboard configuration):     Keyboard Configuration.
3992
                                                              (line  36)
3993
* baseaddr (memory configuration):       Memory Configuration.
3994 418 julius
                                                              (line  94)
3995 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3996 385 jeremybenn
                                                              (line  55)
3997 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3998
* baseaddr (VGA configuration):          Display Interface Configuration.
3999
                                                              (line  26)
4000
* blocksize (cache configuration):       Cache Configuration. (line  29)
4001
* BPB configuration:                     Branch Prediction Configuration.
4002
                                                              (line   6)
4003
* branch prediction configuration:       Branch Prediction Configuration.
4004
                                                              (line   6)
4005
* break (Interactive CLI):               Interactive Command Line.
4006
                                                              (line  57)
4007
* breakpoint list (Interactive CLI):     Interactive Command Line.
4008
                                                              (line  60)
4009
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
4010
                                                              (line  57)
4011
* breaks (Interactive CLI):              Interactive Command Line.
4012
                                                              (line  60)
4013 440 jeremybenn
* bridge setup:                          Establishing a Bridge.
4014
                                                              (line   6)
4015 19 jeremybenn
* btic (branch prediction configuration): Branch Prediction Configuration.
4016
                                                              (line  19)
4017 440 jeremybenn
* BusyBox and Ethernet:                  Networking from OpenRISC Linux and BusyBox.
4018
                                                              (line   6)
4019 19 jeremybenn
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
4020
                                                              (line  48)
4021
* cache configuration:                   Cache Configuration. (line   6)
4022 346 jeremybenn
* calling_convention (CUC configuration): CUC Configuration.  (line  37)
4023 19 jeremybenn
* ce (memory configuration):             Memory Configuration.
4024 418 julius
                                                              (line 124)
4025 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
4026
* channel (UART configuration):          UART Configuration.  (line  29)
4027
* clear breakpoint (Interactive CLI):    Interactive Command Line.
4028
                                                              (line  57)
4029 432 jeremybenn
* clear_interrupt:                       Concepts.            (line  20)
4030 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
4031 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
4032
                                                              (line  54)
4033
* command line for Or1ksim standalone use: Standalone Simulator.
4034
                                                              (line   6)
4035
* complex model:                         Configuring the Build.
4036 104 jeremybenn
                                                              (line  37)
4037 19 jeremybenn
* config:                                Global Data Structures.
4038
                                                              (line   7)
4039
* config.bpb:                            Global Data Structures.
4040
                                                              (line  37)
4041
* config.cpu:                            Global Data Structures.
4042
                                                              (line  22)
4043
* config.cuc:                            Global Data Structures.
4044
                                                              (line  18)
4045
* config.dc:                             Global Data Structures.
4046
                                                              (line  25)
4047
* config.debug:                          Global Data Structures.
4048
                                                              (line  40)
4049
* config.pic:                            Global Data Structures.
4050
                                                              (line  33)
4051
* config.pm:                             Global Data Structures.
4052
                                                              (line  29)
4053
* config.sim:                            Global Data Structures.
4054
                                                              (line  11)
4055
* config.vapi:                           Global Data Structures.
4056
                                                              (line  14)
4057
* configuration dynamic structure:       Global Data Structures.
4058
                                                              (line  49)
4059
* configuration file structure:          Configuration File Format.
4060
                                                              (line   6)
4061
* configuration global structure:        Global Data Structures.
4062
                                                              (line   7)
4063
* configuration info (Interactive CLI):  Interactive Command Line.
4064
                                                              (line 119)
4065
* configuration of generic peripherals:  Generic Peripheral Configuration.
4066
                                                              (line   6)
4067
* configuration parameter setting (Interactive CLI): Interactive Command Line.
4068
                                                              (line 146)
4069
* configuring branch prediction:         Branch Prediction Configuration.
4070
                                                              (line   6)
4071
* configuring data & instruction caches: Cache Configuration. (line   6)
4072
* configuring data & instruction MMUs:   Memory Management Configuration.
4073
                                                              (line   6)
4074
* configuring DMA:                       DMA Configuration.   (line   6)
4075
* configuring memory:                    Memory Configuration.
4076
                                                              (line   6)
4077
* configuring Or1ksim:                   Configuration.       (line   6)
4078
* configuring power management:          Power Management Configuration.
4079
                                                              (line   6)
4080
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
4081
                                                              (line   6)
4082
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
4083
* configuring the CPU:                   CPU Configuration.   (line   6)
4084
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
4085
                                                              (line   6)
4086
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
4087
                                                              (line   6)
4088
* configuring the Ethernet interface:    Ethernet Configuration.
4089
                                                              (line   6)
4090 440 jeremybenn
* configuring the Ethernet TUN/TAP interface: Ethernet TUN/TAP Interface.
4091
                                                              (line   6)
4092 19 jeremybenn
* configuring the frame buffer:          Frame Buffer Configuration.
4093
                                                              (line   6)
4094
* configuring the GPIO:                  GPIO Configuration.  (line   6)
4095
* configuring the interrupt controller:  Interrupt Configuration.
4096
                                                              (line   6)
4097
* configuring the keyboard interface:    Keyboard Configuration.
4098
                                                              (line   6)
4099
* configuring the memory controller:     Memory Controller Configuration.
4100
                                                              (line   6)
4101
* configuring the processor:             CPU Configuration.   (line   6)
4102
* configuring the PS2 interface:         Keyboard Configuration.
4103
                                                              (line   6)
4104
* configuring the UART:                  UART Configuration.  (line   6)
4105
* configuring the Verification API (VAPI): Verification API Configuration.
4106
                                                              (line   6)
4107
* configuring the VGA interface:         Display Interface Configuration.
4108
                                                              (line   6)
4109
* copying memory (Interactive CLI):      Interactive Command Line.
4110
                                                              (line  54)
4111
* CPU configuration:                     CPU Configuration.   (line   6)
4112
* CUC configuration:                     CUC Configuration.   (line   6)
4113
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
4114
                                                              (line 162)
4115
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
4116
* data cache configuration:              Cache Configuration. (line   6)
4117
* data MMU configuration:                Memory Management Configuration.
4118
                                                              (line   6)
4119
* DCGE (power management register):      Power Management Configuration.
4120
                                                              (line  21)
4121
* debug (Interactive CLI):               Interactive Command Line.
4122 346 jeremybenn
                                                              (line 151)
4123 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
4124
* debug channel toggle (Interactive CLI): Interactive Command Line.
4125
                                                              (line 141)
4126
* debug interface configuration:         Debug Interface Configuration.
4127
                                                              (line   6)
4128
* debug mode toggle (Interactive CLI):   Interactive Command Line.
4129
                                                              (line 151)
4130
* debug unit configuration:              Debug Interface Configuration.
4131
                                                              (line   6)
4132
* Debug Unit verification (VAPI):        Verification API.    (line  34)
4133
* debugging enabled (Argtable2):         Configuring the Build.
4134 127 jeremybenn
                                                              (line  98)
4135 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
4136
* DejaGnu configuration:                 Regression Testing.  (line  21)
4137
* DejaGNU tests directories:             Regression Testing.  (line  50)
4138
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
4139 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
4140 418 julius
                                                              (line 144)
4141 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
4142 418 julius
                                                              (line 150)
4143 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
4144 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
4145 385 jeremybenn
                                                              (line  40)
4146 19 jeremybenn
* disassemble (Interactive CLI):         Interactive Command Line.
4147
                                                              (line  41)
4148
* disc interface configuration:          Disc Interface Configuration.
4149
                                                              (line   6)
4150
* disc interface device configuration:   Disc Interface Configuration.
4151 385 jeremybenn
                                                              (line  92)
4152 19 jeremybenn
* display interface configuration:       Display Interface Configuration.
4153
                                                              (line   6)
4154
* displaying memory (Interactive CLI):   Interactive Command Line.
4155
                                                              (line  31)
4156
* displaying registers (Interactive CLI): Interactive Command Line.
4157
                                                              (line  14)
4158
* dm (Interactive CLI):                  Interactive Command Line.
4159
                                                              (line  31)
4160
* dma (Ethernet configuration):          Ethernet Configuration.
4161 440 jeremybenn
                                                              (line  34)
4162 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
4163
* DMA verification (VAPI):               Verification API.    (line  73)
4164
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
4165 385 jeremybenn
                                                              (line  74)
4166 19 jeremybenn
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4167 385 jeremybenn
                                                              (line  75)
4168 19 jeremybenn
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
4169 385 jeremybenn
                                                              (line  73)
4170 19 jeremybenn
* DME (power management register):       Power Management Configuration.
4171
                                                              (line  15)
4172
* DMMU configuration:                    Memory Management Configuration.
4173
                                                              (line   6)
4174
* doze mode (power management register): Power Management Configuration.
4175
                                                              (line  15)
4176 451 jeremybenn
* dummy_crc (Ethernet configuration):    Ethernet Configuration.
4177
                                                              (line 104)
4178 19 jeremybenn
* dv (Interactive CLI):                  Interactive Command Line.
4179
                                                              (line 124)
4180
* dynamic clock gating (power management register): Power Management Configuration.
4181
                                                              (line  21)
4182
* dynamic model:                         Configuring the Build.
4183 104 jeremybenn
                                                              (line  37)
4184 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
4185
                                                              (line  23)
4186
* edge_trigger (interrupt controller):   Interrupt Configuration.
4187
                                                              (line  16)
4188 346 jeremybenn
* enable_bursts (CUC configuration):     CUC Configuration.   (line  41)
4189 19 jeremybenn
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
4190 385 jeremybenn
                                                              (line  22)
4191 19 jeremybenn
* enabled (branch prediction configuration): Branch Prediction Configuration.
4192
                                                              (line  15)
4193
* enabled (cache configuration):         Cache Configuration. (line  11)
4194
* enabled (debug interface configuration): Debug Interface Configuration.
4195
                                                              (line  11)
4196
* enabled (DMA configuration):           DMA Configuration.   (line  20)
4197
* enabled (Ethernet configuration):      Ethernet Configuration.
4198 440 jeremybenn
                                                              (line  19)
4199 19 jeremybenn
* enabled (frame buffer configuration):  Frame Buffer Configuration.
4200
                                                              (line  16)
4201
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
4202
                                                              (line  18)
4203
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
4204
* enabled (interrupt controller):        Interrupt Configuration.
4205
                                                              (line  12)
4206
* enabled (keyboard configuration):      Keyboard Configuration.
4207
                                                              (line  32)
4208
* enabled (memory controller configuration): Memory Controller Configuration.
4209 385 jeremybenn
                                                              (line  44)
4210 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
4211
                                                              (line  12)
4212
* enabled (power management configuration): Power Management Configuration.
4213
                                                              (line  35)
4214
* enabled (UART configuration):          UART Configuration.  (line  18)
4215
* enabled (verification API configuration): Verification API Configuration.
4216
                                                              (line  15)
4217
* enabled (VGA configuration):           Display Interface Configuration.
4218
                                                              (line  22)
4219
* enabling Ethernet via socket:          Configuring the Build.
4220 104 jeremybenn
                                                              (line  59)
4221 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
4222
                                                              (line  32)
4223
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
4224
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
4225 440 jeremybenn
* Ethernet bridge setup:                 Establishing a Bridge.
4226
                                                              (line   6)
4227 19 jeremybenn
* Ethernet configuration:                Ethernet Configuration.
4228
                                                              (line   6)
4229
* Ethernet verification (VAPI):          Verification API.    (line  78)
4230
* Ethernet via socket, enabling:         Configuring the Build.
4231 104 jeremybenn
                                                              (line  59)
4232 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
4233
                                                              (line  69)
4234 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
4235
                                                              (line 103)
4236
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
4237
                                                              (line 111)
4238 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
4239
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
4240
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
4241 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
4242 82 jeremybenn
                                                              (line  97)
4243 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
4244 82 jeremybenn
                                                              (line  93)
4245 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
4246 82 jeremybenn
                                                              (line  86)
4247
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
4248 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
4249 82 jeremybenn
                                                              (line  58)
4250 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
4251 82 jeremybenn
                                                              (line  62)
4252 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
4253 82 jeremybenn
                                                              (line  69)
4254 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
4255 82 jeremybenn
                                                              (line  74)
4256 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
4257
                                                              (line  23)
4258
* execution history (Interactive CLI):   Interactive Command Line.
4259
                                                              (line  67)
4260
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
4261 385 jeremybenn
                                                              (line 108)
4262 19 jeremybenn
* file (keyboard configuration):         Keyboard Configuration.
4263
                                                              (line  51)
4264
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
4265 82 jeremybenn
                                                              (line  36)
4266 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
4267
                                                              (line  47)
4268 440 jeremybenn
* firewall with Ethernet bridge and TAP/TUN: Opening the Firewall.
4269
                                                              (line   6)
4270 19 jeremybenn
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
4271 385 jeremybenn
                                                              (line 121)
4272 19 jeremybenn
* flag setting by instructions:          Configuring the Build.
4273 127 jeremybenn
                                                              (line 118)
4274 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
4275
                                                              (line   6)
4276
* generic peripheral configuration:      Generic Peripheral Configuration.
4277
                                                              (line   6)
4278
* GPIO configuration:                    GPIO Configuration.  (line   6)
4279
* GPIO verification (VAPI):              Verification API.    (line  88)
4280
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
4281
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
4282
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
4283
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
4284
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
4285
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
4286
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
4287 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
4288 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
4289 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
4290 385 jeremybenn
                                                              (line 125)
4291 19 jeremybenn
* help (Interactive CLI):                Interactive Command Line.
4292
                                                              (line 170)
4293
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
4294
                                                              (line 133)
4295
* hide_device_id (verification API configuration): Verification API Configuration.
4296
                                                              (line  36)
4297
* hist (Interactive CLI):                Interactive Command Line.
4298
                                                              (line  67)
4299 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
4300 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
4301
                                                              (line  67)
4302
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
4303
                                                              (line  33)
4304
* hitdelay (instruction cache configuration): Cache Configuration.
4305
                                                              (line  38)
4306
* hitdelay (MMU configuration):          Memory Management Configuration.
4307
                                                              (line  51)
4308 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
4309 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
4310
                                                              (line  49)
4311
* IMMU configuration:                    Memory Management Configuration.
4312
                                                              (line   6)
4313
* index (memory controller configuration): Memory Controller Configuration.
4314 385 jeremybenn
                                                              (line  77)
4315 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
4316
                                                              (line 119)
4317
* installing Or1ksim:                    Installation.        (line   6)
4318
* instruction cache configuration:       Cache Configuration. (line   6)
4319
* instruction MMU configuration:         Memory Management Configuration.
4320
                                                              (line   6)
4321
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
4322
* instruction profiling utility (Interactive CLI): Interactive Command Line.
4323
                                                              (line 178)
4324
* internal debugging:                    Internal Debugging.  (line   6)
4325
* interrupt controller configuration:    Interrupt Configuration.
4326
                                                              (line   6)
4327 432 jeremybenn
* interrupts:                            Concepts.            (line  20)
4328 19 jeremybenn
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
4329 385 jeremybenn
                                                              (line  36)
4330 19 jeremybenn
* irq (DMA configuration):               DMA Configuration.   (line  34)
4331
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
4332
* irq (keyboard configuration):          Keyboard Configuration.
4333
                                                              (line  47)
4334
* irq (UART configuration):              UART Configuration.  (line  70)
4335
* irq (VGA configuration):               Display Interface Configuration.
4336
                                                              (line  37)
4337
* jitter (UART configuration):           UART Configuration.  (line  78)
4338
* keyboard configuration:                Keyboard Configuration.
4339
                                                              (line   6)
4340 460 jeremybenn
* l.nop 0:                               l.nop Support.       (line  12)
4341
* l.nop 1 (end simulation):              l.nop Support.       (line  15)
4342
* l.nop 2 (report):                      l.nop Support.       (line  19)
4343
* l.nop 3 (printf, now obsolete):        l.nop Support.       (line  22)
4344
* l.nop 4 (putc):                        l.nop Support.       (line  29)
4345
* l.nop 5 (reset statistics counters):   l.nop Support.       (line  34)
4346
* l.nop 6 (get clock ticks):             l.nop Support.       (line  37)
4347
* l.nop 7 (get picoseconds per cycle):   l.nop Support.       (line  41)
4348
* l.nop 8 (turn on tracing):             l.nop Support.       (line  45)
4349
* l.nop 9 (turn off tracing):            l.nop Support.       (line  48)
4350
* l.nop opcode effects:                  l.nop Support.       (line   6)
4351 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
4352
* license for Or1ksim:                   GNU Free Documentation License.
4353
                                                              (line   6)
4354 440 jeremybenn
* Linux (OpenRISC) and Ethernet:         Networking from OpenRISC Linux and BusyBox.
4355
                                                              (line   6)
4356 19 jeremybenn
* list breakpoints (Interactive CLI):    Interactive Command Line.
4357
                                                              (line  60)
4358
* load_hitdelay (data cache configuration): Cache Configuration.
4359
                                                              (line  46)
4360
* load_missdelay (data cache configuration): Cache Configuration.
4361
                                                              (line  50)
4362
* log (memory configuration):            Memory Configuration.
4363 418 julius
                                                              (line 156)
4364 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
4365
                                                              (line  28)
4366 432 jeremybenn
* long:                                  Simulator Library.   (line  94)
4367 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
4368 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
4369 418 julius
                                                              (line 133)
4370 19 jeremybenn
* memory configuration:                  Memory Configuration.
4371
                                                              (line   6)
4372
* memory controller configuration:       Memory Controller Configuration.
4373
                                                              (line   6)
4374
* memory copying (Interactive CLI):      Interactive Command Line.
4375
                                                              (line  54)
4376
* memory display (Interactive CLI):      Interactive Command Line.
4377
                                                              (line  31)
4378
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
4379
                                                              (line 133)
4380
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
4381
                                                              (line 124)
4382
* memory patching (Interactive CLI):     Interactive Command Line.
4383
                                                              (line  48)
4384
* memory profiling end address:          Memory Profiling Utility.
4385
                                                              (line  56)
4386
* memory profiling start address:        Memory Profiling Utility.
4387
                                                              (line  56)
4388
* memory profiling utility (Interactive CLI): Interactive Command Line.
4389
                                                              (line 173)
4390
* memory profiling version of Or1ksim:   Memory Profiling Utility.
4391
                                                              (line   6)
4392
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
4393 346 jeremybenn
* memory_order=exact (CUC configuration): CUC Configuration.  (line  30)
4394 19 jeremybenn
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
4395 346 jeremybenn
* memory_order=strong (CUC configuration): CUC Configuration. (line  27)
4396
* memory_order=weak (CUC configuration): CUC Configuration.   (line  22)
4397 19 jeremybenn
* missdelay (branch prediction configuration): Branch Prediction Configuration.
4398
                                                              (line  37)
4399
* missdelay (instruction cache configuration): Cache Configuration.
4400
                                                              (line  42)
4401
* missdelay (MMU configuration):         Memory Management Configuration.
4402
                                                              (line  55)
4403
* MMU configuration:                     Memory Management Configuration.
4404
                                                              (line   6)
4405 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
4406 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
4407 82 jeremybenn
                                                              (line  34)
4408 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
4409 346 jeremybenn
                                                              (line 173)
4410 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
4411 432 jeremybenn
* mtspr:                                 Concepts.            (line  20)
4412 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
4413 385 jeremybenn
                                                              (line 132)
4414 19 jeremybenn
* name (generic peripheral configuration): Generic Peripheral Configuration.
4415
                                                              (line  42)
4416
* name (memory configuration):           Memory Configuration.
4417 418 julius
                                                              (line 115)
4418 346 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  45)
4419 19 jeremybenn
* nsets (cache configuration):           Cache Configuration. (line  15)
4420
* nsets (MMU configuration):             Memory Management Configuration.
4421
                                                              (line  16)
4422
* nways (cache configuration):           Cache Configuration. (line  22)
4423
* nways (MMU configuration):             Memory Management Configuration.
4424
                                                              (line  22)
4425 432 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  84)
4426
* or1ksim_init:                          Simulator Library.   (line  19)
4427
* or1ksim_interrupt:                     Simulator Library.   (line  99)
4428
* or1ksim_interrupt_clear:               Simulator Library.   (line 121)
4429
* or1ksim_interrupt_set:                 Simulator Library.   (line 110)
4430
* or1ksim_is_le:                         Simulator Library.   (line  89)
4431
* or1ksim_jtag_reset:                    Simulator Library.   (line 130)
4432
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 152)
4433
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 139)
4434
* or1ksim_read_mem:                      Simulator Library.   (line 165)
4435
* or1ksim_read_reg:                      Simulator Library.   (line 197)
4436 346 jeremybenn
* or1ksim_read_spr:                      Simulator Library.   (line 181)
4437 432 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  69)
4438
* or1ksim_run:                           Simulator Library.   (line  58)
4439
* or1ksim_set_stall_state:               Simulator Library.   (line 212)
4440
* or1ksim_set_time_point:                Simulator Library.   (line  80)
4441
* or1ksim_write_mem:                     Simulator Library.   (line 173)
4442
* or1ksim_write_reg:                     Simulator Library.   (line 205)
4443
* or1ksim_write_spr:                     Simulator Library.   (line 189)
4444 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
4445
* overflow flag setting by instructions: Configuring the Build.
4446 127 jeremybenn
                                                              (line 133)
4447 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
4448 385 jeremybenn
                                                              (line 117)
4449 19 jeremybenn
* pagesize (MMU configuration):          Memory Management Configuration.
4450
                                                              (line  27)
4451
* patching memory (Interactive CLI):     Interactive Command Line.
4452
                                                              (line  48)
4453
* patching registers (Interactive CLI):  Interactive Command Line.
4454
                                                              (line  28)
4455
* patching the program counter (Interactive CLI): Interactive Command Line.
4456
                                                              (line  51)
4457
* pattern (memory configuration):        Memory Configuration.
4458 418 julius
                                                              (line  82)
4459 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4460
                                                              (line  51)
4461 440 jeremybenn
* persistent TAP device creation:        Setting Up a Persistent TAP device.
4462
                                                              (line   6)
4463 429 julius
* phy_addr:                              Ethernet Configuration.
4464 451 jeremybenn
                                                              (line  99)
4465 19 jeremybenn
* PIC configuration:                     Interrupt Configuration.
4466
                                                              (line   6)
4467
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4468 385 jeremybenn
                                                              (line 136)
4469 19 jeremybenn
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4470 385 jeremybenn
                                                              (line  55)
4471 19 jeremybenn
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4472 385 jeremybenn
                                                              (line  56)
4473 19 jeremybenn
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4474 385 jeremybenn
                                                              (line  57)
4475 19 jeremybenn
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4476 385 jeremybenn
                                                              (line  58)
4477 19 jeremybenn
* pm (Interactive CLI):                  Interactive Command Line.
4478
                                                              (line  48)
4479
* PMR - DGCE:                            Power Management Configuration.
4480
                                                              (line  21)
4481
* PMR - DME:                             Power Management Configuration.
4482
                                                              (line  15)
4483
* PMR - SDF:                             Power Management Configuration.
4484
                                                              (line  12)
4485
* PMR - SME:                             Power Management Configuration.
4486
                                                              (line  16)
4487
* PMR - SUME:                            Power Management Configuration.
4488
                                                              (line  24)
4489
* PMU configuration:                     Power Management Configuration.
4490
                                                              (line   6)
4491
* poc (memory controller configuration): Memory Controller Configuration.
4492 385 jeremybenn
                                                              (line  64)
4493 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4494
                                                              (line  23)
4495
* power management configuration:        Power Management Configuration.
4496
                                                              (line   6)
4497
* power management register, DGCE:       Power Management Configuration.
4498
                                                              (line  21)
4499
* power management register, DME:        Power Management Configuration.
4500
                                                              (line  15)
4501
* power management register, SDF:        Power Management Configuration.
4502
                                                              (line  12)
4503
* power management register, SME:        Power Management Configuration.
4504
                                                              (line  16)
4505
* power management register, SUME:       Power Management Configuration.
4506
                                                              (line  24)
4507
* pr (Interactive CLI):                  Interactive Command Line.
4508
                                                              (line  28)
4509
* private ports, use of:                 Verification API Configuration.
4510
                                                              (line  23)
4511
* processor configuration:               CPU Configuration.   (line   6)
4512
* processor stall (Interactive CLI):     Interactive Command Line.
4513
                                                              (line  72)
4514
* processor unstall (Interactive CLI):   Interactive Command Line.
4515
                                                              (line  78)
4516
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4517
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4518
                                                              (line  23)
4519
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4520
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4521
* profiling utility (Interactive CLI):   Interactive Command Line.
4522
                                                              (line 178)
4523
* program counter patching (Interactive CLI): Interactive Command Line.
4524
                                                              (line  51)
4525
* programmable interrupt controller configuration: Interrupt Configuration.
4526
                                                              (line   6)
4527
* PS2 configuration:                     Keyboard Configuration.
4528
                                                              (line   6)
4529
* q (Interactive CLI):                   Interactive Command Line.
4530
                                                              (line  11)
4531
* quitting (Interactive CLI):            Interactive Command Line.
4532
                                                              (line  11)
4533
* r (Interactive CLI):                   Interactive Command Line.
4534
                                                              (line  14)
4535
* random_seed (memory configuration):    Memory Configuration.
4536 418 julius
                                                              (line  72)
4537 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4538 82 jeremybenn
                                                              (line  30)
4539 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4540
                                                              (line  41)
4541
* reg_sim_reset:                         Concepts.            (line  13)
4542
* register display (Interactive CLI):    Interactive Command Line.
4543
                                                              (line  14)
4544
* register over time statistics:         Configuring the Build.
4545 127 jeremybenn
                                                              (line  92)
4546 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4547
                                                              (line  28)
4548 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4549 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4550
                                                              (line  20)
4551 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4552 385 jeremybenn
                                                              (line  52)
4553 235 jeremybenn
* Remote Serial Protocol, --srv:         Standalone Simulator.
4554 385 jeremybenn
                                                              (line  60)
4555 432 jeremybenn
* report_interrupt:                      Concepts.            (line  20)
4556 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4557
                                                              (line  63)
4558
* reset hooks:                           Concepts.            (line  13)
4559
* reset the simulator (Interactive CLI): Interactive Command Line.
4560
                                                              (line  63)
4561
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4562 385 jeremybenn
                                                              (line  48)
4563 19 jeremybenn
* rev (CPU configuration):               CPU Configuration.   (line  15)
4564
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4565
                                                              (line  20)
4566
* rsp_port (debug interface configuration): Debug Interface Configuration.
4567 235 jeremybenn
                                                              (line  32)
4568 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4569 440 jeremybenn
                                                              (line  47)
4570 19 jeremybenn
* run (Interactive CLI):                 Interactive Command Line.
4571
                                                              (line  23)
4572
* running code (Interactive CLI):        Interactive Command Line.
4573
                                                              (line  23)
4574
* running Or1ksim:                       Usage.               (line   6)
4575
* runtime:                               Global Data Structures.
4576
                                                              (line  58)
4577
* runtime global structure:              Global Data Structures.
4578
                                                              (line  58)
4579
* runtime.cpu:                           Global Data Structures.
4580
                                                              (line  62)
4581
* runtime.cpu.fout:                      Concepts.            (line   7)
4582
* runtime.cuc:                           Global Data Structures.
4583
                                                              (line  62)
4584
* runtime.vapi:                          Global Data Structures.
4585
                                                              (line  62)
4586
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4587 440 jeremybenn
                                                              (line  67)
4588 19 jeremybenn
* rxfile (Ethernet configuration):       Ethernet Configuration.
4589 440 jeremybenn
                                                              (line  76)
4590 19 jeremybenn
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4591
                                                              (line  23)
4592
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4593
                                                              (line  28)
4594 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4595 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4596
                                                              (line  12)
4597
* section ata:                           Disc Interface Configuration.
4598
                                                              (line   6)
4599
* section bpb:                           Branch Prediction Configuration.
4600
                                                              (line   6)
4601
* section cpio:                          GPIO Configuration.  (line   6)
4602
* section cpu:                           CPU Configuration.   (line   6)
4603
* section cuc:                           CUC Configuration.   (line   6)
4604
* section dc:                            Cache Configuration. (line   6)
4605
* section debug:                         Debug Interface Configuration.
4606
                                                              (line   6)
4607
* section dma:                           DMA Configuration.   (line   6)
4608
* section dmmu:                          Memory Management Configuration.
4609
                                                              (line   6)
4610
* section ethernet:                      Ethernet Configuration.
4611
                                                              (line   6)
4612
* section fb:                            Frame Buffer Configuration.
4613
                                                              (line   6)
4614
* section generic:                       Generic Peripheral Configuration.
4615
                                                              (line   6)
4616
* section ic:                            Cache Configuration. (line   6)
4617
* section immu:                          Memory Management Configuration.
4618
                                                              (line   6)
4619
* section kb:                            Keyboard Configuration.
4620
                                                              (line   6)
4621
* section mc:                            Memory Controller Configuration.
4622
                                                              (line   6)
4623
* section memory:                        Memory Configuration.
4624
                                                              (line   6)
4625
* section pic:                           Interrupt Configuration.
4626
                                                              (line   6)
4627
* section pmu:                           Power Management Configuration.
4628
                                                              (line   6)
4629
* section sim:                           Simulator Behavior.  (line   6)
4630
* section uart:                          UART Configuration.  (line   6)
4631
* section vapi:                          Verification API Configuration.
4632
                                                              (line   6)
4633
* section vga:                           Display Interface Configuration.
4634
                                                              (line   6)
4635
* sections:                              Global Data Structures.
4636
                                                              (line  49)
4637
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4638 385 jeremybenn
                                                              (line 129)
4639 19 jeremybenn
* server_port (verification API configuration): Verification API Configuration.
4640
                                                              (line  19)
4641
* set (Interactive CLI):                 Interactive Command Line.
4642
                                                              (line 146)
4643
* set breakpoint (Interactive CLI):      Interactive Command Line.
4644
                                                              (line  57)
4645
* setdbch (Interactive CLI):             Interactive Command Line.
4646
                                                              (line 141)
4647
* simple model:                          Configuring the Build.
4648 104 jeremybenn
                                                              (line  37)
4649 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4650
* simulator configuration info (Interactive CLI): Interactive Command Line.
4651
                                                              (line 119)
4652
* simulator reset (Interactive CLI):     Interactive Command Line.
4653
                                                              (line  63)
4654
* simulator statistics (Interactive CLI): Interactive Command Line.
4655
                                                              (line  83)
4656
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4657 385 jeremybenn
                                                              (line 113)
4658 19 jeremybenn
* size (generic peripheral configuration): Generic Peripheral Configuration.
4659
                                                              (line  30)
4660
* size (memory configuration):           Memory Configuration.
4661 418 julius
                                                              (line  99)
4662 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4663
                                                              (line  16)
4664
* slow down factor (power management register): Power Management Configuration.
4665
                                                              (line  12)
4666
* SME (power management register):       Power Management Configuration.
4667
                                                              (line  16)
4668
* sr (CPU configuration):                CPU Configuration.   (line  53)
4669
* stall (Interactive CLI):               Interactive Command Line.
4670
                                                              (line  72)
4671
* stall the processor (Interactive CLI): Interactive Command Line.
4672
                                                              (line  72)
4673
* statistics, register over time:        Configuring the Build.
4674 127 jeremybenn
                                                              (line  92)
4675 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4676
                                                              (line  83)
4677
* stats (Interactive CLI):               Interactive Command Line.
4678
                                                              (line  83)
4679
* stepping code (Interactive CLI):       Interactive Command Line.
4680
                                                              (line  19)
4681
* store_hitdelay (data cache configuration): Cache Configuration.
4682
                                                              (line  54)
4683
* store_missdelay (data cache configuration): Cache Configuration.
4684
                                                              (line  58)
4685
* SUME (power management register):      Power Management Configuration.
4686
                                                              (line  24)
4687 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4688 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4689
                                                              (line  24)
4690
* t (Interactive CLI):                   Interactive Command Line.
4691
                                                              (line  19)
4692 440 jeremybenn
* TAP device creation:                   Setting Up a Persistent TAP device.
4693
                                                              (line   6)
4694
* tap_dev (Ethernet configuration):      Ethernet Configuration.
4695
                                                              (line  93)
4696 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4697 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4698
                                                              (line  23)
4699
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4700 235 jeremybenn
                                                              (line  37)
4701 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4702
* test code for target:                  Regression Testing.  (line  63)
4703
* test make file:                        Regression Testing.  (line  27)
4704
* test README:                           Regression Testing.  (line  32)
4705
* testing:                               Regression Testing.  (line   6)
4706 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4707 127 jeremybenn
                                                              (line 105)
4708 346 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  49)
4709 19 jeremybenn
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4710 346 jeremybenn
                                                              (line  49)
4711 19 jeremybenn
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4712
                                                              (line  57)
4713
* toggle debug channels (Interactive CLI): Interactive Command Line.
4714
                                                              (line 141)
4715
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4716
                                                              (line 151)
4717 442 julius
* trace generation of Or1ksim:           Trace Generation.    (line   6)
4718 19 jeremybenn
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4719 440 jeremybenn
                                                              (line  68)
4720 19 jeremybenn
* txfile (Ethernet configuration):       Ethernet Configuration.
4721 440 jeremybenn
                                                              (line  77)
4722 19 jeremybenn
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4723 82 jeremybenn
                                                              (line  36)
4724 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4725
                                                              (line  47)
4726
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4727 385 jeremybenn
                                                              (line 103)
4728 19 jeremybenn
* type (memory configuration):           Memory Configuration.
4729 385 jeremybenn
                                                              (line  37)
4730 418 julius
* type=exitnops (memory configuration):  Memory Configuration.
4731 420 jeremybenn
                                                              (line  66)
4732 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4733 385 jeremybenn
                                                              (line  47)
4734 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4735 385 jeremybenn
                                                              (line  41)
4736 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4737 385 jeremybenn
                                                              (line  51)
4738 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4739 385 jeremybenn
                                                              (line  56)
4740 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4741
* UART I/O from/to a physical serial port: UART Configuration.
4742
                                                              (line  62)
4743
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4744
* UART I/O from/to files:                UART Configuration.  (line  33)
4745
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4746
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4747
* UART verification (VAPI):              Verification API.    (line  41)
4748
* unstall (Interactive CLI):             Interactive Command Line.
4749
                                                              (line  78)
4750
* unstall the processor (Interactive CLI): Interactive Command Line.
4751
                                                              (line  78)
4752
* upr (CPU configuration):               CPU Configuration.   (line  21)
4753 432 jeremybenn
* use_nmi (interrupt controller):        Interrupt Configuration.
4754
                                                              (line  30)
4755 19 jeremybenn
* ustates (cache configuration):         Cache Configuration. (line  33)
4756
* ustates (MMU configuration):           Memory Management Configuration.
4757
                                                              (line  41)
4758
* VAPI configuration:                    Verification API Configuration.
4759
                                                              (line   6)
4760
* VAPI for Debug Unit:                   Verification API.    (line  34)
4761
* VAPI for DMA:                          Verification API.    (line  73)
4762
* VAPI for Ethernet:                     Verification API.    (line  78)
4763
* VAPI for GPIO:                         Verification API.    (line  88)
4764
* VAPI for UART:                         Verification API.    (line  41)
4765
* vapi_id (debug interface configuration): Debug Interface Configuration.
4766 235 jeremybenn
                                                              (line  43)
4767 346 jeremybenn
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4768 451 jeremybenn
                                                              (line 119)
4769 346 jeremybenn
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4770 19 jeremybenn
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4771
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4772
* vapi_log_file (verification API configuration): Verification API Configuration.
4773
                                                              (line  41)
4774
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4775
                                                              (line  41)
4776
* ver (CPU configuration):               CPU Configuration.   (line  15)
4777
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4778
* Verification API configuration:        Verification API Configuration.
4779
                                                              (line   6)
4780
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4781
                                                              (line 124)
4782
* VGA configuration:                     Display Interface Configuration.
4783
 
4784
 
4785
                                                              (line  50)
4786
4787
4788

4789
Tag Table:
4790 450 jeremybenn
Node: Top810
4791
Node: Installation1220
4792
Node: Preparation1467
4793
Node: Configuring the Build1762
4794
Node: Build and Install7902
4795
Node: Known Issues8668
4796
Node: Usage9723
4797 460 jeremybenn
Node: Standalone Simulator10007
4798
Node: Profiling Utility14567
4799
Node: Memory Profiling Utility15473
4800
Node: Trace Generation16833
4801
Node: Simulator Library18075
4802
Node: Ethernet TUN/TAP Interface28507
4803
Node: Setting Up a Persistent TAP device29612
4804
Node: Establishing a Bridge30287
4805
Node: Opening the Firewall31970
4806
Node: Disabling Ethernet Filtering32461
4807
Node: Networking from OpenRISC Linux and BusyBox33086
4808
Node: Tearing Down a Bridge34748
4809
Node: l.nop Support35491
4810
Node: Configuration37001
4811
Node: Configuration File Format37613
4812
Node: Configuration File Preprocessing37998
4813
Node: Configuration File Syntax38295
4814
Node: Simulator Configuration41080
4815
Node: Simulator Behavior41371
4816
Node: Verification API Configuration45952
4817
Node: CUC Configuration47892
4818
Node: Core OpenRISC Configuration49884
4819
Node: CPU Configuration50386
4820
Node: Memory Configuration54505
4821
Node: Memory Management Configuration61227
4822
Node: Cache Configuration63604
4823
Node: Interrupt Configuration65990
4824
Node: Power Management Configuration67823
4825
Node: Branch Prediction Configuration69100
4826
Node: Debug Interface Configuration70460
4827
Node: Peripheral Configuration72803
4828
Node: Memory Controller Configuration73429
4829
Node: UART Configuration77209
4830
Node: DMA Configuration80728
4831
Node: Ethernet Configuration82595
4832
Node: GPIO Configuration87874
4833
Node: Display Interface Configuration89507
4834
Node: Frame Buffer Configuration91816
4835
Node: Keyboard Configuration93680
4836
Node: Disc Interface Configuration95918
4837
Node: Generic Peripheral Configuration101022
4838
Node: Interactive Command Line103317
4839
Node: Verification API110291
4840
Node: Code Internals114721
4841
Node: Coding Conventions115304
4842
Node: Global Data Structures119731
4843
Node: Concepts122388
4844
Ref: Output Redirection122533
4845
Ref: Interrupts Internal123071
4846
Node: Internal Debugging124224
4847
Node: Regression Testing124748
4848
Node: GNU Free Documentation License128537

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