OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.info] - Blame information for rev 557

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 538 julius
This is ../../or1ksim/doc/or1ksim.info, produced by makeinfo version
2
4.13 from ../../or1ksim/doc/or1ksim.texi.
3 19 jeremybenn
 
4
INFO-DIR-SECTION Embedded development
5
START-INFO-DIR-ENTRY
6 442 julius
* Or1ksim: (or32-elf-or1ksim).  The OpenRISC 1000 Architectural
7 19 jeremybenn
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 538 julius
     tar jxf or1ksim-2011-04-28.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 538 julius
     ../or1ksim-2011-04-28/configure --target=or32-elf ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 385 jeremybenn
For testing (using `make check'), the `--target' parameter may be
92
specified, to allow the target tool chain to be selected.  If not
93
specified, it will default to `or32-elf', which is the same prefix used
94
with the standard OpenRISC toolchain installation script.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
     Or1ksim has developed to improve functionality and performance.
108
     This feature allows three versions of Or1ksim to be built
109
 
110
    `--enable-execution=simple'
111
          Build the original simple interpreting simulator
112
 
113
    `--enable-execution=complex'
114 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
115
          suggest this is 50% faster than the simple simulator.  This
116
          is the default.
117 19 jeremybenn
 
118
 
119
     The default is `--enable-execution=complex'.
120
 
121
`--enable-ethphy'
122
`--disable-ethphy'
123
     If enabled, this option allows the Ethernet to be simulated by
124
     connecting via a socket (the alternative reads and writes, from
125 82 jeremybenn
     and to files).  This must then be configured using the relevant
126
     fields in the `ethernet' section of the configuration file.  *Note
127 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
128
 
129
     The default is for this to be disabled.
130
 
131 127 jeremybenn
`--enable-unsigned-xori'
132
`--disable-unsigned-xori'
133 346 jeremybenn
     Historically, `l.xori', has sign extended its operand.  This is
134 127 jeremybenn
     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
135
     but in the absence of `l.not', it allows a register to be inverted
136
     in a single instruction using:
137
 
138
          `l.xori  rD,rA,-1'
139
 
140
     This flag causes Or1ksim to treat the immediate operand as
141
     unsigned (i.e to zero-extend rather than sign-extend).
142
 
143
     The default is to sign-extend, so that existing code will continue
144
     to work.
145
 
146
          Caution: The GNU compiler tool chain makes heavy use of this
147
          instruction.  Using unsigned behavior will require the
148
          compiler to be modified accordingly.
149
 
150
          This option is provided for experimentation.  A future
151
          version of OpenRISC may adopt this more consistent behavior
152
          and also provide a `l.not' opcode.
153
 
154 19 jeremybenn
`--enable-range-stats'
155
`--disable-range-stats'
156
     If enabled, this option allows statistics to be collected to
157 82 jeremybenn
     analyse register access over time.  The default is for this to be
158 19 jeremybenn
     disabled.
159
 
160
`--enable-debug'
161
`--disable-debug'
162
     This is a feature of the Argtable2 package used to process
163 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
164
     Argtable2.  It is provided for completeness, but there is no
165
     reason why this feature should ever be needed by any Or1ksim user.
166 19 jeremybenn
 
167 82 jeremybenn
`--enable-all-tests'
168
`--disable-all-tests'
169
     Some of the tests (at the time of writing just one) will not
170
     compile without error.  If enabled with this flag, all test
171
     programs will be compiled with `make check'.
172 19 jeremybenn
 
173 82 jeremybenn
     This flag is intended for those working on the test package, who
174
     wish to get the missing test(s) working.
175
 
176
 
177 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
178 346 jeremybenn
because they led to invalid behavior of Or1ksim.  Those removed are:
179 112 jeremybenn
 
180 124 jeremybenn
`--enable-arith-flag'
181
`--disable-arith-flag'
182
     If enabled, this option caused certain instructions to set the flag
183
     (`F' bit) in the supervision register if the result were zero.
184
     The instructions affected by this were `l.add', `l.addc',
185
     `l.addi', `l.and' and `l.andi'.
186
 
187 346 jeremybenn
     If set, this caused incorrect behavior.  Whether or not flags are
188 124 jeremybenn
     set is part of the OpenRISC 1000 architectural specification.  The
189
     only flags which should set this are the "set flag" instructions:
190
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
191
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
192
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
193
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
194
 
195 112 jeremybenn
`--enable-ov-flag'
196
`--disable-ov-flag'
197 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
198
     If not, those instructions would not set the overflow flat.  The
199
     instructions affected by this were `l.add', `l.addc', `l.addi',
200
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
201
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
202
     `l.sub', `l.xor' and `l.xori'.
203 112 jeremybenn
 
204
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
205
     specification defines which flags are set by which instructions.
206
 
207
     Within the above list, the arithmetic instructions (`l.add',
208
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
209
     `l.sub'), together with `l.addic' which is missed out, set the
210
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
211
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
212
     `l.xor' and `l.xori') do not.
213
 
214
 
215 19 jeremybenn

216
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
217
 
218
1.3 Building and Installing
219
===========================
220
 
221 82 jeremybenn
Build the tool with:
222 19 jeremybenn
 
223
     make all
224 82 jeremybenn
 
225
If you have the OpenRISC tool chain and DejaGNU installed, you can
226
verify the tool as follows (otherwise omit this step):
227
 
228
     make check
229
 
230
Install the tool with:
231
 
232 19 jeremybenn
     make install
233
 
234
This will install the three variations of the Or1ksim tool,
235 442 julius
`or32-elf-sim', `or32-elf-psim' and `or32-elf-mpsim', the Or1ksim
236
library, `libsim', the header file, `or1ksim.h' and this documentation
237
in `info' format.
238 19 jeremybenn
 
239
The documentation may be created and installed in alternative formats
240
(PDF, Postscript, DVI, HTML) with for example:
241
 
242
     make pdf
243
     make install-pdf
244
 
245

246
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
247
 
248
1.4 Known Problems and Issues
249
=============================
250
 
251 346 jeremybenn
Full details of outstanding issues may be found in the `NEWS' file in
252
the main directory of the distribution.  The OpenRISC tracker may be
253
used to see the current state of these issues and to raise new problems
254
and feature requests.  It may be found at bugtracker.
255 19 jeremybenn
 
256 346 jeremybenn
The following issues are long standing and unlikely to be fixed in
257
Or1ksim in the near future.
258
 
259 19 jeremybenn
   * The Supervision Register Little Endian Enable (LEE) bit is
260 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
261 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
262
 
263
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
264 82 jeremybenn
     instances using the library.  This is clearly a problem when
265
     considering multi-core applications.  However it stems from the
266
     original design, and can only be fixed by a complete rewrite.  The
267 19 jeremybenn
     entire source code uses static global constants liberally!
268
 
269
 
270

271
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
272
 
273
2 Usage
274
*******
275
 
276
* Menu:
277
 
278
* Standalone Simulator::
279
* Profiling Utility::
280
* Memory Profiling Utility::
281 442 julius
* Trace Generation::
282 19 jeremybenn
* Simulator Library::
283 440 jeremybenn
* Ethernet TUN/TAP Interface::
284 460 jeremybenn
* l.nop Support::
285 19 jeremybenn
 
286

287
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
288
 
289
2.1 Standalone Simulator
290
========================
291
 
292
The general form the standalone command is:
293
 
294 442 julius
     or32-elf-sim [-vhiqVt] [-f FILE] [--nosrv] [--srv=[N]]
295 346 jeremybenn
                      [-m ][-d STR]
296 19 jeremybenn
                      [--enable-profile] [--enable-mprofile] [FILE]
297
 
298 82 jeremybenn
Many of the options have both a short and a long form.  For example
299
`-h' or `--help'.
300 19 jeremybenn
 
301
`-v'
302
`--version'
303
     Print out the version and copyright notice for Or1ksim and exit.
304
 
305
`-h'
306
`--help'
307
     Print out help about the command line options and what they mean.
308
 
309 346 jeremybenn
`-i'
310
`--interactive'
311
     After starting, drop into the Or1ksim interactive command shell.
312
 
313
`-q'
314
`--quiet'
315
     Do not generate any information messages, only error messages.
316
 
317
`-V'
318
`--verbose'
319
     Generate extra output messages (equivalent of specifying the
320
     "verbose" option in the simulator configuration section (see *note
321
     Simulator Behavior: Simulator Behavior.).
322
 
323 385 jeremybenn
`-t'
324
`--trace'
325 420 jeremybenn
     Dump instruction just executed and any register/memory location
326
     chaged after each instruction (one line per instruction).
327 385 jeremybenn
 
328 472 jeremybenn
`--trace-physical'
329
`--trace-virtual'
330
     When tracing instructions, show the physical address
331
     (`--trace-physical') and/or the virtual address
332
     (`--trace-virtual') of the instruction being executed.  Both flags
333
     may be specified, in which case both physical and virtual
334
     addresses are shown, physical first.
335
 
336
          Note: Either or both flags may be specified without
337
          `--trace', to indicate how addresses should be shown if
338
          subsequently enabled by a `SIGUSER1' signal or `l.nop 8'
339
          opcode (*note Trace Generation: Trace Generation.).
340
 
341 19 jeremybenn
`-f FILE'
342 385 jeremybenn
`--file=FILE'
343 19 jeremybenn
     Read configuration commands from the specified file, looking first
344
     in the current directory, and otherwise in the `$HOME/.or1k'
345 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
346
     in those two locations is used.  Failure to find the file is a
347
     fatal error.  *Note Configuration: Configuration, for detailed
348
     information on configuring Or1ksim.
349 19 jeremybenn
 
350
`--nosrv'
351 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
352
     overrides any setting specified in the configuration file.  This
353
     option may not be specified with `--srv'.  If it is, a rude
354
     message is printed and the `--nosrv' option is ignored.
355 19 jeremybenn
 
356
`--srv'
357
 
358
`--srv=N'
359 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
360
     overrides any setting specified in the configuration file.  If the
361
     parameter, N, is specified, use that as the TCP/IP port for the
362
     server, otherwise a random value from the private port range
363
     (41920-65535) will be used.  This option may not be specified with
364
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
365
     option is ignored.
366 19 jeremybenn
 
367 385 jeremybenn
`-m SIZE'
368 346 jeremybenn
`--memory=SIZE'
369
     Configure a memory block of SIZE bytes, starting at address zero.
370
     The size may be followed by `k', `K', `m', `M', `g', `G', to
371
     indicate kilobytes (2^10 bytes), megabytes (2^20 bytes) and
372
     gigabytes (2^30 bytes).
373
 
374
     This is mainly intended for use when Or1ksim is used without a
375
     configuration file, to allow just the processor and memory to be
376
     set up.  This is the equivalent of specifying a configuration
377
     memory section with `baseaddr = 0' and `size = SIZE' and all other
378
     parameters taking their default value.
379
 
380
     If a configuration file is also used, it should be sure not to
381
     specify an overlapping memory block.
382
 
383 385 jeremybenn
`-d CONFIG_STRING'
384 19 jeremybenn
`--debug-config=CONFIG_STRING'
385 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
386
     use by developers only, and is not covered further here.  See the
387 19 jeremybenn
     source code for more details.
388
 
389 346 jeremybenn
`--report-memory-errors'
390
     By default all exceptions are now handled silently.  If this
391
     option is specified, bus exceptions will be reported with a
392
     message to standard error indicating the address at which the
393
     exception occurred.
394 19 jeremybenn
 
395 346 jeremybenn
     This was the default behaviour up to Or1ksim 0.4.0.  This flag is
396
     provided for those who wish to keep that behavior.
397
 
398 19 jeremybenn
`--strict-npc'
399
     In real hardware, setting the next program counter (NPC, SPR 16),
400 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
401
     until the pipeline refills, reading the NPC will return zero.
402
     This is typically the case when debugging, since the processor is
403 19 jeremybenn
     stalled.
404
 
405
     Historically, Or1ksim has always returned the value of the NPC,
406 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
407
     is used, then Or1ksim will mirror real hardware more accurately.
408
     If the NPC is changed while the processor is stalled, subsequent
409 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
410
 
411
     This is not currently the default behavior, since tools such as
412
     GDB have been implemented assuming the historic Or1ksim behavior.
413
     However at some time in the future it will become the default.
414
 
415
`--enable-profile'
416
     Enable instruction profiling.
417
 
418
`--enable-mprofile'
419
     Enable memory profiling.
420
 
421
 
422

423
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
424
 
425
2.2 Profiling Utility
426
=====================
427
 
428 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
429
It may be invoked as a standalone command, or from the Or1ksim CLI.
430
The general form the standalone command is:
431 19 jeremybenn
 
432 442 julius
     or32-elf-profile [-vhcq] [-g=FILE]
433 19 jeremybenn
 
434 82 jeremybenn
Many of the options have both a short and a long form.  For example
435
`-h' or `--help'.
436 19 jeremybenn
 
437
`-v'
438
`--version'
439
     Print out the version and copyright notice for the Or1ksim
440
     profiling utility and exit.
441
 
442
`-h'
443
`--help'
444
     Print out help about the command line options and what they mean.
445
 
446
`-c'
447
`--cumulative'
448
     Show cumulative sum of cycles in functions
449
 
450
`-q'
451
`--quiet'
452
     Suppress messages
453
 
454
`-g=FILE'
455
`--generate=FILE'
456 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
457 19 jeremybenn
     `sim.profile' is used.
458
 
459
 
460

461 442 julius
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Trace Generation,  Prev: Profiling Utility,  Up: Usage
462 19 jeremybenn
 
463
2.3 Memory Profiling Utility
464
============================
465
 
466 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
467
be invoked as a standalone command, or from the Or1ksim CLI.  The
468 19 jeremybenn
general form the standalone command is:
469
 
470 442 julius
     or32-elf-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
471 19 jeremybenn
 
472 82 jeremybenn
Many of the options have both a short and a long form.  For example
473
`-h' or `--help'.
474 19 jeremybenn
 
475
`-v'
476
`--version'
477
     Print out the version and copyright notice for the Or1ksim memory
478
     profiling utility and exit.
479
 
480
`-h'
481
`--help'
482
     Print out help about the command line options and what they mean.
483
 
484
`-m=M'
485
`--mode=M'
486 82 jeremybenn
     Specify the mode out output.  Permitted options are
487 19 jeremybenn
 
488
    `detailed'
489
    `d'
490 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
491 19 jeremybenn
 
492
    `pretty'
493
    `p'
494
          Pretty printed output.
495
 
496
    `access'
497
    `a'
498
          Memory accesses only.
499
 
500
    `width'
501
    `w'
502
          Access width only.
503
 
504
 
505
`-g=N'
506
`--group=N'
507
     Group 2^n bits of successive addresses together.
508
 
509
`-f=FILE'
510
`--filename=FILE'
511 82 jeremybenn
     The data file to analyse.  If not specified, the default,
512 19 jeremybenn
     `sim.profile' is used.
513
 
514
`FROM'
515
`TO'
516
     FROM and TO are respectively the start and end address of the
517
     region of memory to be analysed.
518
 
519
 
520

521 442 julius
File: or1ksim.info,  Node: Trace Generation,  Next: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
522 19 jeremybenn
 
523 442 julius
2.4 Trace Generation
524
====================
525
 
526
An execution trace can be generated at run time with options passed by
527
the command line, or via the operating system's signal passing
528 472 jeremybenn
mechanism, or by `l.nop' opcodes in an application program.
529 442 julius
 
530 472 jeremybenn
The following flag can be used to create an execution dump.
531 450 jeremybenn
 
532 442 julius
`-t'
533
`--trace'
534
     Dump instruction just executed and any register/memory location
535 472 jeremybenn
     changed after each instruction (one line per instruction).  Each
536
     line starts with either "S" or "U" to indicate whether the
537
     processor was in supervisor or user mode _when the instruction
538
     completed_.  It is worth bearing in mind that tracing happens at
539
     completion of instruction execution and shows the state at that
540
     time.
541 442 julius
 
542 450 jeremybenn
Passing a signal `SIGUSR1' while the simulator is running toggles trace
543
generation. This can be done with the following command, assuming
544
Or1ksim's executable name is `or32-elf-sim':
545
 
546
     pkill -SIGUSR1 or32-elf-sim
547
 
548
This is useful in the case where trace output is desired after a
549
significant amount of simulation time, where it would be inconvenient to
550
generate trace up to that point.
551
 
552
If the `pkill' utility is not available, the `kill' utility can be used
553
if Or1ksim's process number is known. Use the following to determine
554
the process ID of the `or32-elf-sim' and then send the `SIGUSR1'
555
command to toggle execution trace generation:
556
 
557
     ps a | grep or32-elf-sim
558
     kill -SIGUSR1 _process-number_
559
 
560 472 jeremybenn
Tracing can also be enabled and disabled from within a target program
561
using the `l.nop 8' and `l.nop 9' opcodes to enable and disable tracing
562
respectively.
563
 
564
By default tracing will show the virtual address of each instruction
565
traced.  This may be controlled by two options, `--trace-physical' to
566
show the physical address and/or `--trace-virtual' to show the virtual
567
address. If neither is specified, the virtual address is shown.
568
 
569
     Note: Either or both flags may be specified without `--trace', to
570
     indicate how addresses should be shown if subsequently enabled by a
571
     `SIGUSER1' signal or `l.nop 8' opcode.
572
 
573 442 julius

574
File: or1ksim.info,  Node: Simulator Library,  Next: Ethernet TUN/TAP Interface,  Prev: Trace Generation,  Up: Usage
575
 
576
2.5 Simulator Library
577 19 jeremybenn
=====================
578
 
579
Or1ksim may be used as a static of dynamic library, `libsim.a' or
580 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
581 19 jeremybenn
should be added to the link command.
582
 
583
The header file `or1ksim.h' contains appropriate declarations of the
584 82 jeremybenn
functions exported by the Or1ksim library.  These are:
585 19 jeremybenn
 
586 346 jeremybenn
 -- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
587 432 jeremybenn
          *CLASS_PTR, int (*UPR)(void *CLASS_PTR, unsigned long int
588
          ADDR, unsigned char MASK[], unsigned char RDATA[], int
589
          DATA_LEN), int (*UPW)(void *CLASS_PTR, unsigned long int
590
          ADDR, unsigned char MASK[], unsigned char WDATA[], int
591
          DATA_LEN))
592 346 jeremybenn
     The initialization function is supplied with a vector of arguments,
593
     which are interpreted as arguments to the standalone version (see
594
     *note Standalone Simulator: Standalone Simulator.), a pointer to
595
     the calling class, CLASS_PTR (since the library may be used from
596
     C++) and two up-call functions, one for reads, UPR, and one for
597
     writes, UPW.
598 19 jeremybenn
 
599
     UPW is called for any write to an address external to the model
600 82 jeremybenn
     (determined by a `generic' section in the configuration file).
601
     UPR is called for any reads to an external address.  The CLASS_PTR
602
     is passed back with these upcalls, allowing the function to
603
     associate the call with the class which originally initialized the
604 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
605
     non-zero otherwise.  At the present time the meaning of non-zero
606
     values is not defined but this may change in the future.
607 19 jeremybenn
 
608 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
609 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
610 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
611
     address, since the upcall function must handle all generic
612
     devices, using the full address for decoding.
613 19 jeremybenn
 
614 346 jeremybenn
     Endianness is not a concern, since Or1ksim is transferring byte
615
     vectors, not multi-byte values.
616 19 jeremybenn
 
617 346 jeremybenn
     The result indicates whether the initialization was successful.
618
     The integer values are available as an `enum or1ksim', with
619
     possible values `OR1KSIM_RC_OK' and `OR1KSIM_RC_BADINIT'.
620 19 jeremybenn
 
621 346 jeremybenn
          Caution: This is a change from versions 0.3.0 and 0.4.0.  It
622
          further simplifies the interface, and makes Or1ksim more
623
          consistent with payload representation in SystemC TLM 2.0.
624
 
625 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
626
          single words (4 bytes), using masks if smaller values are
627
          required.  In this it mimcs the behavior of the WishBone bus.
628
 
629
 
630 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
631
     Run the simulator for the simulated duration specified (in
632 346 jeremybenn
     seconds).  A duration of -1 indicates `run forever'
633 19 jeremybenn
 
634 346 jeremybenn
     The result indicates how the run terminated.  The integer values
635
     are available as an `enum or1ksim', with possible values
636
     `OR1KSIM_RC_OK' (ran for the full duration), `OR1KSIM_RC_BRKPT'
637
     (terminated early due to hitting a breakpoint) and
638
     `OR1KSIM_RC_HALTED' (terminated early due to hitting `l.nop 1').
639 19 jeremybenn
 
640 346 jeremybenn
 
641 19 jeremybenn
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
642
     Change the duration of a run specified in an earlier call to
643 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
644 19 jeremybenn
     realizes it needs to change the duration of the run specified in
645
     the call to `or1ksim_run' that has been interrupted by the upcall.
646
 
647
     The time specified is the amount of time that the run must continue
648
     for (i.e the duration from _now_, not the duration from the
649
     original call to `or1ksim_run').
650
 
651
 
652
 -- `or1ksim.h': void or1ksim_set_time_point ()
653 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
654 19 jeremybenn
 
655
 
656
 -- `or1ksim.h': double or1ksim_get_time_period ()
657
     Return the simulated time (in seconds) that has elapsed since the
658
     last call to `or1ksim_set_time_point'.
659
 
660
 
661
 -- `or1ksim.h': int or1ksim_is_le ()
662
     Return 1 (logical true) if the Or1ksim simulation is
663
     little-endian, 0 otherwise.
664
 
665
 
666
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
667 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
668
     specified in the configuration file.
669 19 jeremybenn
 
670
 
671
 -- `or1ksim.h': void or1ksim_interrupt (int I)
672 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
673 432 jeremybenn
     interrupt must be cleared separately by clearing the corresponding
674
     bit in the PICSR SPR.  Until the interrupt is cleared, any further
675
     interrupts on the same line will be ignored with a warning.  A
676
     warning will be generated and the interrupt request ignored if
677
     level sensitive interrupts have been configured with the
678
     programmable interrupt controller (*note Interrupt Configuration:
679
     Interrupt Configuration.).
680 19 jeremybenn
 
681
 
682
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
683 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
684 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
685 432 jeremybenn
     `or1ksim_interrupt_clear'.  Until the interrupt is cleared, any
686
     further setting of interrupts on the same line will be ignored
687
     with a warning.  A warning will be generated, and the interrupt
688
     request ignored if edge sensitive interrupts have been configured
689
     with the programmable interrupt controller (*note Interrupt
690
     Configuration: Interrupt Configuration.).
691 19 jeremybenn
 
692
 
693
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
694
     Clear a level-triggered interrupt on interrupt line I, which was
695 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
696 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
697
     edge sensitive interrupts have been configured with the
698
     programmable interrupt controller (*note Interrupt Configuration:
699
     Interrupt Configuration.).
700
 
701
 
702 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
703 346 jeremybenn
     Drive a reset sequence through the JTAG interface.  Return the
704 104 jeremybenn
     (model) time taken for this action.  Remember that the JTAG has
705
     its own clock, which can be an order of magnitude slower than the
706
     main clock, so even a reset (5 JTAG cycles) could take 50
707
     processor clock cycles to complete.
708
 
709
 
710 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned char *JREG, int
711
          NUM_BITS)
712 104 jeremybenn
     Shift the supplied register through the JTAG instruction register.
713 346 jeremybenn
     Return the (model) time taken for this action.  The register is
714 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
715
     least significant byte.  If the total number of bits is not an
716
     exact number of bytes, then the odd bits are found in the least
717
     significant end of the highest numbered byte.
718
 
719
     For example a 12-bit register would have bits 0-7 in byte 0 and
720
     bits 11-8 in the least significant 4 bits of byte 1.
721
 
722
 
723 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned char *JREG, int
724
          NUM_BITS)
725 104 jeremybenn
     Shift the supplied register through the JTAG data register.
726 346 jeremybenn
     Return the (model) time taken for this action.  The register is
727 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
728
     least significant byte.  If the total number of bits is not an
729
     exact number of bytes, then the odd bits are found in the least
730
     significant end of the highest numbered byte.
731
 
732
     For example a 12-bit register would have bits 0-7 in byte 0 and
733
     bits 11-8 in the least significant 4 bits of byte 1.
734
 
735
 
736 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_mem (unsigned long int ADDR, unsigned
737
          char *BUF, int LEN)
738 346 jeremybenn
     Read LEN bytes from ADDR, placing the result in BUF.  Return LEN
739
     on success and 0 on failure.
740
 
741
          Note: This function was added in Or1ksim 0.5.0.
742
 
743
 
744 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_mem (unsigned long int ADDR, const
745
          unsigned char *BUF, int LEN)
746 346 jeremybenn
     Write LEN bytes to ADDR, taking the data from BUF.  Return LEN on
747
     success and 0 on failure.
748
 
749
          Note: This function was added in Or1ksim 0.5.0.
750
 
751
 
752 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned long int
753
          *SPRVAL_PTR)
754 346 jeremybenn
     Read the SPR specified by SPRNUM, placing the result in
755
     SPRVAL_PTR.  Return non-zero on success and 0 on failure.
756
 
757
          Note: This function was added in Or1ksim 0.5.0.
758
 
759
 
760 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned long int
761
          SPRVA)
762 346 jeremybenn
     Write SPRVAL to the SPR specified by SPRNUM.  Return non-zero on
763
     success and 0 on failure.
764
 
765
          Note: This function was added in Or1ksim 0.5.0.
766
 
767
 
768 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned long int
769
          *REGVAL_PTR)
770 346 jeremybenn
     Read the general purpose register specified by REGNUM, placing the
771
     result in REGVAL_PTR.  Return non-zero on success and 0 on failure.
772
 
773
          Note: This function was added in Or1ksim 0.5.0.
774
 
775
 
776 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned long int
777
          REGVA)
778 346 jeremybenn
     Write REGVAL to the general purpose register specified by REGNUM.
779
     Return non-zero on success and 0 on failure.
780
 
781
          Note: This function was added in Or1ksim 0.5.0.
782
 
783
 
784 432 jeremybenn
 -- `or1ksim.h': void or1ksim_set_stall_state (int STATE)
785 346 jeremybenn
     Set the processor's state according to STATE (1 = stalled, 0 = not
786
     stalled).
787
 
788
          Note: This function was added in Or1ksim 0.5.0.
789
 
790
 
791 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
792
installation directory (as specified with the `--prefix' option to the
793
`configure' script).
794
 
795
For example if the main installation directory is `/opt/or1ksim', the
796 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
797 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
798
(`libsim.so').
799
 
800
To link against the library add the `-lsim' flag when linking and do
801
one of the following:
802
 
803
   * Add the library directory to the `LD_LIBRARY_PATH' environment
804 82 jeremybenn
     variable during execution.  For example:
805 19 jeremybenn
 
806
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
807
 
808
   * Add the library directory to the `LD_RUN_PATH' environment
809 82 jeremybenn
     variable during linking.  For example:
810 19 jeremybenn
 
811
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
812
 
813
   * Use the linker `--rpath' option and specify the library directory
814 82 jeremybenn
     when linking your program.  For example
815 19 jeremybenn
 
816 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
817 19 jeremybenn
 
818
   * Add the library directory to `/etc/ld.so.conf'
819
 
820
 
821

822 460 jeremybenn
File: or1ksim.info,  Node: Ethernet TUN/TAP Interface,  Next: l.nop Support,  Prev: Simulator Library,  Up: Usage
823 440 jeremybenn
 
824 442 julius
2.6 Ethernet TUN/TAP Interface
825 440 jeremybenn
==============================
826
 
827
When an Ethernet peripheral is configured (*note Ethernet
828
Configuration: Ethernet Configuration.), one option is to tunnel
829
traffic through a TUN/TAP interface.  The low level TAP interface is
830
used to tunnel raw Ethernet datagrams.
831
 
832
The TAP interface can then be connected to a physical Ethernet through a
833
bridge, allowing the Or1ksim model to connect to a physical network.
834
This is particularly when Or1ksim is running the OpenRISC Linux kernel
835
image.
836
 
837
This section explains how to set up a bridge for use by Or1ksim. It does
838
require superuser access to the host machine (or at least the relevant
839
network capabilities). A system administrator can modify these
840
guidelines so they are executed on reboot if appropriate.
841
 
842
* Menu:
843
 
844
* Setting Up a Persistent TAP device::
845
* Establishing a Bridge::
846
* Opening the Firewall::
847
* Disabling Ethernet Filtering::
848
* Networking from OpenRISC Linux and BusyBox::
849
* Tearing Down a Bridge::
850
 
851

852
File: or1ksim.info,  Node: Setting Up a Persistent TAP device,  Next: Establishing a Bridge,  Up: Ethernet TUN/TAP Interface
853
 
854 442 julius
2.6.1 Setting Up a Persistent TAP device
855 440 jeremybenn
----------------------------------------
856
 
857
TUN/TAP devices can be created dynamically, but this requires superuser
858
privileges (or at least `CAP_NET_ADMIN' capability).  The solution is
859
to create a persistent TAP device.  This can be done using either
860
`openvpn' or `tunctl'.  In either case the package must be installed on
861
the host system.  Using `openvpn', the following would set up a TAP
862
interface for a specified user and group.
863
 
864
     openvpn --mktun --dev tap_n_ --user _username_ --group _groupname_
865
 
866

867
File: or1ksim.info,  Node: Establishing a Bridge,  Next: Opening the Firewall,  Prev: Setting Up a Persistent TAP device,  Up: Ethernet TUN/TAP Interface
868
 
869 442 julius
2.6.2 Establishing a Bridge
870 440 jeremybenn
---------------------------
871
 
872
A bridge is a "virtual" local area network interfaces, subsuming two or
873
more existing network interfaces.  In this case we will bridge the
874
physical Ethernet interface of the host with the TAP interface that
875
will be used by Or1ksim.
876
 
877
The Ethernet and TAP must lose their own individual IP addresses (by
878
setting them to 0.0.0.0) and are replaced by the IP address of the
879
bridge interface. To do this we use the `bridge-utils' package, which
880
must be installed on the host system. These commands are require
881
superuser privileges or `CAP_NET_ADMIN' capability. To create a new
882
interface `br_n_' the following commands are appropriate.
883
 
884
     brctl addbr br_n_
885
     brctl addif br_n_ eth_x_
886
     brctl addif br_n_ tap_y_
887
 
888
     ifconfig eth_x_ 0.0.0.0 promisc up
889
     ifconfig tap_y_ 0.0.0.0 promisc up
890
 
891
     dhclient br_n_
892
 
893
The last command instructs the bridge to obtain its IP address, netmask,
894
broadcast address, gateway and nameserver information using DHCP.  In a
895
network without DHCP it should be replaced by `ifconfig' to set a
896
static IP address, netmask and broadcast address.
897
 
898
     Note: This will leave a spare dhclient process running in the
899
     background, which should be killed for tidiness. There is a
900
     technique to avoid this using `omshell', but that is beyond the
901
     scope of this guide.
902
 
903
     Note: It is not clear to the author why the existing interfaces
904
     need to be brought up in promiscuous mode, but it seems to cure
905
     various problems.
906
 
907

908
File: or1ksim.info,  Node: Opening the Firewall,  Next: Disabling Ethernet Filtering,  Prev: Establishing a Bridge,  Up: Ethernet TUN/TAP Interface
909
 
910 442 julius
2.6.3 Opening the Firewall
911 440 jeremybenn
--------------------------
912
 
913
Firewall rules should be added to ensure traffic flows freely through
914
the TAP and bridge interfaces. As superuser the following commands are
915
appropriate.
916
 
917
     iptables -A INPUT -i tap_y_ -j ACCEPT
918
     iptables -A INPUT -i br_n_ -j ACCEPT
919
     iptables -A FORWARD -i br_n_ -j ACCEPT
920
 
921

922
File: or1ksim.info,  Node: Disabling Ethernet Filtering,  Next: Networking from OpenRISC Linux and BusyBox,  Prev: Opening the Firewall,  Up: Ethernet TUN/TAP Interface
923
 
924 442 julius
2.6.4 Disabling Ethernet Filtering
925 440 jeremybenn
----------------------------------
926
 
927
Some systems may have ethernet filtering enabled (`ebtables',
928
`bridge-nf', `arptables') which will stop traffic flowing through the
929
bridge.
930
 
931
The easiest way to disable this is by writing zero to all `bridge-nf-*'
932
entries in `/proc/sys/net/bridge'. As superuser the following commands
933
will achieve this.
934
 
935
     cd /proc/sys/net/bridge
936
     for f in bridge-nf-*; do echo 0 > $f; done
937
 
938

939
File: or1ksim.info,  Node: Networking from OpenRISC Linux and BusyBox,  Next: Tearing Down a Bridge,  Prev: Disabling Ethernet Filtering,  Up: Ethernet TUN/TAP Interface
940
 
941 442 julius
2.6.5 Networking from OpenRISC Linux and BusyBox
942 440 jeremybenn
------------------------------------------------
943
 
944
The main use of this style of Ethernet interface to Or1ksim is when
945
running the OpenRISC Linux kernel with BusyBox. The following commands
946
in the BusyBox console window will configure the Ethernet interface
947
(assumed to be `eth0') and bring it up with a DHCP assigned address.
948
 
949
     ifconfig eth0
950
     ifup eth0
951
 
952
At this stage interface to IP addresses will work correctly.
953
 
954
For DNS to work the BusyBox system needs to know where to find a
955
nameserver.  Under BusyBox, `udhcp' does not configure
956
`/etc/resolv.conf' automatically.
957
 
958
The solution is to duplicate the nameserver entry from the
959
`/etc/resolv.conf' file of the host on the BusyBox system. A typical
960
file might be as follows:
961
 
962
     `nameserver 192.168.0.1'
963
 
964
It is convenient to make this permanent within the Linux initramfs. Add
965
the file as `arch/openrisc/support/initramfs/etc/resolv.conf' within
966
the Linux source tree and rebuild `vmlinux'. It will then be present
967
automatically.
968
 
969
One of the most useful functions that is possible is to mount the host
970
file system through NFS. For example, from the BusyBox console:
971
 
972
     mount -t nfs -o nolock 192.168.0.60:/home /mnt
973
 
974
Another useful technique is to telnet into the BusyBox system from the
975
host. This is particularly valuable when a console process locks up,
976
since the `xterm' console will not recognize ctrl-C. Instead the rogue
977
process can be killed from a telnet connection.
978
 
979

980
File: or1ksim.info,  Node: Tearing Down a Bridge,  Prev: Networking from OpenRISC Linux and BusyBox,  Up: Ethernet TUN/TAP Interface
981
 
982 442 julius
2.6.6 Tearing Down a Bridge
983 440 jeremybenn
---------------------------
984
 
985
There is little reason why a bridge should ever need to be torn down,
986
but if desired, the following commands will achieve the effect.
987
 
988
     ifconfig br_n_ down
989
     brctl delbr br_n_
990
 
991
     dhclient eth_x_
992
 
993
As before this will leave a spare `dhclient' process in the background
994
which should be killed.
995
 
996
If desired the TAP interface can be deleted using
997
 
998
     openvpn --rmtun -dev tap_y_
999
 
1000
     Caution: The TAP interface should not be in use when running this
1001
     command. For example any OpenRISC Linux/BusyBox sessions should be
1002
     closed first.
1003
 
1004

1005 460 jeremybenn
File: or1ksim.info,  Node: l.nop Support,  Prev: Ethernet TUN/TAP Interface,  Up: Usage
1006
 
1007
2.7 l.nop Opcode Support
1008
========================
1009
 
1010
The OpenRISC `l.nop' opcode can take a parameter.  This has no effect
1011
on the semantics of the opcode, but can be used to trigger side effect
1012
behavior in a simulator.  Within Or1ksim, the following parameters are
1013
supported.
1014
 
1015
`l.nop 0'
1016
     The equivalent to `l.nop' with no parameter. Has no side effects.
1017
 
1018
`l.nop 1'
1019
     Execution of Or1ksim is terminated. This is used to implement the
1020
     library `exit' functions.
1021
 
1022
`l.nop 2'
1023
     Report the value in `r3' on the console as a 32-bit hex value.
1024
 
1025
`l.nop 3'
1026
     In earlier versions of Or1ksim this treated `r3' as a pointer to a
1027 508 jeremybenn
     `printf' style format string, and registers `r4' through `r8' as
1028 460 jeremybenn
     parameters for that format string.
1029
 
1030
     This opcode is no longer supported, and has no effect if used.
1031
 
1032
`l.nop 4'
1033
     The value in `r3' is printed to standard output as an ASCII
1034
     character.  All library output routines are implemented using this
1035
     opcode.
1036
 
1037
`l.nop 5'
1038
     The statistics counters are reset.
1039
 
1040
`l.nop 6'
1041
     The number of clock ticks since start of execution (a 64-bit
1042
     value) is returned in `r11' (low 32 bits) and `r12' (high 32 bits).
1043
 
1044
`l.nop 7'
1045
     The number of picoseconds per clock cycle is returned in `r11'.
1046
     This is used with `l.nop 6' to implement timing functions.
1047
 
1048
`l.nop 8'
1049
     Instruction tracing is turned on.
1050
 
1051
`l.nop 9'
1052
     Instruction tracing is turned off.
1053
 
1054 483 jeremybenn
`l.nop 10'
1055
     A 32-bit random number is returned in `r11'.
1056 460 jeremybenn
 
1057 483 jeremybenn
     The random numbers are generated using `random', which in turn is
1058
     seeded through `srandom' using the host `/dev/urandom' if
1059
     available, or else the process ID of the Or1ksim instance.
1060
 
1061
     This opcode is particularly useful for situations where a target
1062
     program running on Or1ksim needs to obtain genuine system entropy
1063
     to generate random numbers.
1064
 
1065
`l.nop 11'
1066
     Return a non-zero value in `r11'.
1067
 
1068
     This opcode can be used to detect if a target is running under
1069
     Or1ksim.  Set `r11' to zero, issue this opcode, and look to see if
1070
     `r11' is non-zero.
1071
 
1072
 
1073 460 jeremybenn

1074 19 jeremybenn
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
1075
 
1076
3 Configuration
1077
***************
1078
 
1079 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
1080 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
1081 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
1082
the default `sim.cfg' is used.  The file is looked for first in the
1083 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
1084 19 jeremybenn
 
1085
* Menu:
1086
 
1087
* Configuration File Format::
1088
* Simulator Configuration::
1089
* Core OpenRISC Configuration::
1090
* Peripheral Configuration::
1091
 
1092

1093
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
1094
 
1095
3.1 Configuration File Format
1096
=============================
1097
 
1098 346 jeremybenn
The configuration file is a plain text file.  A reference example,
1099
`sim.cfg', is included in the top level directory of the distribution.
1100 19 jeremybenn
 
1101
* Menu:
1102
 
1103
* Configuration File Preprocessing::
1104
* Configuration File Syntax::
1105
 
1106

1107
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
1108
 
1109
3.1.1 Configuration File Preprocessing
1110
--------------------------------------
1111
 
1112 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
1113 19 jeremybenn
`/*' and `*/').
1114
 
1115

1116
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
1117
 
1118
3.1.2 Configuration File Syntax
1119
-------------------------------
1120
 
1121
The configuration file is divided into a series of sections, with the
1122
general form:
1123
 
1124
     section SECTION_NAME
1125
 
1126
       ...
1127
 
1128
     end
1129
 
1130
Sections may also have sub-sections within them (currently only the
1131
ATA/ATAPI disc interface uses this).
1132
 
1133
Within a section, or sub-section are a series of parameter assignments,
1134
one per line, withe the general form
1135
 
1136
       PARAMETER = VALUE
1137
 
1138
Depending on the parameter, the value may be a named value (an
1139
enumeration), an integer (specified in any format acceptable in C) or a
1140 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
1141
mean "true" or "on" and the value "0" to mean "false" or "off".  An
1142 19 jeremybenn
example from a memory section shows each of these
1143
 
1144
     section memory
1145
       type    = random
1146
       pattern = 0x00
1147
       name    = "FLASH"
1148
       ...
1149
     end
1150
 
1151
Many parameters are optional and take reasonable default values if not
1152 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
1153 19 jeremybenn
parameter in `section memory') _must_ be specified.
1154
 
1155
Subsections are introduced by a keyword, with a parameter value (no `='
1156 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
1157 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
1158
 
1159
     section ata
1160
       ...
1161
       device 0
1162
         type    = 1
1163
         file = "FILENAME"
1164
         ...
1165
       enddevice
1166
       ...
1167
     end
1168
 
1169
Some sections (for example `section sim') should appear only once.
1170
Others (for example `section memory' may appear multiple times.
1171
 
1172
Sections may be omitted, _unless they contain parameters which are
1173 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
1174 19 jeremybenn
is optional (for example whether it has a UART), then that
1175 82 jeremybenn
functionality will not be provided.  If the section describes a part of
1176 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
1177
parameters of that section will take their default values.
1178
 
1179
All optional parts of the functionality are always described by
1180
sections including a `enabled' parameter, which can be set to 0 to
1181
ensure that functionality is explicitly omitted.
1182
 
1183
Even if a section is disabled, all its parameters will be read and
1184 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
1185
the Or1ksim command line (*note Interactive Command Line: Interactive
1186 19 jeremybenn
Command Line.).
1187
 
1188
     Tip: It generally clearer to have sections describing _all_
1189
     components, with omitted functionality explicitly indicated by
1190
     setting the `enabled' parameter to 0
1191
 
1192
The following sections describe the various configuration sections and
1193
the parameters which may be set in each.
1194
 
1195

1196
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
1197
 
1198
3.2 Simulator Configuration
1199
===========================
1200
 
1201
* Menu:
1202
 
1203
* Simulator Behavior::
1204
* Verification API Configuration::
1205
* CUC Configuration::
1206
 
1207

1208
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
1209
 
1210
3.2.1 Simulator Behavior
1211
------------------------
1212
 
1213 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
1214
appear only once.  The following parameters may be specified.
1215 19 jeremybenn
 
1216
`verbose = 0|1'
1217 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
1218 19 jeremybenn
 
1219
`debug = 0-9'
1220 82 jeremybenn
 
1221
     higher the value the greater the number of messages.  Default 0.
1222
     Negative values will be treated as 0 (with a warning).  Values
1223
     that are too large will be treated as 9 (with a warning).
1224 19 jeremybenn
 
1225
`profile = 0|1'
1226
     If 1 (true) generate a profiling file using the file specified in
1227 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
1228 19 jeremybenn
 
1229
`prof_file = ``FILENAME'''
1230 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
1231
     Default `sim.profile'.  For backwards compatibility, the
1232
     alternative name `prof_fn' is supported for this parameter, but
1233 346 jeremybenn
     deprecated.  Default `sim.profile'.
1234 19 jeremybenn
 
1235
`mprofile = 0|1'
1236
     If 1 (true) generate a memory profiling file using the file
1237
     specified in the `mprof_file' parameter or otherwise
1238 82 jeremybenn
     `sim.mprofile'.  Default 0.
1239 19 jeremybenn
 
1240 346 jeremybenn
`mprof_file = ``FILENAME'''
1241 19 jeremybenn
     Specifies the file to be used with the `mprofile' parameter.
1242 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
1243 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
1244 346 jeremybenn
     deprecated.  Default `sim.mprofile'.
1245 19 jeremybenn
 
1246
`history = 0|1'
1247 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
1248 19 jeremybenn
 
1249
          Note: Setting this parameter seriously degrades performance.
1250
 
1251
          Note: If this execution flow tracking is enabled, then
1252
          `dependstats' must be enabled in the CPU configuration
1253
          section (*note CPU Configuration: CPU Configuration.).
1254
 
1255
`exe_log = 0|1'
1256 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
1257
     file specified in parameter `exe_log_file'.  Default 0.
1258 19 jeremybenn
 
1259
          Note: Setting this parameter seriously degrades performance.
1260
 
1261
`exe_log_type = default|hardware|simple|software'
1262
     Type of execution log to produce.
1263
 
1264
    `default'
1265 82 jeremybenn
          Produce default output for the execution log.  In the current
1266 19 jeremybenn
          implementation this is the equivalent of `hardware'.
1267
 
1268
    `hardware'
1269
          After each instruction execution, log the number of
1270
          instructions executed so far, the next instruction to execute
1271
          (in hex), the general purpose registers (GPRs), status
1272
          register, exception program counter, exception, effective
1273
          address register and exception status register.
1274
 
1275
    `simple'
1276
          After each instruction execution, log the number of
1277
          instructions executed so far and the next instruction to
1278
          execute, symbolically disassembled.
1279
 
1280
    `software'
1281
          After each instruction execution, log the number of
1282
          instructions executed so far and the next instruction to
1283 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
1284 19 jeremybenn
          each operand to the instruction.
1285
 
1286
 
1287 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
1288 19 jeremybenn
     insensitive) will be treated as the default with a warning.
1289
 
1290
          Note: Execution logs can be _very_ big.
1291
 
1292
`exe_log_start = VALUE'
1293 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
1294 19 jeremybenn
 
1295
`exe_log_end = VALUE'
1296 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
1297
     once started logging will continue until the simulator exits).
1298 19 jeremybenn
 
1299
`exe_log_marker = VALUE'
1300
     Specifies the number of instructions between printing horizontal
1301 82 jeremybenn
     markers.  Default is to produce no markers.
1302 19 jeremybenn
 
1303
`exe_log_file = FILENAME'
1304
     Filename for the execution log filename if `exe_log' is enabled.
1305 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
1306 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
1307
     deprecated.
1308
 
1309 202 julius
`exe_bin_insn_log = 0|1'
1310 346 jeremybenn
     Enable logging of executed instructions to a file in binary format.
1311
     This is helpful for off-line dynamic execution analysis.
1312 202 julius
 
1313 346 jeremybenn
          Note: Execution logs can be _very_ big.  For example, while
1314 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
1315
          size was generated.
1316 202 julius
 
1317
`exe_bin_insn_log_file = FILENAME'
1318
     Filename for the binary execution log filename if
1319
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
1320
 
1321 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
1322 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
1323
     specified, `ps' is assumed.  Default 4000ps (250MHz).
1324 19 jeremybenn
 
1325
 
1326

1327
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
1328
 
1329
3.2.2 Verification API (VAPI) Configuration
1330
-------------------------------------------
1331
 
1332
The Verification API (VAPI) provides a TCP/IP interface to allow
1333 82 jeremybenn
components of the simulation to be controlled externally.  *Note
1334 19 jeremybenn
Verification API: Verification API, for more details.
1335
 
1336 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
1337
section may appear at most once.  The following parameters may be
1338 19 jeremybenn
specified.
1339
 
1340
`enabled = 0|1'
1341
     If 1 (true), verification API is enabled and its server started.
1342
     If 0 (the default), it is disabled.
1343
 
1344
`server_port = VALUE'
1345
     When VAPI is enabled, communication will be via TCP/IP on the port
1346 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
1347 19 jeremybenn
     The default value is 50000.
1348
 
1349 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
1350 19 jeremybenn
          practice suggests users should adopt port values in the
1351 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
1352 19 jeremybenn
 
1353
`log_enabled = 0|1'
1354
     If 1 (true), all VAPI requests and sent commands will be logged.
1355 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
1356 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
1357
 
1358
          Caution: This can generate a substantial amount of file I/O
1359
          and seriously degrade simulator performance.
1360
 
1361
`hide_device_id = 0|1'
1362 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
1363
     device ID.  This feature (when set to 1) is provided for backwards
1364 19 jeremybenn
     compatibility with an old version of VAPI.
1365
 
1366
`vapi_log_file = "FILENAME"'
1367
     Use `filename' as the file for logged data is logging is enabled
1368 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
1369 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
1370
     supported for this parameter, but deprecated.
1371
 
1372
 
1373

1374
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
1375
 
1376
3.2.3 Custom Unit Compiler (CUC) Configuration
1377
----------------------------------------------
1378
 
1379
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1380 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1381
beyond the initial prototype phase.  The configuration parameters are
1382 19 jeremybenn
described here for the record.
1383
 
1384 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1385
appear at most once.  The following parameters may be specified.
1386 19 jeremybenn
 
1387
`memory_order = none|weak|strong|exact'
1388
     This parameter specifies the memory ordering required:
1389
 
1390
    `memory_order=none'
1391
          Different memory ordering, even if there are dependencies.
1392
          Bursts can be made, width can change.
1393
 
1394 346 jeremybenn
    `memory_order=weak'
1395 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1396 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1397
          change.
1398
 
1399 346 jeremybenn
    `memory_order=strong'
1400 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1401 19 jeremybenn
 
1402 346 jeremybenn
    `memory_order=exact'
1403 19 jeremybenn
          Exactly the same memory ordering and widths.
1404
 
1405
 
1406 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1407 19 jeremybenn
     orderings are ignored with a warning.
1408
 
1409
`calling_convention = 0|1'
1410 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1411 19 jeremybenn
     (the default), they may use other convenitions.
1412
 
1413
`enable_bursts = 0 | 1'
1414 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1415 19 jeremybenn
     not detected.
1416
 
1417
`no_multicycle = 0 | 1'
1418 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1419
     (the default), multicycle logic paths will be generated.
1420 19 jeremybenn
 
1421
`timings_file = "FILENAME"'
1422 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1423
     default value is `"virtex.tim"'.  For backwards compatibility, the
1424 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1425
     deprecated.
1426
 
1427
 
1428

1429
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1430
 
1431
3.3 Configuring the OpenRISC Architectural Components
1432
=====================================================
1433
 
1434
* Menu:
1435
 
1436
* CPU Configuration::
1437
* Memory Configuration::
1438
* Memory Management Configuration::
1439
* Cache Configuration::
1440
* Interrupt Configuration::
1441
* Power Management Configuration::
1442
* Branch Prediction Configuration::
1443
* Debug Interface Configuration::
1444 556 julius
* Performance Counters Configuration::
1445 19 jeremybenn
 
1446

1447
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1448
 
1449
3.3.1 CPU Configuration
1450
-----------------------
1451
 
1452 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1453
appear only once.  At present Or1ksim does not model multi-CPU systems.
1454 19 jeremybenn
The following parameters may be specified.
1455
 
1456
`ver = VALUE'
1457
 
1458
`cfg = VALUE'
1459
 
1460
`rev = VALUE'
1461
     The values are used to form the corresponding fields in the `VR'
1462 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1463 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1464
     and `cfg', 6 bits for `rev').
1465
 
1466
`upr = VALUE'
1467
     Used as the value of the Unit Present Register (UPR) Special
1468 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1469 19 jeremybenn
     i.e.
1470
        * UPR present (0x00000001)
1471
 
1472
        * Data cache present (0x00000002)
1473
 
1474
        * Instruction cache present (0x00000004)
1475
 
1476 556 julius
        * Data MMU present (0x00000008)
1477 19 jeremybenn
 
1478
        * Instruction MMU present (0x00000010)
1479
 
1480
        * Debug unit present (0x00000040)
1481
 
1482
        * Power management unit present (0x00000100)
1483
 
1484
        * Programmable interrupt controller present (0x00000200)
1485
 
1486
        * Tick timer present (0x00000400)
1487
 
1488
     However, with the exection of the UPR present (0x00000001) and tick
1489
     timer present, the various fields will be modified with the values
1490
     specified in their corresponding configuration sections.
1491
 
1492
`cfgr = VALUE'
1493
     Sets the CPU configuration register (Special Purpose Register 2) to
1494 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1495
     instruction set.  Attempts to set any other value are accepted, but
1496 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1497
 
1498
`sr = VALUE'
1499
     Sets the supervision register Special Purpose Register (SPR 0x11)
1500 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1501 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1502
 
1503 98 jeremybenn
          Note: This is particularly useful when an image is held in
1504
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1505
          so that interrupt vectors are basedf at 0xf0000000, rather
1506
          than 0x0.
1507
 
1508 19 jeremybenn
`superscalar = 0|1'
1509 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1510 19 jeremybenn
     0.
1511
 
1512
     In the current simulator, the only functional effect of superscalar
1513
     mode is to affect the calculation of the number of cycles taken to
1514
     execute an instruction.
1515
 
1516
          Caution: The code for this does not appear to be complete or
1517
          well tested, so users are advised not to use this option.
1518
 
1519
`hazards = 0|1'
1520 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1521
     value is 0.
1522 19 jeremybenn
 
1523
     In the current simulator, the only functional effect is to cause
1524
     logging of hazard waiting information if the CPU is superscalar.
1525
     However nowhere in the simulator is this data actually computed,
1526
     so the net result is probably to have no effect.
1527
 
1528
     if harzards are tracked, current hazards can be displayed using the
1529
     simulator's `r' command.
1530
 
1531
          Caution: The code for this does not appear to be complete or
1532
          well tested, so users are advised not to use this option.
1533
 
1534
`dependstats = 0|1'
1535 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1536
     value 0.
1537 19 jeremybenn
 
1538
     If these values are calculated, the depencies can be displayed
1539
     using the simulator's `stat' command.
1540
 
1541
          Note: This field must be enabled, if execution execution flow
1542
          tracking (field `history') has been requested in the simulator
1543
          configuration section (*note Simulator Behavior: Simulator
1544
          Behavior.).
1545
 
1546
`sbuf_len = VALUE'
1547
     The length of the store buffer is set to VALUE, which must be no
1548 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1549
     warning.  Negative values will be treated as 0 with a warning.
1550
     Use 0 to disable the store buffer.
1551 19 jeremybenn
 
1552
     When the store buffer is active, stores are accumulated and
1553
     committed when I/O is idle.
1554
 
1555 100 julius
`hardfloat = 0|1'
1556 346 jeremybenn
     If 1, hardfloat instructions are enabled.  Default value 0.
1557 19 jeremybenn
 
1558 104 jeremybenn
 
1559 19 jeremybenn

1560
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1561
 
1562
3.3.2 Memory Configuration
1563
--------------------------
1564
 
1565 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1566 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1567 19 jeremybenn
 
1568 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1569 385 jeremybenn
     controller.  If a memory controller is enabled, then appropriate
1570
     initalization code must be provided.  The section describing
1571
     memory controller configuration describes the steps necessary for
1572
     using smaller or larger memory sections (*note Memory Controller
1573
     Configuration: Memory Controller Configuration.).
1574 98 jeremybenn
 
1575 385 jeremybenn
     The "uClibc" startup code initalizes a memory controller, assumed
1576
     to be mapped at 0x93000000.  If a memory controller is _not_
1577
     enabled, then the standard C library code will generate memory
1578
     access errors.  The solution is to declare an additional writable
1579
     memory block, mimicing the memory controller's register bank as
1580
     follows.
1581 98 jeremybenn
 
1582
          section memory
1583
            pattern = 0x00
1584
            type = unknown
1585
            name = "MC shadow"
1586
            baseaddr = 0x93000000
1587
            size     = 0x00000080
1588
            delayr = 2
1589
            delayw = 4
1590
          end
1591
 
1592
 
1593
The following parameters may be specified.
1594
 
1595 418 julius
`type=random|pattern|unknown|zero|exitnops'
1596 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1597 19 jeremybenn
     default value is `unknown'.
1598
 
1599
    `random'
1600 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1601 19 jeremybenn
          random generator may be set using the `random_seed' field in
1602
          this section (see below), thus ensuring the same "random"
1603
          values are used each time.
1604
 
1605
    `pattern'
1606
          Set the memory values to be a pattern value, which is set
1607
          using the `pattern' field in this section (see below).
1608
 
1609
    `unknown'
1610 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1611 240 julius
          This option will yield faster initialization of the
1612 346 jeremybenn
          simulator.  This is the default.
1613 19 jeremybenn
 
1614
    `zero'
1615 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1616 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1617
          such.
1618
 
1619 420 jeremybenn
               Note: As a consequence, if the `pattern' field is
1620
               _subsequently_ specified in this section, the value in
1621
               that field will be used instead of zero to initialize
1622
               the memory.
1623
 
1624 418 julius
    `exitnops'
1625
          Set the memory values to be an instruction used to signal end
1626
          of simulation. This is useful for causing immediate end of
1627
          simulation when PC corruption occurs.
1628
 
1629 19 jeremybenn
 
1630
`random_seed = VALUE'
1631 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1632 19 jeremybenn
     has any effect for memory type `random'.
1633
 
1634
     The default value is -1, which means the seed will be set from a
1635
     call to the `time' function, thus ensuring different random values
1636 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1637 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1638
     values used in any particular run.
1639
 
1640
`pattern = VALUE'
1641 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1642
     default value is 0.  This only has any effect for memory type
1643
     `pattern'.  The least significant 8 bits of this value is used to
1644
     initialize each byte.  More than 8 bits can be specified, but will
1645 19 jeremybenn
     ignored with a warning.
1646
 
1647
          Tip: The default value, is equivalent to setting the memory
1648 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1649 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1650
          and not specifying a value for `pattern'.
1651
 
1652
`baseaddr = VALUE'
1653 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1654 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1655
     The default value is 0.
1656
 
1657
`size = VALUE'
1658 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1659
     be a multiple of 4 (i.e.  word aligned).  The default value is
1660
     1024.
1661 19 jeremybenn
 
1662
          Note: When allocating memory, the simulator will allocate the
1663
          nearest 2^n bytes greater than or equal to VALUE, and will not
1664
          notice memory misses in any part of the memory between VALUE
1665
          and the amount allocated.
1666
 
1667
          As a consequence users are strongly recommended to specify
1668 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1669 19 jeremybenn
          amount of memory is required, it should be specified as
1670
          separate, contiguous blocks, each of which is a power of 2 in
1671
          size.
1672
 
1673
`name = "TEXT"'
1674 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1675
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1676 19 jeremybenn
     `"anonymous memory block"'.
1677
 
1678
          Note: It is not clear that this information is currently ever
1679 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1680 19 jeremybenn
          command of the simulator ignores it.
1681
 
1682
`ce = VALUE'
1683 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1684 19 jeremybenn
     instance should have a unique chip enable index, which should be
1685 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1686 19 jeremybenn
     controller when identifying different memory instances.
1687
 
1688 346 jeremybenn
     There is no requirement to set `ce' if a memory controller is not
1689
     enabled.  The default value is -1 (invalid).
1690 19 jeremybenn
 
1691
`mc = VALUE'
1692 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1693 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1694
     for a memory controller (*note Memory Controller Configuration:
1695
     Memory Controller Configuration.).
1696
 
1697 346 jeremybenn
     There is no requirement to set `mc' if a memory controller is not
1698
     enabled.  Default value is 0, which is also the default value of a
1699 98 jeremybenn
     memory controller `index' field.  This is suitable therefore for
1700
     designs with just one memory controller.
1701 19 jeremybenn
 
1702
`delayr = VALUE'
1703 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1704
     memory does not support reading.  Default value 1.  The simulator
1705 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1706
     count when reading from main memory.
1707
 
1708
`delayw = VALUE'
1709 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1710
     memory does not support writing.  Default value 1.  The simulator
1711 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1712
     count when writing to main memory.
1713
 
1714
`log = "FILE"'
1715
     If specified, `file' names a file for all memory accesses to be
1716 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1717 19 jeremybenn
     that the memory is not logged.
1718
 
1719
 
1720

1721
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1722
 
1723
3.3.3 Memory Management Configuration
1724
-------------------------------------
1725
 
1726
Memory Management Unit (MMU) configuration is described in `section
1727
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1728 82 jeremybenn
Each section should appear at most once.  The following parameters may
1729 19 jeremybenn
be specified.
1730
 
1731
`enabled = 0|1'
1732
     If 1 (true), the data or instruction (as appropriate) MMU is
1733 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1734 19 jeremybenn
 
1735
`nsets = VALUE'
1736
     Sets the number of data or instruction (as appropriate) TLB sets to
1737 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1738
     which do not fit these criteria are ignored with a warning.  The
1739 19 jeremybenn
     default value is 1.
1740
 
1741
`nways = VALUE'
1742
     Sets the number of data or instruction (as appropriate) TLB ways to
1743 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1744
     this range are ignored with a warning.  The default value is 1.
1745 19 jeremybenn
 
1746
`pagesize = VALUE'
1747
     The data or instruction (as appropriate) MMU page size is set to
1748 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1749
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1750 19 jeremybenn
 
1751
`entrysize = VALUE'
1752
     The data or instruction (as appropriate) MMU entry size is set to
1753 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1754
     of 2 are ignored with a warning.  The default value is 1.
1755 19 jeremybenn
 
1756
          Note: Or1ksim does not appear to use the `entrysize' parameter
1757 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1758 19 jeremybenn
          not seem to matter.
1759
 
1760
`ustates = VALUE'
1761
     The number of instruction usage states for the data or instruction
1762
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1763 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1764 19 jeremybenn
     value is 2.
1765
 
1766
          Note: Or1ksim does not appear to use the `ustates' parameter
1767 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1768 19 jeremybenn
          not seem to matter.
1769
 
1770
`hitdelay = VALUE'
1771
     Set the number of cycles a data or instruction (as appropriate) MMU
1772 82 jeremybenn
     hit costs.  Default value 1.
1773 19 jeremybenn
 
1774
`missdelay = VALUE'
1775
     Set the number of cycles a data or instruction (as appropriate) MMU
1776 82 jeremybenn
     miss costs.  Default value 1.
1777 19 jeremybenn
 
1778
 
1779

1780
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1781
 
1782
3.3.4 Cache Configuration
1783
-------------------------
1784
 
1785
Cache configuration is described in `section dc' (for the data cache)
1786 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1787
appear at most once.  The following parameters may be specified.
1788 19 jeremybenn
 
1789
`enabled = 0|1'
1790
     If 1 (true), the data or instruction (as appropriate) cache is
1791 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1792 19 jeremybenn
 
1793
`nsets = VALUE'
1794
     Sets the number of data or instruction (as appropriate) cache sets
1795
     to VALUE, which must be a power of two, not exceeding
1796
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1797 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1798
     both defined in the code to be 1024).  The default value is 1.
1799 19 jeremybenn
 
1800
`nways = VALUE'
1801
     Sets the number of data or instruction (as appropriate) cache ways
1802
     to VALUE, which must be a power of two, not exceeding
1803
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1804 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1805
     both defined in the code to be 32).  The default value is 1.
1806 19 jeremybenn
 
1807
`blocksize = VALUE'
1808
     The data or instruction (as appropriate) cache block size is set to
1809 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1810 19 jeremybenn
 
1811
`ustates = VALUE'
1812
     The number of instruction usage states for the data or instruction
1813
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1814
     The default value is 2.
1815
 
1816
`hitdelay = VALUE'
1817 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1818
     cache hit costs.  Default value 1.
1819 19 jeremybenn
 
1820
`missdelay = VALUE'
1821 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1822
     cache miss costs.  Default value 1.
1823 19 jeremybenn
 
1824
`load_hitdelay = VALUE'
1825 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1826
     costs.  Default value 2.
1827 19 jeremybenn
 
1828
`load_missdelay = VALUE'
1829 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1830
     miss costs.  Default value 2.
1831 19 jeremybenn
 
1832
`store_hitdelay = VALUE'
1833 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1834
     costs.  Default value 0.
1835 19 jeremybenn
 
1836
`store_missdelay = VALUE'
1837 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1838
     miss costs.  Default value 0.
1839 19 jeremybenn
 
1840
 
1841

1842
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1843
 
1844
3.3.5 Interrupt Configuration
1845
-----------------------------
1846
 
1847
Programmable Interrupt Controller (PIC) configuration is described in
1848 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1849
mechanism for handling multiple interrupt controllers.  The following
1850 19 jeremybenn
parameters may be specified.
1851
 
1852
`enabled = 0|1'
1853 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1854
 
1855 19 jeremybenn
 
1856
`edge_trigger = 0|1'
1857
     If 1 (true, the default), the programmable interrupt controller is
1858 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1859 19 jeremybenn
 
1860 432 jeremybenn
     The library interface (*note Simulator Library: Simulator Library.)
1861
     provides different functions for setting the different types of
1862
     interrupt, and a function to clear level sensitive interrupts. Edge
1863
     sensitive interrupts must be cleared by clearing the corresponding
1864
     bit in the PICSR SPR.
1865 19 jeremybenn
 
1866 432 jeremybenn
     Internal functions to set and clear interrupts are also provided
1867
     for peripherals implemented within Or1ksim. *Note Interrupts
1868
     Internal: Interrupts Internal for more details.
1869 430 julius
 
1870 432 jeremybenn
`use_nmi = 0|1'
1871
     If 1 (true, the default), interrupt lines 0 and 1 are
1872
     non-maskable. In other words the least significant 2 bits of the
1873
     PICMR SPR are hard-wired to 1.  If 0 (false), all interrupt lines
1874
     are treated as equivalent.
1875 430 julius
 
1876 432 jeremybenn
          Note: These are not non-maskable in the true sense that they
1877
          will pre-empt other interrupts.  Rather they can never be
1878
          masked out using the PICMR register. It is up the interrupt
1879
          exception handler to give these interrupt lines priority, and
1880
          indeed to decide on the priority order in general.
1881 430 julius
 
1882 432 jeremybenn
 
1883 19 jeremybenn

1884
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1885
 
1886
3.3.6 Power Management Configuration
1887
------------------------------------
1888
 
1889 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1890 19 jeremybenn
(which only happens when the power management unit is enabled) of
1891
setting the different bits in the power management Special Purpose
1892
Register (PMR, SPR 0x4000) is
1893
 
1894
`SDF (bit mask 0x0000000f)'
1895
     No effect - these bits are ignored
1896
 
1897
`DME (bit mask 0x00000010)'
1898
`SME (bit mask 0x00000020)'
1899
     Both these bits cause the processor to stop executing
1900 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1901 19 jeremybenn
     VAPI etc) carry on as normal.
1902
 
1903
`DCGE (bit mask 0x00000004)'
1904
     No effect - this bit is ignored
1905
 
1906
`SUME (bit mask 0x00000008)'
1907
     Enabling this bit causes a message to be printed, advising that the
1908
     processor is suspending and the simulator exits.
1909
 
1910
 
1911
On reset all bits are cleared.
1912
 
1913 82 jeremybenn
Power management configuration is described in `section pm'.  This
1914
section may appear at most once.  The following parameter may be
1915 19 jeremybenn
specified.
1916
 
1917
`enabled = 0|1'
1918 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1919
     is disabled.
1920 19 jeremybenn
 
1921
 
1922

1923
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1924
 
1925
3.3.7 Branch Prediction Configuration
1926
-------------------------------------
1927
 
1928
From examining the code base, it seems the branch prediction function
1929 82 jeremybenn
is not fully implemented.  At present the functionality seems
1930
restricted to collection of statistics.
1931 19 jeremybenn
 
1932 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1933
section may appear at most once.  The following parameters may be
1934 19 jeremybenn
specified.
1935
 
1936
`enabled = 0|1'
1937 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1938 19 jeremybenn
     is disabled.
1939
 
1940
`btic = 0|1'
1941
     If 1 (true), the branch target instruction cache model is enabled.
1942
     If 0 (the default), it is disabled.
1943
 
1944
`sbp_bf_fwd = 0|1'
1945 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1946 19 jeremybenn
 
1947
     instruction.
1948
 
1949
`sbp_bnf_fwd = 0|1'
1950 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1951
     If 0 (the default), do not use forward prediction for this
1952 19 jeremybenn
     instruction.
1953
 
1954
`hitdelay = VALUE'
1955 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1956 19 jeremybenn
     value 0.
1957
 
1958
`missdelay = VALUE'
1959 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1960 19 jeremybenn
     value 0.
1961
 
1962
 
1963

1964 556 julius
File: or1ksim.info,  Node: Debug Interface Configuration,  Next: Performance Counters Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1965 19 jeremybenn
 
1966
3.3.8 Debug Interface Configuration
1967
-----------------------------------
1968
 
1969
The debug unit and debug interface configuration is described in
1970 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1971 19 jeremybenn
parameters may be specified.
1972
 
1973
`enabled = 0|1'
1974 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1975 19 jeremybenn
     disabled.
1976
 
1977
          Note: This enables the functionality of the debug unit (its
1978 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1979
          external interface to the debug unit.  For that, see
1980 235 jeremybenn
          `rsp_enabled' below.
1981 19 jeremybenn
 
1982
`rsp_enabled = 0|1'
1983
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1984
     provding an interface to an external GNU debugger, using the port
1985
     specified in the `rsp_port' field (see below), or the
1986 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1987 19 jeremybenn
     not started, and no external interface is provided.
1988
 
1989
     For more detailed information on the interface to the GNU Debugger
1990
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1991
     Practical Experience with the OpenRISC 1000 Architecture', by
1992
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1993
 
1994
`rsp_port = VALUE'
1995
     VALUE specifies the port to be used for the GDB "Remote Serial
1996 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1997
     51000.  If the value 0 is specified, Or1ksim will instead look for
1998 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1999
 
2000
          Tip: There is no registered port for Or1ksim "Remote Serial
2001 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
2002
          users should adopt port values in the "Dynamic" or "Private"
2003
          port range, i.e.  49152-65535.
2004 19 jeremybenn
 
2005
`vapi_id = VALUE'
2006
     VALUE specifies the value of the Verification API (VAPI) base
2007 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
2008 19 jeremybenn
     Verification API, for more details.
2009
 
2010
     If this is specified and VALUE is non-zero, all OpenRISC Remote
2011
     JTAG protocol transactions will be logged to the VAPI log file, if
2012 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
2013
     the debug unit.  No VAPI commands are sent, nor requests handled.
2014 19 jeremybenn
 
2015
 
2016

2017 556 julius
File: or1ksim.info,  Node: Performance Counters Configuration,  Prev: Debug Interface Configuration,  Up: Core OpenRISC Configuration
2018
 
2019
3.3.9 Performance Counters Configuration
2020
----------------------------------------
2021
 
2022
The performance counters unit is described in `section pcu'.  This
2023
section may appear at most once.  The following parameters may be
2024
specified.
2025
 
2026
`enabled = 0|1'
2027
     If 1 (true), the performance counters unit is enabled.  If 0 (the
2028
     default), it is disabled.
2029
 
2030
 
2031

2032 19 jeremybenn
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
2033
 
2034
3.4 Configuring Memory Mapped Peripherals
2035
=========================================
2036
 
2037 82 jeremybenn
All peripheral components are optional.  If they are specified, then
2038 19 jeremybenn
(unlike other components) by default they are enabled.
2039
 
2040
* Menu:
2041
 
2042
* Memory Controller Configuration::
2043
* UART Configuration::
2044
* DMA Configuration::
2045
* Ethernet Configuration::
2046
* GPIO Configuration::
2047
* Display Interface Configuration::
2048
* Frame Buffer Configuration::
2049
* Keyboard Configuration::
2050
* Disc Interface Configuration::
2051
* Generic Peripheral Configuration::
2052
 
2053

2054
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
2055
 
2056
3.4.1 Memory Controller Configuration
2057
-------------------------------------
2058
 
2059
The memory controller used in Or1ksim is the component implemented at
2060 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
2061 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
2062 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
2063
memory mapped component, which resides on the main OpenRISC Wishbone
2064
data bus.
2065 19 jeremybenn
 
2066 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
2067 19 jeremybenn
section may appear multiple times, specifying multiple memory
2068 98 jeremybenn
controllers.
2069 19 jeremybenn
 
2070 385 jeremybenn
     Warning: There are known to be problems with the current memory
2071
     controller, which currently is not included in the regression test
2072
     suite. Users are advised not to use the memory controller in the
2073
     current release.
2074 98 jeremybenn
 
2075 385 jeremybenn
     Caution: There is no initialization code in the standard "newlib"
2076
     library.
2077
 
2078
     The standard "uClibc" library assumes a memory controller mapped
2079
     at 0x93000000 and will initialize the memory controller to expect
2080
     64MB memory blocks, and any memory declarations _must_ reflect
2081
     this.
2082
 
2083 98 jeremybenn
     If smaller memory blocks are declared with a memory controller,
2084
     then sufficient memory will not be allocated by Or1ksim, but out of
2085 346 jeremybenn
     range memory accesses will not be trapped.  For example declaring a
2086 98 jeremybenn
     memory section from 0-4MB with a memory controller enabled would
2087
     mean that accesses between 4MB and 64MB would be permitted, but
2088
     having no allocated memory would likely cause a segmentation fault.
2089
 
2090
     If the user is determined to use smaller memories with the memory
2091
     controller, then custom initialization code must be provided, to
2092
     ensure the memory controller traps out-of-memory accesses.
2093
 
2094
The following parameters may be specified.
2095
 
2096 19 jeremybenn
`enabled = 0|1'
2097 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
2098
     0, it is disabled.
2099 19 jeremybenn
 
2100
          Note: The memory controller can effectively also be disabled
2101
          by setting an appropriate power on control register value
2102 82 jeremybenn
          (see below).  However this should only be used if it is
2103 19 jeremybenn
          desired to specifically model this behavior of the memory
2104
          controller, not as a way of disabling the memory controller
2105
          in general.
2106
 
2107
`baseaddr = VALUE'
2108
     Set the base address of the memory controller's memory mapped
2109 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2110 19 jeremybenn
     sensible value.
2111
 
2112
     The memory controller has a 7 bit address bus, with a total of 19
2113
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
2114
     addresses 0x50 through 0x7c are not used).
2115
 
2116
`poc = VALUE'
2117
     Specifies the value of the power on control register, The least
2118
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
2119
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
2120
     the type of memory connected (use 0 for a disabled interface, 1
2121
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
2122
     devices).
2123
 
2124
     If other bits are specified, they are ignored with a warning.
2125
 
2126
          Caution: The default value, 0, corresponds to a disabled
2127
          8-bit bus, and is likely not the most suitable value
2128
 
2129
`index = VALUE'
2130
     Specify the index of this memory controller amongst all the memory
2131 82 jeremybenn
     controllers.  This value should be unique for each memory
2132 19 jeremybenn
     controller, and is used to associate specific memories with the
2133
     controller, through the `mc' field in the `section memory'
2134
     configuration (*note Memory Configuration: Memory Configuration.).
2135
 
2136
     The default value, 0, is suitable when there is only one memory
2137
     controller.
2138
 
2139
 
2140

2141
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
2142
 
2143
3.4.2 UART Configuration
2144
------------------------
2145
 
2146
The UART implemented in Or1ksim follows the specification of the
2147 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
2148 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
2149
 
2150
The component provides a number of interfaces to emulate the behavior
2151
of an external terminal connected to the UART.
2152
 
2153 82 jeremybenn
UART configuration is described in `section uart'.  This section may
2154
appear multiple times, specifying multiple UARTs.  The following
2155 19 jeremybenn
parameters may be specified.
2156
 
2157
`enabled = 0|1'
2158 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
2159 19 jeremybenn
     disabled.
2160
 
2161
`baseaddr = VALUE'
2162
     Set the base address of the UART's memory mapped registers to
2163 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2164 19 jeremybenn
 
2165
     The UART has a 3 bit address bus, with a total of 8 8-bit
2166
     registers, at addresses 0x0 through 0x7.
2167
 
2168
`channel = "TYPE:ARGS"'
2169
     Specify the channel representing the terminal connected to the UART
2170
     Rx & Tx pins.
2171
 
2172
    `channel="file:`rxfile',`txfile'"'
2173
          Read input characters from the file `rxfile' and write output
2174
          characters to the file `txfile' (which will be created if
2175
          required).
2176
 
2177
    `channel="xterm:ARGS"'
2178
          Create an xterm on startup, write UART Tx traffic to the
2179
          xterm and take Rx traffic from the keyboard when the xterm
2180 82 jeremybenn
          window is selected.  Additional arguments to the xterm
2181
          command (for example specifying window size may be specified
2182
          in ARGS, or this may be left blank.
2183 19 jeremybenn
 
2184
    `channel="tcp:VALUE"'
2185
          Open the TCP/IP port specified by VALUE and read and write
2186
          UART traffic from and to it.
2187
 
2188
          Typically a telnet session is connected to the other end of
2189
          this port.
2190
 
2191
               Tip: There is no registered port for Or1ksim telnet UART
2192 82 jeremybenn
               connection.  Priviledged access is required to read
2193 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
2194 346 jeremybenn
               Instead users should use port values in the "Dynamic" or
2195
               "Private" port range, i.e.  49152-65535.
2196 19 jeremybenn
 
2197
    `channel="fd:`rxfd',`txfd'"'
2198
          Read and write characters from and to the existing open
2199
          numerical file descriptors, file `rxfd' and `txfd'.
2200
 
2201
    `channel="tty:device=/dev/ttyS0,baud=9600"'
2202
          Read and write characters from and to a physical serial port.
2203 346 jeremybenn
          The precise device (shown here as `/dev/ttyS0') may vary from
2204
          machine to machine.
2205 19 jeremybenn
 
2206
 
2207
     The default value for this field is `"xterm:"'.
2208
 
2209
`irq = VALUE'
2210 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
2211 19 jeremybenn
 
2212
`16550 = 0|1'
2213 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
2214
     default), it has the functionality of a 16450.  The principal
2215 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
2216
 
2217
`jitter = VALUE'
2218
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
2219 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
2220 19 jeremybenn
 
2221
          Note: This functionality has yet to be implemented, so this
2222
          parameter has no effect.
2223
 
2224
`vapi_id = VALUE'
2225
     VALUE specifies the value of the Verification API (VAPI) base
2226 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
2227 19 jeremybenn
     Verification API, for more details, which details the use of the
2228
     VAPI with the UART.
2229
 
2230
 
2231

2232
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
2233
 
2234
3.4.3 DMA Configuration
2235
-----------------------
2236
 
2237
The DMA controller used in Or1ksim is the component implemented at
2238 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
2239 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
2240 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
2241
memory mapped component, which resides on the main OpenRISC Wishbone
2242
data bus.  The present implementation is incomplete, intended only to
2243
support the Ethernet interface (*note Ethernet Configuration::),
2244
although the Ethernet interface is not yet completed.
2245 19 jeremybenn
 
2246 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
2247
appear multiple times, specifying multiple DMA controllers.  The
2248 19 jeremybenn
following parameters may be specified.
2249
 
2250
`enabled = 0|1'
2251 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
2252
     it is disabled.
2253 19 jeremybenn
 
2254
`baseaddr = VALUE'
2255
     Set the base address of the DMA's memory mapped registers to
2256 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2257 19 jeremybenn
 
2258
     The DMA controller has a 10 bit address bus, with a total of 253
2259 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
2260
     0x010 control the overall behavior of the DMA controller.  There
2261
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
2262
     channels available.  Addresses 0x014 through 0x01c are not used.
2263 19 jeremybenn
 
2264
`irq = VALUE'
2265 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
2266 19 jeremybenn
     0.
2267
 
2268
`vapi_id = VALUE'
2269
     VALUE specifies the value of the Verification API (VAPI) base
2270 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
2271 19 jeremybenn
     API: Verification API, for more details, which details the use of
2272
     the VAPI with the DMA controller.
2273
 
2274
 
2275

2276
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
2277
 
2278
3.4.4 Ethernet Configuration
2279
----------------------------
2280
 
2281 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
2282
section may appear multiple times, specifying multiple Ethernet
2283
interfaces.  The following parameters may be specified.
2284 19 jeremybenn
 
2285 440 jeremybenn
The Ethernet MAC used in Or1ksim corresponds to the Verilog
2286
implementation in project "ethmac". It's source code can be found in
2287
the top level SVN directory, `ethmac'.  It also forms part of the
2288
OpenRISC reference SoC, ORPSoC.  It is described in the document
2289
`Ethernet IP Core Specification' by Igor Mohor, which can be found in
2290
the `doc' subdirectory.  It is a memory mapped component, which resides
2291
on the main OpenRISC Wishbone data bus.
2292
 
2293 19 jeremybenn
`enabled = 0|1'
2294 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
2295
     is disabled.
2296 19 jeremybenn
 
2297
`baseaddr = VALUE'
2298
     Set the base address of the MAC's memory mapped registers to
2299 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2300 19 jeremybenn
 
2301
     The Ethernet MAC has a 7-bit address bus, with a total of 21
2302 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
2303 19 jeremybenn
 
2304
          Note: The Ethernet specification describes a Tx control
2305 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
2306
          is not implemented in the Or1ksim model.
2307 19 jeremybenn
 
2308
`dma = VALUE'
2309
     VALUE specifies the DMA controller with which this Ethernet is
2310 82 jeremybenn
     associated.  The default value is 0.
2311 19 jeremybenn
 
2312
          Note: Support for external DMA is not provided in the current
2313 82 jeremybenn
          implementation, and this value is ignored.  In any case there
2314 19 jeremybenn
          is no equivalent field to which this can be matched in the
2315
          current DMA component implementation (*note DMA
2316
          Configuration: DMA Configuration.).
2317
 
2318
`irq = VALUE'
2319 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
2320 19 jeremybenn
 
2321 440 jeremybenn
`rtx_type = "file"|"tap"'
2322
     Specifies whether to use a TUN/TAP interface or file interface
2323
     (the default) to model the external connection of the Ethernet.
2324 19 jeremybenn
 
2325 440 jeremybenn
     If a TUN/TAP interface is requested, Ethernet packets will be sent
2326
     and received through the pesistent TAP interface specified in
2327
     parameter `tap_dev' (see below).
2328 19 jeremybenn
 
2329 440 jeremybenn
     More details on configuring the TUN/TAP interface are given in the
2330
     Usage section (*note Ethernet TUN/TAP Interface: Ethernet TUN/TAP
2331
     Interface.).
2332 19 jeremybenn
 
2333 440 jeremybenn
     If a file interface (the default), is requested, the Ethernet will
2334
     be modelled by reading and writing from and to the files specified
2335
     in the `rxfile' and `txfile' parameters (see below).
2336
 
2337
          Caution: If a file interface is specified, Or1ksim will
2338
          terminate once the receive file specified by `rxfile' is
2339
          exhausted.
2340
 
2341 19 jeremybenn
`rx_channel = RXVALUE'
2342
`tx_channel = TXVALUE'
2343
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
2344 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
2345 19 jeremybenn
 
2346
          Note: As noted above, support for external DMA is not
2347
          provided in the current implementation, and so these values
2348
          are ignored.
2349
 
2350
`rxfile = "RXFILE"'
2351
`txfile = "TXFILE"'
2352
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
2353
     as input and TXFILE specifies the fie to use as output.
2354
 
2355 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
2356
     packet length (32 bits), followed by that many bytes of data.
2357
     Once the input file is empty, the Ethernet MAC behaves as though
2358
     there were no data on the Ethernet.  The default values of these
2359 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
2360
 
2361 82 jeremybenn
     The input file must exist and be readable.  The output file must be
2362
     writable and will be created if necessary.  If either of these
2363 19 jeremybenn
     conditions is not met, a warning will be given.
2364
 
2365 440 jeremybenn
          Caution: Or1ksim will terminate once the RXFILE is exhausted.
2366 19 jeremybenn
 
2367 440 jeremybenn
`tap_dev = "TAP"'
2368
     When `rtx_type' is `"tap"' (see above), TAP_DEV specifies the TAP
2369
     device to use for communication.  This should be a persistent TAP
2370
     device configured for the system (*note Ethernet TUN/TAP
2371
     Interface: Ethernet TUN/TAP Interface.)
2372
 
2373 451 jeremybenn
`phy_addr = VALUE'
2374
     VALUE specifies the address for emulated ethernet PHY (default 0).
2375
     If there are multiple Ethernet peripherals, they should each have a
2376
     different PHY value.
2377
 
2378
`dummy_crc = 0|1'
2379
     If 1 (true, the default), the length of the data transferred to
2380
     the core will be increased by 4 bytes, as though the CRC were
2381
     included.
2382
 
2383
          Note: This is for historical consistency with the OpenRISC
2384
          Ethernet hardware MAC, which passes on the CRC in the data
2385
          packet. This is unusual behavior for a MAC, but the OpenRISC
2386
          Linux device drivers have been written to expect it.
2387
 
2388
`phy_addr = VALUE'
2389
     VALUE specifies the address for emulated ethernet PHY (default 0).
2390
     If there are multiple Ethernet peripherals, they should each have a
2391
     different PHY value.
2392
 
2393 19 jeremybenn
`vapi_id = VALUE'
2394
     VALUE specifies the value of the Verification API (VAPI) base
2395 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
2396 19 jeremybenn
     Verification API, for more details, which details the use of the
2397
     VAPI with the DMA controller.
2398
 
2399
 
2400

2401
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
2402
 
2403
3.4.5 GPIO Configuration
2404
------------------------
2405
 
2406
The GPIO used in Or1ksim is the component implemented at OpenCores, and
2407 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
2408 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
2409 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
2410 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
2411
 
2412 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
2413
appear multiple times, specifying multiple GPIO devices.  The following
2414 19 jeremybenn
parameters may be specified.
2415
 
2416
`enabled = 0|1'
2417 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
2418 19 jeremybenn
     disabled.
2419
 
2420
`baseaddr = VALUE'
2421
     Set the base address of the GPIO's memory mapped registers to
2422 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2423 19 jeremybenn
 
2424
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
2425
     registers, although the number of bits that are actively used
2426 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
2427 19 jeremybenn
 
2428
`irq = VALUE'
2429 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
2430 19 jeremybenn
 
2431
`vapi_id = VALUE'
2432
     VALUE specifies the value of the Verification API (VAPI) base
2433 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2434 19 jeremybenn
     Verification API, for more details, which details the use of the
2435 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2436 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2437
     but deprecated.
2438
 
2439
 
2440

2441
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2442
 
2443
3.4.6 Display Interface Configuration
2444
-------------------------------------
2445
 
2446
Or1ksim models a VGA interface to an external monitor.  The VGA
2447
controller used in Or1ksim is the component implemented at OpenCores,
2448 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2449 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2450 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2451 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2452
which resides on the main OpenRISC Wishbone data bus.
2453 19 jeremybenn
 
2454
The current implementation provides only functionality to dump the
2455
screen to a file at intervals.
2456
 
2457 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2458 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2459
The following parameters may be specified.
2460
 
2461
`enabled = 0|1'
2462 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2463 19 jeremybenn
     disabled.
2464
 
2465
`baseaddr = VALUE'
2466
     Set the base address of the VGA controller's memory mapped
2467 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2468 19 jeremybenn
     sensible value.
2469
 
2470
     The VGA controller has a 12-bit address bus, with 7 32-bit
2471
     registers, at addresses 0x000 through 0x018, and two color lookup
2472 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2473 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2474
     are not used.
2475
 
2476
`irq = VALUE'
2477 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2478 19 jeremybenn
     0.
2479
 
2480
`refresh_rate = VALUE'
2481 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2482 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2483
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2484
     50 times per simulated second.
2485
 
2486
`txfile = "FILE"'
2487
     FILE specifies the base of the filename for screen dumps.
2488
     Successive screen dumps will be in BMP format, in files with the
2489
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2490 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2491 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2492
     supported for this parameter, but deprecated.
2493
 
2494
 
2495

2496
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2497
 
2498
3.4.7 Frame Buffer Configuration
2499
--------------------------------
2500
 
2501 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2502 19 jeremybenn
     configuration fields are described here, but the component should
2503 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2504 19 jeremybenn
     to make screen dumps to file.
2505
 
2506 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2507
may appear multiple times, specifying multiple frame buffers.  The
2508 19 jeremybenn
following parameters may be specified.
2509
 
2510
`enabled = 0|1'
2511 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2512 19 jeremybenn
     is disabled.
2513
 
2514
`baseaddr = VALUE'
2515
     Set the base address of the frame buffer's memory mapped registers
2516 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2517
     value.
2518 19 jeremybenn
 
2519
     The frame buffer has an 121-bit address bus, with 4 32-bit
2520
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2521 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2522 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2523
 
2524
`refresh_rate = VALUE'
2525 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2526 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2527
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2528
     50 times per simulated second.
2529
 
2530
`txfile = "FILE"'
2531
     FILE specifies the base of the filename for screen dumps.
2532
     Successive screen dumps will be in BMP format, in files with the
2533
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2534 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2535 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2536
     supported for this parameter, but deprecated.
2537
 
2538
 
2539

2540
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2541
 
2542
3.4.8 Keyboard Configuration (PS2)
2543
----------------------------------
2544
 
2545 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2546 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2547 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2548
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2549 19 jeremybenn
standard, this is presumably what is expected with this device.
2550
 
2551
The implementation only provides for keyboard support, which is
2552 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2553 19 jeremybenn
 
2554
     Caution: A standard i8042 device has two registers at addresses
2555 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2556
     suggests that the Or1ksim component places these registers at
2557
     addresses 0x00 and 0x04.
2558 19 jeremybenn
 
2559
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2560
     implements the i8042 device driver, anticipating these registers
2561 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2562 19 jeremybenn
     code will work.
2563
 
2564
     This component should be used with caution.
2565
 
2566 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2567
appear multiple times, specifying multiple keyboard interfaces.  The
2568 19 jeremybenn
following parameters may be specified.
2569
 
2570
`enabled = 0|1'
2571 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2572 19 jeremybenn
     disabled.
2573
 
2574
`baseaddr = VALUE'
2575
     Set the base address of the keyboard's memory mapped registers to
2576 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2577 19 jeremybenn
 
2578
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2579
     registers, at addresses 0x000 and 0x004.
2580
 
2581
          Caution: As noted above, a standard Intel 8042 interface
2582
          would expect to find these registers at locations 0x60 and
2583
          0x64, thus requiring at least a 7-bit bus.
2584
 
2585
`irq = VALUE'
2586 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2587 19 jeremybenn
     value 0.
2588
 
2589
`rxfile = "FILE"'
2590
     `file' specifies a file containing raw key stroke data, which
2591 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2592 19 jeremybenn
     `"kbd_in"'.
2593
 
2594
 
2595

2596
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2597
 
2598
3.4.9 Disc Interface Configuration
2599
----------------------------------
2600
 
2601
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2602
IDE Controller) component implemented at OpenCores, and found in the
2603 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2604 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2605 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2606
which resides on the main OpenRISC Wishbone data bus.
2607 19 jeremybenn
 
2608 385 jeremybenn
     Warning: In the current release of Or1ksim, parsing of the ATA
2609
     section is broken. Users should not configure the disc interface
2610
     in this release.
2611
 
2612 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2613
may appear multiple times, specifying multiple disc controllers.  The
2614 19 jeremybenn
following parameters may be specified.
2615
 
2616
`enabled = 0|1'
2617 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2618 19 jeremybenn
     0, it is disabled.
2619
 
2620
`baseaddr = VALUE'
2621
     Set the base address of the ATA/ATAPI interface's memory mapped
2622 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2623 19 jeremybenn
     sensible value.
2624
 
2625
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2626 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2627
     ATA/ATAPI interface selected (see `dev_id' below), not all
2628
     registers will be available.
2629 19 jeremybenn
 
2630
`irq = VALUE'
2631 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2632 19 jeremybenn
     value 0.
2633
 
2634
`dev_id = 1|2|3'
2635
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2636 82 jeremybenn
     interface to model.  The default value is 1.
2637 19 jeremybenn
 
2638
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2639
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2640
     registers and the `RXD'/`TXD' registers.
2641
 
2642
`rev = VALUE'
2643
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2644 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2645
     be in the range 0-15.  Larger values are truncated with a warning.
2646 346 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2647
     forms bits 24-27.
2648 19 jeremybenn
 
2649
`pio_mode0_t1 = VALUE'
2650
`pio_mode0_t2 = VALUE'
2651
`pio_mode0_t4 = VALUE'
2652
`pio_mode0_teoc = VALUE'
2653
     These parameters specify the timings for use with Programmed
2654 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2655 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2656 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2657 19 jeremybenn
     they do, they will be ignored with a warning.
2658
 
2659
     See the ATA/ATAPI-5 specification for explanations of each of these
2660 82 jeremybenn
     timing parameters.  The default values are:
2661 19 jeremybenn
 
2662
          pio_mode0_t1   =  6
2663
          pio_mode0_t2   = 28
2664
          pio_mode0_t4   =  2
2665
          pio_mode0_teoc = 23
2666
 
2667
`dma_mode0_tm = VALUE'
2668
`dma_mode0_td = VALUE'
2669
`dma_mode0_teoc = VALUE'
2670
     These parameters specify the timings for use with DMA transfers.
2671
     They are specified as the number of clock cycles - 2, rounded up
2672
     to the next highest integer, or zero if that would be negative.
2673 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2674
     ignored with a warning.
2675 19 jeremybenn
 
2676
     See the ATA/ATAPI-5 specification for explanations of each of these
2677 82 jeremybenn
     timing parameters.  The default values are:
2678 19 jeremybenn
 
2679
          dma_mode0_tm   =  4
2680
          dma_mode0_td   = 21
2681
          dma_mode0_teoc = 21
2682
 
2683
 
2684
3.4.9.1 ATA/ATAPI Device Configuration
2685
......................................
2686
 
2687 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2688 19 jeremybenn
device subsection is introduced by
2689
 
2690
     device VALUE
2691
 
2692 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2693
ends with `enddevice'.  Note that if the same device number is
2694
specified more than once, the previous values will be overwritten.
2695
Within the `device' subsection, the following parameters may appear:
2696 19 jeremybenn
 
2697
`type = VALUE'
2698
     VALUEspecifies the type of device: 0 (the default) for "not
2699
     connected", 1 for hard disk simulated in a file and 2 for local
2700
     system hard disk.
2701
 
2702
`file = "FILENAME"'
2703
     `filename' specifies the file to be used for a simulated ATA
2704 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2705 346 jeremybenn
     `"ata_fileN"', where N is the device number.
2706 19 jeremybenn
 
2707
`size = VALUE'
2708
     VALUE specifies the size of a simulated ATA device if the file
2709 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2710 19 jeremybenn
 
2711
`packet = 0|1'
2712 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2713 19 jeremybenn
     default), do not implement the PACKET command feature set.
2714
 
2715
`firmware = "STR"'
2716
     Firmware to report in response to the "Identify Device" command.
2717
     Default `"02207031"'.
2718
 
2719
`heads = VALUE'
2720 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2721 19 jeremybenn
     heads.
2722
 
2723
`sectors = VALUE'
2724 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2725 19 jeremybenn
 
2726
`mwdma = 0|1|2|-1'
2727 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2728 19 jeremybenn
     disable.
2729
 
2730
`pio = 0|1|2|3|4'
2731 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2732 19 jeremybenn
 
2733
 
2734

2735
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2736
 
2737
3.4.10 Generic Peripheral Configuration
2738
---------------------------------------
2739
 
2740
When used as a library (*note Simulator Library: Simulator Library.),
2741
Or1ksim makes provision for any additional peripheral to be implemented
2742 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2743
generates "upcall"s to an external handler.  This interface can support
2744 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2745
for OSCI SystemC (see `http://www.systemc.org').
2746
 
2747
Generic peripheral configuration is described in `section generic'.
2748
This section may appear multiple times, specifying multiple external
2749 82 jeremybenn
peripherals.  The following parameters may be specified.
2750 19 jeremybenn
 
2751
`enabled = 0|1'
2752 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2753 19 jeremybenn
     0, it is disabled.
2754
 
2755
`baseaddr = VALUE'
2756
     Set the base address of the generic peripheral's memory mapped
2757 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2758 19 jeremybenn
     sensible value.
2759
 
2760
     The size of the memory mapped register space is controlled by the
2761
     `size' paramter, described below.
2762
 
2763
`size = VALUE'
2764
     Set the size of the generic peripheral's memory mapped register
2765 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2766 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2767
     parameter `baseaddr' (see above) will be directed to the external
2768
     interface.
2769
 
2770 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2771
     value is zero.  If VALUE is not an exact power of two, accesses to
2772 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2773
     generate a warning, and have no effect (reads will return zero).
2774
 
2775
`name = "STR"'
2776 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2777 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2778 82 jeremybenn
     reporting its status.  The default value is
2779 19 jeremybenn
     `"anonymous external peripheral"'.
2780
 
2781
`byte_enabled = 0|1'
2782
`hw_enabled = 0|1'
2783
`word_enabled = 0|1'
2784
     If 1 (true, the default), these parameters respectively enable the
2785 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2786 19 jeremybenn
     accesses of that width will fail.
2787
 
2788
 
2789

2790
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2791
 
2792
4 Interactive Command Line
2793
**************************
2794
 
2795
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2796 82 jeremybenn
provides the user with an interactive command line.  The commands
2797 19 jeremybenn
available, which may not be abbreviated, are:
2798
 
2799
`q'
2800
     Exit the simulator
2801
 
2802
`r'
2803 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2804 19 jeremybenn
     just executed and next to be executed instructions symbolically
2805
     and the state of the flag in the Supervision Register.
2806
 
2807
`t'
2808
     Execute the next instruction and then display register/instruction
2809
     information as with the `r' command (see above).
2810
 
2811
`run NUM [ hush ]'
2812 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2813 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2814
     above) _unless_ `hush' is specified.
2815
 
2816
`pr REG VALUE'
2817
     Patch register REG with VALUE.
2818
 
2819
`dm FROMADDR [ TOADDR ]'
2820 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2821
     not given, 64 bytes are displayed, starting at FROMADDR.
2822 19 jeremybenn
 
2823
          Caution: The output from this command is broken (a bug).
2824 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2825 19 jeremybenn
          instead of printing out the address at the start of each row,
2826
          it prints the address (of the first of the 16 bytes) before
2827
          _each_ byte.
2828
 
2829
`de FROMADDR [ TOADDR ]'
2830 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2831 19 jeremybenn
     given, 16 instructions are disassembled.
2832
 
2833
     The disassembly is entirely numerical, and gives no symbolic
2834
     information.
2835
 
2836
`pm ADDR VALUE'
2837
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2838
 
2839
`pc VALUE'
2840
     Patch the program counter with VALUE.
2841
 
2842
`cm FROMADDR TOADDR SIZE'
2843
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2844
 
2845
`break ADDR'
2846
     Toggle the breakpoint set at ADDR.
2847
 
2848
`breaks'
2849
     List all set breakpoints
2850
 
2851
`reset'
2852 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2853
     so execution will restart from the reset vector location, 0x100.
2854 19 jeremybenn
 
2855
`hist'
2856
     If saving the execution history has been configured (*note
2857
     Simulator Behavior: Simulator Behavior.), display the execution
2858
     history.
2859
 
2860
`stall'
2861
     Stall the processor, so that control is passed to the debug unit.
2862 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2863 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2864
     debuggers such as GDB.
2865
 
2866
`unstall'
2867 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2868
     This command is useful when debugging the JTAG interface, used by
2869 19 jeremybenn
     debuggers such as GDB.
2870
 
2871
`stats CATEGORY | clear'
2872
     Print the statistics for the given CATEGORY, if available, or
2873 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2874 19 jeremybenn
 
2875
    1
2876
          Miscellaneous statistics: branch predictions (if branch
2877
          predictions are enabled), branch target cache model (if
2878
          enabled), cache (if enbaled), MMU (if enabled) and number of
2879
          addtional load & store cycles.
2880
 
2881
          *Note Configuring the OpenRisc Achitectural Components: Core
2882
          OpenRISC Configuration, for details of how to enable these
2883
          various features.
2884
 
2885
    2
2886 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2887 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2888
 
2889
    3
2890 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2891 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2892
 
2893
    4
2894 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2895 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2896
          Configuration.).
2897
 
2898
    5
2899 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2900 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2901
 
2902
    6
2903 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2904 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2905
 
2906
 
2907
`info'
2908
     Display detailed information about the simulator configuration.
2909
     This is quite a lengthy about, because all MMU TLB information is
2910
     displayed.
2911
 
2912
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2913
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2914 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2915 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2916 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2917 19 jeremybenn
 
2918
     To save to a file, use the redirection function (described after
2919
     this table, below).
2920
 
2921
`dh FROMADDR [ TOADDR ]'
2922
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2923 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2924 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2925
 
2926
     To save to a file, use the redirection function (described after
2927
     this table, below).
2928
 
2929
`setdbch'
2930 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2931 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2932
     channels on the command line.
2933
 
2934
`set SECTION PARAM = VALUE'
2935
     Set the configuration parameter PARA in section SECTION to VALUE.
2936
     *Note Configuration: Configuration, for details of configuration
2937
     parameters and their settings.
2938
 
2939
`debug'
2940 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2941 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2942
     this parameter.
2943
 
2944
          Caution: This is effectively enabling or disabling the debug
2945 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2946 19 jeremybenn
          However using the remote debug interface while the debug unit
2947
          is disabled will lead to undefined behavior and likely crash
2948
          Or1ksim
2949
 
2950
`cuc'
2951
     Enter the the Custom Unit Compiler command prompt (*note CUC
2952
     Configuration: CUC Configuration.).
2953
 
2954
          Caution: The CUC must be properly configured, for this to
2955 82 jeremybenn
          succeed.  In particular a timing file must be available and
2956
          readable.  Otherwise Or1ksim will crash.
2957 19 jeremybenn
 
2958
`help'
2959
     Print out brief information about each command available.
2960
 
2961
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2962 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2963 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2964
     Profiling Utility.).
2965
 
2966
`profile [-vhcq] [-g FILE]'
2967 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2968
     usage as the standalone command (*note Profiling Utility:
2969
     Profiling Utility.).
2970 19 jeremybenn
 
2971
 
2972
For all commands, it is possible to redirect the output to a file, by
2973
using the redirection operator, `>'.
2974
 
2975
     COMMAND > FILENAME
2976
 
2977
This is particularly useful for commands dumping a large amount of
2978
output, such as `dv'.
2979
 
2980
     Caution: Unfortunately there is a serious bug with the redirection
2981 82 jeremybenn
     operator.  It does not return output to standard output after the
2982
     command completes.  Until this bug is fixed, file redirection
2983 19 jeremybenn
     should not be used.
2984
 
2985

2986
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2987
 
2988
5 Verification API (VAPI)
2989
*************************
2990
 
2991
The Verification API (VAPI) provides a TCP/IP interface to allow
2992 82 jeremybenn
components of the simulation to be controlled externally.  The
2993
interface is polled for new requests on each simulated clock cycle.
2994
Components within the simulator may send responses to such requests.
2995 19 jeremybenn
 
2996 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2997
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2998
with a single piece of data (also a 32 bit integer).  On the send side,
2999
it provides for sending a single VAPI ID and data.  However there is no
3000
explicit command-response structure.  Some components just accept
3001
requests (e.g.  to set values), some just generate sends (to report
3002 19 jeremybenn
values), and some do both.
3003
 
3004
Each component has a base ID (32 bit) and its commands will start from
3005 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
3006
amongst components.  Request commands will be directed to the component
3007 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
3008
 
3009
Thus if there are two components with base IDs of 0x200 and 0x300, and
3010
a request with VAPI ID of 0x203 is received, it will be directed to the
3011
first component as its command #3.
3012
 
3013
The results of VAPI interactions are logged (by default in `vapi.log'
3014
unless an alternative is specified in `section vapi').
3015
 
3016
Currently the following components support VAPI:
3017
 
3018
Debug Unit
3019
     Although the Debug Unit can specify a base VAPI ID, it is not used
3020
     to send commands or receive requests.
3021
 
3022
     Instead, if the base VAPI ID is set, all remote JTAG protocol
3023
     exchanges are logged in the VAPI log file.
3024
 
3025
UART
3026
     If a base VAPI ID is specified, the UART sends details of any
3027
     chars or break characters sent, with dteails of the line control
3028
     register etc encoded in the data packet sent.
3029
 
3030
     This supports a single VAPI command request, but encodes a
3031
     sub-command in the top 8 bits of the associated data.
3032
 
3033
    `0x00'
3034
          This stuffs the least significant 8 bits of the data into the
3035
          serial register of the UART and the next 8 bits into the line
3036
          control register, effectively providing control of the next
3037
          character to be sent or received.
3038
 
3039
    `0x01'
3040
          The divisor latch bytes are set from the least significant 16
3041
          bits of the data.
3042
 
3043
    `0x02'
3044
          The line control register is set from bits 15-8 of the data.
3045
 
3046
    `0x03'
3047
          The UART skew is set from the least significant 16 bits of
3048
          the data
3049
 
3050
    `0x04'
3051
          If the 16th most significant bit of the data is 1, start
3052 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
3053
          are sent or cleared after the number of UART clock divider
3054
          ticks specified by the data (immediately if the data is zero).
3055 19 jeremybenn
 
3056
 
3057
DMA
3058
     Although the DMA unit supports a base VAPI ID in its configuration
3059
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
3060
     implemented.
3061
 
3062
Ethernet
3063 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
3064 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
3065 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
3066 19 jeremybenn
     VAPI requests.
3067
 
3068
    `ETH_VAPI_DATA (0)'
3069
 
3070
    `ETH_VAPI_CTRL (0)'
3071
 
3072
GPIO
3073
     If a base VAPI ID is specified, the GPIO sends out on its base
3074
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
3075
     VAPI ID) any changes in outputs.
3076
 
3077 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
3078 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
3079
     GPIO.
3080
 
3081
    `GPIO_VAPI_DATA (0)'
3082
          Set the next input to the commands data field
3083
 
3084
    `GPIO_VAPI_AUX (1)'
3085
          Set the GPIO auxiliary inputs to the data field
3086
 
3087
    `GPIO_VAPI_CLOCK (2)'
3088
          Add an external GPIO clock trigger of period specified in the
3089
          data field.
3090
 
3091
    `GPIO_VAPI_RGPIO_OE (3)'
3092
          Set the GPIO output enable to the data field
3093
 
3094
    `GPIO_VAPI_RGPIO_INTE (4)'
3095
          Set the next interrupt to the data field
3096
 
3097
    `GPIO_VAPI_RGPIO_PTRIG (5)'
3098
          Set the next trigger to the data field
3099
 
3100
    `GPIO_VAPI_RGPIO_AUX (6)'
3101
          Set the next auxiliary input to the data field
3102
 
3103
    `GPIO_VAPI_RGPIO_CTRL (7)'
3104
          Set th next control input to the data field
3105
 
3106
 
3107
 
3108

3109
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
3110
 
3111
6 A Guide to Or1ksim Internals
3112
******************************
3113
 
3114 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
3115 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
3116 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
3117
Linux manual page for `etags'.  A tag file can be created with:
3118 19 jeremybenn
 
3119
     make tags
3120
 
3121
* Menu:
3122
 
3123
* Coding Conventions::
3124
* Global Data Structures::
3125
* Concepts::
3126
* Internal Debugging::
3127 104 jeremybenn
* Regression Testing::
3128 19 jeremybenn
 
3129

3130
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
3131
 
3132
6.1 Coding Conventions for Or1ksim
3133
==================================
3134
 
3135
This chapter provides some guidelines for coding, to facilitate
3136
extensions to Or1ksim
3137
 
3138
_GNU Coding Standard_
3139
     Code should follow the GNU coding standard for C
3140 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
3141 19 jeremybenn
     through the `indent' program.
3142
 
3143
_`#include' headers_
3144
     All C source code files should include `config.h' before any other
3145
     file.
3146
 
3147
     This should be followed by inclusion of any system headers (but see
3148
     the comments about portability and `port.h' below) and then by any
3149
     Or1ksim package headers.
3150
 
3151
     If `port.h' is required, it should be the first package header to
3152
     be included after the system headers.
3153
 
3154
     All C source code and header files should directly include any
3155 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
3156
     other header having already included it.  The two exceptions are
3157 19 jeremybenn
 
3158
       1. All header files may assume that `config.h' has already been
3159
          included.
3160
 
3161
       2. System headers which impose portability problems should be
3162
          included by using the package header `port.h', rather than
3163 82 jeremybenn
          the system headers themselves.  This is the case for code
3164 19 jeremybenn
          requiring
3165
 
3166
             * `strndup' (from `string.h')
3167
 
3168
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
3169
 
3170
             * `isblank' (from `ctype.h')
3171
 
3172
 
3173
 
3174
_`#include' files once only_
3175
     All include files should be protected by `#ifndef' to ensure their
3176 82 jeremybenn
     definitions are only included once.  For instance a header file
3177 19 jeremybenn
     `X-Y.H' should surround its contents with:
3178
 
3179
          #ifndef X_Y__H
3180
          #define X_Y__H
3181
 
3182
          
3183
 
3184
          #endif  /* X_Y__H */
3185
 
3186
_Avoid `typedef'_
3187
     The GNU coding style for C does not have a clear way to distinguish
3188 82 jeremybenn
     between user type name and user variables.  For this reason
3189 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
3190 82 jeremybenn
     defined types.  This makes the code much easier to read.
3191 19 jeremybenn
 
3192
     There are some `typedef' declarations in the `argtable2' library
3193
     and the ELF and COFF headers, because this code is taken from
3194
     other places.
3195
 
3196
     Within Or1ksim legacy uses of `typedef' have largely been purged,
3197
     except in the Custom Unit Compiler (*note Custom Unit Compiler
3198
     (CUC) Configuration: CUC Configuration.).
3199
 
3200
     The remaining uses of `typedef' occur in two places:
3201
 
3202
        * `port/port.h' defines types to replace those in header files
3203
          that are not available (character functions, string
3204
          duplication, integer types).
3205
 
3206
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
3207
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
3208
          and signed register (`orreg_t') values.
3209
 
3210
 
3211
     Where new types are defined, they should appear in one of these two
3212 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
3213
     `arch.h' should always have the suffix `_h'.
3214 19 jeremybenn
 
3215
_Don't begin names with underscore_
3216
     Names beginning with `_' are intended to be part of the C
3217 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
3218 19 jeremybenn
 
3219
_Keep Non-global top level entities static_
3220
     All top level entities (functions, variables), which are not
3221
     explicitly part of a global interface should be declared static.
3222
     This ensures that unwanted connections are not inadvertently built
3223
     across the program.
3224
 
3225
_Use of `inline'_
3226 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
3227 19 jeremybenn
     out for themselves what is best in this respect.
3228
 
3229
_Initialization_
3230 82 jeremybenn
     All data structures should be explicitly initialized.  In
3231
     particular code should not rely on static data structures being
3232
     initialized to zero.
3233 19 jeremybenn
 
3234
     The rationale is that in future static data structures may become
3235 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
3236 19 jeremybenn
     historically.
3237
 
3238
     A specific case is with new peripherals, which should always
3239
     include a `start' function to pre-initialize all configuration
3240
     parameters to sensible defaults
3241
 
3242
_Configuration Validation_
3243
     All configuration values should be validated, preferably when
3244
     encountered, if not when the `section' is closed, or otherwise at
3245
     run time when the parameter is first used.
3246
 
3247
 
3248

3249
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
3250
 
3251
6.2 Global Data Structures
3252
==========================
3253
 
3254
`config'
3255
     The global variable `config' of type `struct config' holds the
3256
     configuration data for some of the Or1ksim components which are
3257 82 jeremybenn
     always present.  At present the components are:
3258 19 jeremybenn
 
3259
        * The simulator defined in `section sim' (*note Simulator
3260
          Configuration: Simulator Configuration.).
3261
 
3262
        * The Verification API (VAPI) defined  in `section vapi' (*note
3263
          Verification API (VAPI) Configuration: Verification API
3264
          Configuration.).
3265
 
3266
        * The Custom Unit Compiler (CUC), defined in `section cuc'
3267
          (*note Custom Unit Compiler (CUC) Configuration: CUC
3268
          Configuration.).
3269
 
3270
        * The CPU, defined in `section cpu' (*note CPU Configuration:
3271
          CPU Configuration.).
3272
 
3273
        * The data cache (but not the instruction cache), defined in
3274
          `section dc' (*note Cache Configuration: Cache
3275
          Configuration.).
3276
 
3277
        * The power management unit, defined in `section pm' (*note
3278
          Power Management Configuration: Power Management
3279
          Configuration.).
3280
 
3281
        * The programmable interrupt controller, defined in
3282
          `section pic' (*note Interrupt Configuration: Interrupt
3283
          Configuration.).
3284
 
3285
        * Branch prediciton, defined in `section bpb' (*note Branch
3286
          Prediction Configuration: Branch Prediction Configuration.).
3287
 
3288
        * The debug unit, defined in `section debug' (*note Debug
3289
          Interface Configuration: Debug Interface Configuration.).
3290
 
3291
 
3292
     This struct is made of a collection of structs, one for each
3293 82 jeremybenn
     component.  For example the simulator configuration is held in
3294 19 jeremybenn
     `config.sim'.
3295
 
3296
`config'
3297
     This is a linked list of data structures holding configuration data
3298
     for all sections which are not held in the main `config' data
3299 82 jeremybenn
     structure.  In general these are components (such as peripherals
3300
     and memory) which may occur multiple times.  However it also
3301
     handles some architectural components which may occur only once,
3302
     such as the memory management units, the instruction cache, the
3303
     interrupt controller and branch prediction.
3304 19 jeremybenn
 
3305
`runtime'
3306
     The global variable `runtime' of type `struct runtime' holds all
3307 82 jeremybenn
     the runtime information about the simulation.  To access this
3308 19 jeremybenn
     variable, `sim-config.h' must be included.
3309
 
3310
     This struct is itself made of 3 other structs, `cpu' (for CPU run
3311
     time state), `vapi' (for Verification API state) and `cuc' (for
3312
     Custom Unit Compiler state).
3313
 
3314
 
3315

3316
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
3317
 
3318
6.3 Concepts
3319
============
3320
 
3321
_Output Redirection_
3322 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
3323 19 jeremybenn
     should be explicitly written to this stream, or may use the
3324
     `PRINTF' macro, which will write its arguments to this output
3325
     stream.
3326
 
3327
_Reset Hooks_
3328
     Any peripheral may register a routine to be called when the the
3329
     processor is reset by calling `reg_sim_reset', providing a
3330 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
3331 19 jeremybenn
     that function will be called with the data stucture pointer as
3332
     argument.
3333
 
3334 432 jeremybenn
_Interrupts_
3335
     An internal peripheral can model the effect of an interrupt being
3336
     asserted by calling `report_interrupt'.  This is used for both edge
3337
     and level sensitive interrupts.
3338 19 jeremybenn
 
3339 432 jeremybenn
     The effect is to set the corresponding bit in the PICSR SPR and to
3340
     queue an interrupt exception to take place after the current
3341
     instruction completes execution.
3342
 
3343
     Externally, the different interrupts require different mechanisms
3344
     for clearing.  Level sensitive interrupts should be cleared by
3345
     deasserting the interrupt line, edge sensitive interrupts by
3346
     clearing the corresponding bit in the PICSR SPR.
3347
 
3348
     Internally this amounts to the same thing (clearing the PICSPR
3349
     bit), so a single function is provided, `clear_interrupt'.  Note
3350
     however that when level sensitive interrupts are configured, PICSR
3351
     is read only, and can only be cleared by calling
3352
     `clear_interrupt'.  Using the two functions provided will ensure
3353
     the peripheral works correctly whichever type of interrupt is used.
3354
 
3355
          Note: Until an interrupt is cleared, all subsequent
3356
          interrupts are ignored with a warning.
3357
 
3358
 
3359 19 jeremybenn

3360 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
3361 19 jeremybenn
 
3362
6.4 Internal Debugging
3363
======================
3364
 
3365
The function `debug' is like `printf', but with an extra first
3366 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
3367
the simulator configuration (*note Simulator Behavior: Simulator
3368
Behavior.) is greater than or equal to this value, the remaining
3369
arguments are printed to the current output stream (*note Output
3370
Redirection: Output Redirection.).
3371 19 jeremybenn
 
3372

3373 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
3374
 
3375
6.5 Regression Testing
3376
======================
3377
 
3378
Or1ksim now includes a regression test suite for both standalone and
3379
library usage as described earlier (*note Building and Installing:
3380
Build and Install.).  Running the tests requires that the OpenRISC
3381
toolchain and DejaGNU are both installed.
3382
 
3383
Tests are written using `expect', a derivative of TCL.  Documentation
3384
of DejaGnu, `expect' and TCL are freely available on the Web.  The
3385
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
3386
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
3387
provides a concise introduction.
3388
 
3389
All test code is found in the `testsuite' directory.  The key files and
3390
directories used are as follows.
3391
 
3392
`global-conf.exp'
3393
     This is the global DejaGNU configuration file used to set up
3394
     parameters common to all tests.  If the user has the environment
3395
     varialbe `DEJAGNU' defined, it will be used instead, but this is
3396
     not recommended.
3397
 
3398
`Makefile.am'
3399
     This is the top level `automake' file for the testsuite.  The only
3400
     changes likely to be needed here is additional local cleanup of
3401
     files created by new tests.
3402
 
3403
`README'
3404
     This contains details of all the tests
3405
 
3406
`config'
3407
     This contains DejaGnu board configurations.  Since the tests are
3408
     generally run on a Unix host, this should just contain `Unix.exp'.
3409
 
3410
`lib'
3411
     This contains DejaGnu tool specific configurations.  "Tool" has a
3412
     specific meaning in DejaGNU, referring just to a grouping of
3413
     tests.  In this case there are two such "tools", "or1ksim" and
3414
     "libsim" for tests of the standalone tool and tests of the library.
3415
 
3416
     Corresponding to this, there are two tool specific configuration
3417
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
3418
     procedures for common use among the tests.
3419
 
3420
`libsim.tests'
3421
`or1ksim.tests'
3422
     These are the directories of tests of the Or1ksim library.  They
3423
     also include Or1ksim configuration files and each has a
3424
     `Makefile.am' file.  `Makefile.am' should be updated whenever
3425
     files are added to this directory, to ensure they are included in
3426
     the distribution.
3427
 
3428
`test-code'
3429
     These are all the test programs to be compiled on the host (each
3430
     in its own directory).  In general these are programs to support
3431
     testing of the library, and build various programs linking in the
3432
     library.
3433
 
3434
`test-code'
3435
     These are all the test programs to be compiled with the OpenRISC
3436
     tool chain to run with either standalone Or1ksim or the library.
3437
     This directory includes its own `configure.ac', since it must set
3438
     up a separate tool chain based on the target, not the host.
3439
 
3440
 
3441
To add a new test needs the following steps.
3442
 
3443 346 jeremybenn
   * Put new host C code in its own directory within `test-code'.  Add
3444 104 jeremybenn
     the directory to the existing `Makefile.am' in the `test-code'
3445
     directory and create a `Makefile.am' in the new directory to drive
3446 346 jeremybenn
     building the test program(s).  Don't forget to add the new
3447 104 jeremybenn
     `Makefile' to the top level `configure.ac' so it gets generated.
3448
     Not all tests require code here.
3449
 
3450 346 jeremybenn
   * Put new target C code in its own directory within `test-code-or1k'.
3451
     Once again modify & create `Makefile.am'.  This time modify the
3452
     `configure.ac' in the `test-code-or1k' so the `Makefile' gets
3453
     generated.  The existing programs provide examples to start from,
3454
     including custom linker scripts where needed.
3455 104 jeremybenn
 
3456
   * Add one or more tests and configuration files to the relevant
3457 346 jeremybenn
     "tool" test directory.  Use the existing tests as templates.  They
3458 104 jeremybenn
     make heavy use of the `expect'/TCL procedures in the `config'
3459
     directory to facilitate driving the tests.
3460
 
3461
 
3462

3463 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3464
 
3465
7 GNU Free Documentation License
3466
********************************
3467
 
3468
                      Version 1.2, November 2002
3469
 
3470
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3471
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3472
 
3473
     Everyone is permitted to copy and distribute verbatim copies
3474
     of this license document, but changing it is not allowed.
3475
 
3476
  0. PREAMBLE
3477
 
3478
     The purpose of this License is to make a manual, textbook, or other
3479
     functional and useful document "free" in the sense of freedom: to
3480
     assure everyone the effective freedom to copy and redistribute it,
3481
     with or without modifying it, either commercially or
3482
     noncommercially.  Secondarily, this License preserves for the
3483
     author and publisher a way to get credit for their work, while not
3484
     being considered responsible for modifications made by others.
3485
 
3486
     This License is a kind of "copyleft", which means that derivative
3487
     works of the document must themselves be free in the same sense.
3488
     It complements the GNU General Public License, which is a copyleft
3489
     license designed for free software.
3490
 
3491
     We have designed this License in order to use it for manuals for
3492
     free software, because free software needs free documentation: a
3493
     free program should come with manuals providing the same freedoms
3494
     that the software does.  But this License is not limited to
3495
     software manuals; it can be used for any textual work, regardless
3496
     of subject matter or whether it is published as a printed book.
3497
     We recommend this License principally for works whose purpose is
3498
     instruction or reference.
3499
 
3500
  1. APPLICABILITY AND DEFINITIONS
3501
 
3502
     This License applies to any manual or other work, in any medium,
3503
     that contains a notice placed by the copyright holder saying it
3504
     can be distributed under the terms of this License.  Such a notice
3505
     grants a world-wide, royalty-free license, unlimited in duration,
3506
     to use that work under the conditions stated herein.  The
3507
     "Document", below, refers to any such manual or work.  Any member
3508
     of the public is a licensee, and is addressed as "you".  You
3509
     accept the license if you copy, modify or distribute the work in a
3510
     way requiring permission under copyright law.
3511
 
3512
     A "Modified Version" of the Document means any work containing the
3513
     Document or a portion of it, either copied verbatim, or with
3514
     modifications and/or translated into another language.
3515
 
3516
     A "Secondary Section" is a named appendix or a front-matter section
3517
     of the Document that deals exclusively with the relationship of the
3518
     publishers or authors of the Document to the Document's overall
3519
     subject (or to related matters) and contains nothing that could
3520
     fall directly within that overall subject.  (Thus, if the Document
3521
     is in part a textbook of mathematics, a Secondary Section may not
3522
     explain any mathematics.)  The relationship could be a matter of
3523
     historical connection with the subject or with related matters, or
3524
     of legal, commercial, philosophical, ethical or political position
3525
     regarding them.
3526
 
3527
     The "Invariant Sections" are certain Secondary Sections whose
3528
     titles are designated, as being those of Invariant Sections, in
3529
     the notice that says that the Document is released under this
3530
     License.  If a section does not fit the above definition of
3531
     Secondary then it is not allowed to be designated as Invariant.
3532
     The Document may contain zero Invariant Sections.  If the Document
3533
     does not identify any Invariant Sections then there are none.
3534
 
3535
     The "Cover Texts" are certain short passages of text that are
3536
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3537
     that says that the Document is released under this License.  A
3538
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3539
     be at most 25 words.
3540
 
3541
     A "Transparent" copy of the Document means a machine-readable copy,
3542
     represented in a format whose specification is available to the
3543
     general public, that is suitable for revising the document
3544
     straightforwardly with generic text editors or (for images
3545
     composed of pixels) generic paint programs or (for drawings) some
3546
     widely available drawing editor, and that is suitable for input to
3547
     text formatters or for automatic translation to a variety of
3548
     formats suitable for input to text formatters.  A copy made in an
3549
     otherwise Transparent file format whose markup, or absence of
3550
     markup, has been arranged to thwart or discourage subsequent
3551
     modification by readers is not Transparent.  An image format is
3552
     not Transparent if used for any substantial amount of text.  A
3553
     copy that is not "Transparent" is called "Opaque".
3554
 
3555
     Examples of suitable formats for Transparent copies include plain
3556
     ASCII without markup, Texinfo input format, LaTeX input format,
3557
     SGML or XML using a publicly available DTD, and
3558
     standard-conforming simple HTML, PostScript or PDF designed for
3559
     human modification.  Examples of transparent image formats include
3560
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3561
     can be read and edited only by proprietary word processors, SGML or
3562
     XML for which the DTD and/or processing tools are not generally
3563
     available, and the machine-generated HTML, PostScript or PDF
3564
     produced by some word processors for output purposes only.
3565
 
3566
     The "Title Page" means, for a printed book, the title page itself,
3567
     plus such following pages as are needed to hold, legibly, the
3568
     material this License requires to appear in the title page.  For
3569
     works in formats which do not have any title page as such, "Title
3570
     Page" means the text near the most prominent appearance of the
3571
     work's title, preceding the beginning of the body of the text.
3572
 
3573
     A section "Entitled XYZ" means a named subunit of the Document
3574
     whose title either is precisely XYZ or contains XYZ in parentheses
3575
     following text that translates XYZ in another language.  (Here XYZ
3576
     stands for a specific section name mentioned below, such as
3577
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3578
     To "Preserve the Title" of such a section when you modify the
3579
     Document means that it remains a section "Entitled XYZ" according
3580
     to this definition.
3581
 
3582
     The Document may include Warranty Disclaimers next to the notice
3583
     which states that this License applies to the Document.  These
3584
     Warranty Disclaimers are considered to be included by reference in
3585
     this License, but only as regards disclaiming warranties: any other
3586
     implication that these Warranty Disclaimers may have is void and
3587
     has no effect on the meaning of this License.
3588
 
3589
  2. VERBATIM COPYING
3590
 
3591
     You may copy and distribute the Document in any medium, either
3592
     commercially or noncommercially, provided that this License, the
3593
     copyright notices, and the license notice saying this License
3594
     applies to the Document are reproduced in all copies, and that you
3595
     add no other conditions whatsoever to those of this License.  You
3596
     may not use technical measures to obstruct or control the reading
3597
     or further copying of the copies you make or distribute.  However,
3598
     you may accept compensation in exchange for copies.  If you
3599
     distribute a large enough number of copies you must also follow
3600
     the conditions in section 3.
3601
 
3602
     You may also lend copies, under the same conditions stated above,
3603
     and you may publicly display copies.
3604
 
3605
  3. COPYING IN QUANTITY
3606
 
3607
     If you publish printed copies (or copies in media that commonly
3608
     have printed covers) of the Document, numbering more than 100, and
3609
     the Document's license notice requires Cover Texts, you must
3610
     enclose the copies in covers that carry, clearly and legibly, all
3611
     these Cover Texts: Front-Cover Texts on the front cover, and
3612
     Back-Cover Texts on the back cover.  Both covers must also clearly
3613
     and legibly identify you as the publisher of these copies.  The
3614
     front cover must present the full title with all words of the
3615
     title equally prominent and visible.  You may add other material
3616
     on the covers in addition.  Copying with changes limited to the
3617
     covers, as long as they preserve the title of the Document and
3618
     satisfy these conditions, can be treated as verbatim copying in
3619
     other respects.
3620
 
3621
     If the required texts for either cover are too voluminous to fit
3622
     legibly, you should put the first ones listed (as many as fit
3623
     reasonably) on the actual cover, and continue the rest onto
3624
     adjacent pages.
3625
 
3626
     If you publish or distribute Opaque copies of the Document
3627
     numbering more than 100, you must either include a
3628
     machine-readable Transparent copy along with each Opaque copy, or
3629
     state in or with each Opaque copy a computer-network location from
3630
     which the general network-using public has access to download
3631
     using public-standard network protocols a complete Transparent
3632
     copy of the Document, free of added material.  If you use the
3633
     latter option, you must take reasonably prudent steps, when you
3634
     begin distribution of Opaque copies in quantity, to ensure that
3635
     this Transparent copy will remain thus accessible at the stated
3636
     location until at least one year after the last time you
3637
     distribute an Opaque copy (directly or through your agents or
3638
     retailers) of that edition to the public.
3639
 
3640
     It is requested, but not required, that you contact the authors of
3641
     the Document well before redistributing any large number of
3642
     copies, to give them a chance to provide you with an updated
3643
     version of the Document.
3644
 
3645
  4. MODIFICATIONS
3646
 
3647
     You may copy and distribute a Modified Version of the Document
3648
     under the conditions of sections 2 and 3 above, provided that you
3649
     release the Modified Version under precisely this License, with
3650
     the Modified Version filling the role of the Document, thus
3651
     licensing distribution and modification of the Modified Version to
3652
     whoever possesses a copy of it.  In addition, you must do these
3653
     things in the Modified Version:
3654
 
3655
       A. Use in the Title Page (and on the covers, if any) a title
3656
          distinct from that of the Document, and from those of
3657
          previous versions (which should, if there were any, be listed
3658
          in the History section of the Document).  You may use the
3659
          same title as a previous version if the original publisher of
3660
          that version gives permission.
3661
 
3662
       B. List on the Title Page, as authors, one or more persons or
3663
          entities responsible for authorship of the modifications in
3664
          the Modified Version, together with at least five of the
3665
          principal authors of the Document (all of its principal
3666
          authors, if it has fewer than five), unless they release you
3667
          from this requirement.
3668
 
3669
       C. State on the Title page the name of the publisher of the
3670
          Modified Version, as the publisher.
3671
 
3672
       D. Preserve all the copyright notices of the Document.
3673
 
3674
       E. Add an appropriate copyright notice for your modifications
3675
          adjacent to the other copyright notices.
3676
 
3677
       F. Include, immediately after the copyright notices, a license
3678
          notice giving the public permission to use the Modified
3679
          Version under the terms of this License, in the form shown in
3680
          the Addendum below.
3681
 
3682
       G. Preserve in that license notice the full lists of Invariant
3683
          Sections and required Cover Texts given in the Document's
3684
          license notice.
3685
 
3686
       H. Include an unaltered copy of this License.
3687
 
3688
       I. Preserve the section Entitled "History", Preserve its Title,
3689
          and add to it an item stating at least the title, year, new
3690
          authors, and publisher of the Modified Version as given on
3691
          the Title Page.  If there is no section Entitled "History" in
3692
          the Document, create one stating the title, year, authors,
3693
          and publisher of the Document as given on its Title Page,
3694
          then add an item describing the Modified Version as stated in
3695
          the previous sentence.
3696
 
3697
       J. Preserve the network location, if any, given in the Document
3698
          for public access to a Transparent copy of the Document, and
3699
          likewise the network locations given in the Document for
3700
          previous versions it was based on.  These may be placed in
3701
          the "History" section.  You may omit a network location for a
3702
          work that was published at least four years before the
3703
          Document itself, or if the original publisher of the version
3704
          it refers to gives permission.
3705
 
3706
       K. For any section Entitled "Acknowledgements" or "Dedications",
3707
          Preserve the Title of the section, and preserve in the
3708
          section all the substance and tone of each of the contributor
3709
          acknowledgements and/or dedications given therein.
3710
 
3711
       L. Preserve all the Invariant Sections of the Document,
3712
          unaltered in their text and in their titles.  Section numbers
3713
          or the equivalent are not considered part of the section
3714
          titles.
3715
 
3716
       M. Delete any section Entitled "Endorsements".  Such a section
3717
          may not be included in the Modified Version.
3718
 
3719
       N. Do not retitle any existing section to be Entitled
3720
          "Endorsements" or to conflict in title with any Invariant
3721
          Section.
3722
 
3723
       O. Preserve any Warranty Disclaimers.
3724
 
3725
     If the Modified Version includes new front-matter sections or
3726
     appendices that qualify as Secondary Sections and contain no
3727
     material copied from the Document, you may at your option
3728
     designate some or all of these sections as invariant.  To do this,
3729
     add their titles to the list of Invariant Sections in the Modified
3730
     Version's license notice.  These titles must be distinct from any
3731
     other section titles.
3732
 
3733
     You may add a section Entitled "Endorsements", provided it contains
3734
     nothing but endorsements of your Modified Version by various
3735
     parties--for example, statements of peer review or that the text
3736
     has been approved by an organization as the authoritative
3737
     definition of a standard.
3738
 
3739
     You may add a passage of up to five words as a Front-Cover Text,
3740
     and a passage of up to 25 words as a Back-Cover Text, to the end
3741
     of the list of Cover Texts in the Modified Version.  Only one
3742
     passage of Front-Cover Text and one of Back-Cover Text may be
3743
     added by (or through arrangements made by) any one entity.  If the
3744
     Document already includes a cover text for the same cover,
3745
     previously added by you or by arrangement made by the same entity
3746
     you are acting on behalf of, you may not add another; but you may
3747
     replace the old one, on explicit permission from the previous
3748
     publisher that added the old one.
3749
 
3750
     The author(s) and publisher(s) of the Document do not by this
3751
     License give permission to use their names for publicity for or to
3752
     assert or imply endorsement of any Modified Version.
3753
 
3754
  5. COMBINING DOCUMENTS
3755
 
3756
     You may combine the Document with other documents released under
3757
     this License, under the terms defined in section 4 above for
3758
     modified versions, provided that you include in the combination
3759
     all of the Invariant Sections of all of the original documents,
3760
     unmodified, and list them all as Invariant Sections of your
3761
     combined work in its license notice, and that you preserve all
3762
     their Warranty Disclaimers.
3763
 
3764
     The combined work need only contain one copy of this License, and
3765
     multiple identical Invariant Sections may be replaced with a single
3766
     copy.  If there are multiple Invariant Sections with the same name
3767
     but different contents, make the title of each such section unique
3768
     by adding at the end of it, in parentheses, the name of the
3769
     original author or publisher of that section if known, or else a
3770
     unique number.  Make the same adjustment to the section titles in
3771
     the list of Invariant Sections in the license notice of the
3772
     combined work.
3773
 
3774
     In the combination, you must combine any sections Entitled
3775
     "History" in the various original documents, forming one section
3776
     Entitled "History"; likewise combine any sections Entitled
3777
     "Acknowledgements", and any sections Entitled "Dedications".  You
3778
     must delete all sections Entitled "Endorsements."
3779
 
3780
  6. COLLECTIONS OF DOCUMENTS
3781
 
3782
     You may make a collection consisting of the Document and other
3783
     documents released under this License, and replace the individual
3784
     copies of this License in the various documents with a single copy
3785
     that is included in the collection, provided that you follow the
3786
     rules of this License for verbatim copying of each of the
3787
     documents in all other respects.
3788
 
3789
     You may extract a single document from such a collection, and
3790
     distribute it individually under this License, provided you insert
3791
     a copy of this License into the extracted document, and follow
3792
     this License in all other respects regarding verbatim copying of
3793
     that document.
3794
 
3795
  7. AGGREGATION WITH INDEPENDENT WORKS
3796
 
3797
     A compilation of the Document or its derivatives with other
3798
     separate and independent documents or works, in or on a volume of
3799
     a storage or distribution medium, is called an "aggregate" if the
3800
     copyright resulting from the compilation is not used to limit the
3801
     legal rights of the compilation's users beyond what the individual
3802
     works permit.  When the Document is included in an aggregate, this
3803
     License does not apply to the other works in the aggregate which
3804
     are not themselves derivative works of the Document.
3805
 
3806
     If the Cover Text requirement of section 3 is applicable to these
3807
     copies of the Document, then if the Document is less than one half
3808
     of the entire aggregate, the Document's Cover Texts may be placed
3809
     on covers that bracket the Document within the aggregate, or the
3810
     electronic equivalent of covers if the Document is in electronic
3811
     form.  Otherwise they must appear on printed covers that bracket
3812
     the whole aggregate.
3813
 
3814
  8. TRANSLATION
3815
 
3816
     Translation is considered a kind of modification, so you may
3817
     distribute translations of the Document under the terms of section
3818
     4.  Replacing Invariant Sections with translations requires special
3819
     permission from their copyright holders, but you may include
3820
     translations of some or all Invariant Sections in addition to the
3821
     original versions of these Invariant Sections.  You may include a
3822
     translation of this License, and all the license notices in the
3823
     Document, and any Warranty Disclaimers, provided that you also
3824
     include the original English version of this License and the
3825
     original versions of those notices and disclaimers.  In case of a
3826
     disagreement between the translation and the original version of
3827
     this License or a notice or disclaimer, the original version will
3828
     prevail.
3829
 
3830
     If a section in the Document is Entitled "Acknowledgements",
3831
     "Dedications", or "History", the requirement (section 4) to
3832
     Preserve its Title (section 1) will typically require changing the
3833
     actual title.
3834
 
3835
  9. TERMINATION
3836
 
3837
     You may not copy, modify, sublicense, or distribute the Document
3838
     except as expressly provided for under this License.  Any other
3839
     attempt to copy, modify, sublicense or distribute the Document is
3840
     void, and will automatically terminate your rights under this
3841
     License.  However, parties who have received copies, or rights,
3842
     from you under this License will not have their licenses
3843
     terminated so long as such parties remain in full compliance.
3844
 
3845
 10. FUTURE REVISIONS OF THIS LICENSE
3846
 
3847
     The Free Software Foundation may publish new, revised versions of
3848
     the GNU Free Documentation License from time to time.  Such new
3849
     versions will be similar in spirit to the present version, but may
3850
     differ in detail to address new problems or concerns.  See
3851
     `http://www.gnu.org/copyleft/'.
3852
 
3853
     Each version of the License is given a distinguishing version
3854
     number.  If the Document specifies that a particular numbered
3855
     version of this License "or any later version" applies to it, you
3856
     have the option of following the terms and conditions either of
3857
     that specified version or of any later version that has been
3858
     published (not as a draft) by the Free Software Foundation.  If
3859
     the Document does not specify a version number of this License,
3860
     you may choose any version ever published (not as a draft) by the
3861
     Free Software Foundation.
3862
 
3863
ADDENDUM: How to use this License for your documents
3864
====================================================
3865
 
3866
To use this License in a document you have written, include a copy of
3867
the License in the document and put the following copyright and license
3868
notices just after the title page:
3869
 
3870
       Copyright (C)  YEAR  YOUR NAME.
3871
       Permission is granted to copy, distribute and/or modify this document
3872
       under the terms of the GNU Free Documentation License, Version 1.2
3873
       or any later version published by the Free Software Foundation;
3874
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3875
       Texts.  A copy of the license is included in the section entitled ``GNU
3876
       Free Documentation License''.
3877
 
3878
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3879
replace the "with...Texts." line with this:
3880
 
3881
         with the Invariant Sections being LIST THEIR TITLES, with
3882
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3883
         being LIST.
3884
 
3885
If you have Invariant Sections without Cover Texts, or some other
3886
combination of the three, merge those two alternatives to suit the
3887
situation.
3888
 
3889
If your document contains nontrivial examples of program code, we
3890
recommend releasing these examples in parallel under your choice of
3891
free software license, such as the GNU General Public License, to
3892
permit their use in free software.
3893
 
3894

3895
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3896
 
3897
Index
3898
*****
3899
 
3900
 
3901
* Menu:
3902
3903
* --cumulative:                          Profiling Utility.   (line  26)
3904
* --debug-config:                        Standalone Simulator.
3905 472 jeremybenn
                                                              (line  99)
3906 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3907 552 julius
                                                              (line  98)
3908 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3909 552 julius
                                                              (line 111)
3910 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3911 552 julius
                                                              (line  91)
3912 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3913 552 julius
                                                              (line  52)
3914 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3915 552 julius
                                                              (line 126)
3916 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3917 104 jeremybenn
                                                              (line  30)
3918 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3919 552 julius
                                                              (line  85)
3920 127 jeremybenn
* --disable-unsigned-xori:               Configuring the Build.
3921 552 julius
                                                              (line  62)
3922 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3923 552 julius
                                                              (line  97)
3924 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3925 552 julius
                                                              (line 110)
3926 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3927 552 julius
                                                              (line  90)
3928 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3929 552 julius
                                                              (line  51)
3930 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3931 552 julius
                                                              (line  36)
3932 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3933 472 jeremybenn
                                                              (line 133)
3934 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3935 552 julius
                                                              (line 125)
3936 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3937 472 jeremybenn
                                                              (line 130)
3938 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3939 104 jeremybenn
                                                              (line  29)
3940 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3941 552 julius
                                                              (line  84)
3942 127 jeremybenn
* --enable-unsigned-xori:                Configuring the Build.
3943 552 julius
                                                              (line  61)
3944 19 jeremybenn
* --file:                                Standalone Simulator.
3945 472 jeremybenn
                                                              (line  57)
3946 19 jeremybenn
* --filename:                            Memory Profiling Utility.
3947
                                                              (line  51)
3948
* --generate:                            Profiling Utility.   (line  34)
3949
* --group:                               Memory Profiling Utility.
3950
                                                              (line  47)
3951
* --help:                                Standalone Simulator.
3952 346 jeremybenn
                                                              (line  21)
3953 19 jeremybenn
* --help (memory profiling utility):     Memory Profiling Utility.
3954
                                                              (line  22)
3955
* --help (profiling utility):            Profiling Utility.   (line  22)
3956
* --interactive:                         Standalone Simulator.
3957 346 jeremybenn
                                                              (line  25)
3958
* --memory:                              Standalone Simulator.
3959 472 jeremybenn
                                                              (line  83)
3960 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3961
                                                              (line  26)
3962
* --nosrv:                               Standalone Simulator.
3963 472 jeremybenn
                                                              (line  65)
3964 346 jeremybenn
* --quiet <1>:                           Profiling Utility.   (line  30)
3965
* --quiet:                               Standalone Simulator.
3966
                                                              (line  29)
3967
* --report-memory-errors:                Standalone Simulator.
3968 472 jeremybenn
                                                              (line 104)
3969 19 jeremybenn
* --srv:                                 Standalone Simulator.
3970 472 jeremybenn
                                                              (line  73)
3971 19 jeremybenn
* --strict-npc:                          Standalone Simulator.
3972 472 jeremybenn
                                                              (line 113)
3973
* --trace <1>:                           Trace Generation.    (line  14)
3974 420 jeremybenn
* --trace:                               Standalone Simulator.
3975
                                                              (line  39)
3976 472 jeremybenn
* --trace-physical <1>:                  Trace Generation.    (line  44)
3977
* --trace-physical:                      Standalone Simulator.
3978
                                                              (line  44)
3979
* --trace-virtual <1>:                   Trace Generation.    (line  44)
3980
* --trace-virtual:                       Standalone Simulator.
3981
                                                              (line  44)
3982 346 jeremybenn
* --verbose:                             Standalone Simulator.
3983
                                                              (line  33)
3984 19 jeremybenn
* --version:                             Standalone Simulator.
3985 346 jeremybenn
                                                              (line  17)
3986 19 jeremybenn
* --version (memory profiling utility):  Memory Profiling Utility.
3987
                                                              (line  17)
3988
* --version (profiling utility):         Profiling Utility.   (line  17)
3989
* -c:                                    Profiling Utility.   (line  26)
3990
* -d:                                    Standalone Simulator.
3991 472 jeremybenn
                                                              (line  99)
3992 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3993
                                                              (line  51)
3994
* -f:                                    Standalone Simulator.
3995 472 jeremybenn
                                                              (line  57)
3996 346 jeremybenn
* -g <1>:                                Memory Profiling Utility.
3997 19 jeremybenn
                                                              (line  47)
3998 346 jeremybenn
* -g:                                    Profiling Utility.   (line  34)
3999 19 jeremybenn
* -h:                                    Standalone Simulator.
4000 346 jeremybenn
                                                              (line  21)
4001 19 jeremybenn
* -h (memory profiling utility):         Memory Profiling Utility.
4002
                                                              (line  22)
4003
* -h (profiling utility):                Profiling Utility.   (line  22)
4004
* -i:                                    Standalone Simulator.
4005 346 jeremybenn
                                                              (line  25)
4006
* -m <1>:                                Memory Profiling Utility.
4007 19 jeremybenn
                                                              (line  26)
4008 346 jeremybenn
* -m:                                    Standalone Simulator.
4009 472 jeremybenn
                                                              (line  83)
4010 346 jeremybenn
* -q <1>:                                Profiling Utility.   (line  30)
4011
* -q:                                    Standalone Simulator.
4012
                                                              (line  29)
4013 472 jeremybenn
* -t <1>:                                Trace Generation.    (line  14)
4014 420 jeremybenn
* -t:                                    Standalone Simulator.
4015
                                                              (line  39)
4016 346 jeremybenn
* -V:                                    Standalone Simulator.
4017
                                                              (line  33)
4018 19 jeremybenn
* -v:                                    Standalone Simulator.
4019 346 jeremybenn
                                                              (line  17)
4020 19 jeremybenn
* -v (memory profiling utility):         Memory Profiling Utility.
4021
                                                              (line  17)
4022
* -v (profiling utility):                Profiling Utility.   (line  17)
4023
* 0x00 UART VAPI sub-command (UART verification): Verification API.
4024
                                                              (line  49)
4025
* 0x01 UART VAPI sub-command (UART verification): Verification API.
4026
                                                              (line  55)
4027
* 0x02 UART VAPI sub-command (UART verification): Verification API.
4028
                                                              (line  59)
4029
* 0x03 UART VAPI sub-command (UART verification): Verification API.
4030
                                                              (line  62)
4031
* 0x04 UART VAPI sub-command (UART verification): Verification API.
4032
                                                              (line  66)
4033
* 16550 (UART configuration):            UART Configuration.  (line  73)
4034 82 jeremybenn
* all tests enabled:                     Configuring the Build.
4035 552 julius
                                                              (line  98)
4036 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
4037 552 julius
                                                              (line  91)
4038 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
4039
                                                              (line   6)
4040
* ATA/ATAPI device configuration:        Disc Interface Configuration.
4041 385 jeremybenn
                                                              (line  92)
4042 19 jeremybenn
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
4043
                                                              (line  32)
4044
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
4045 385 jeremybenn
                                                              (line  26)
4046 19 jeremybenn
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
4047
* baseaddr (Ethernet configuration):     Ethernet Configuration.
4048 440 jeremybenn
                                                              (line  23)
4049 19 jeremybenn
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
4050
                                                              (line  20)
4051
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
4052
                                                              (line  22)
4053
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
4054
* baseaddr (keyboard configuration):     Keyboard Configuration.
4055
                                                              (line  36)
4056
* baseaddr (memory configuration):       Memory Configuration.
4057 418 julius
                                                              (line  94)
4058 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
4059 385 jeremybenn
                                                              (line  55)
4060 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
4061
* baseaddr (VGA configuration):          Display Interface Configuration.
4062
                                                              (line  26)
4063
* blocksize (cache configuration):       Cache Configuration. (line  29)
4064
* BPB configuration:                     Branch Prediction Configuration.
4065
                                                              (line   6)
4066
* branch prediction configuration:       Branch Prediction Configuration.
4067
                                                              (line   6)
4068
* break (Interactive CLI):               Interactive Command Line.
4069
                                                              (line  57)
4070
* breakpoint list (Interactive CLI):     Interactive Command Line.
4071
                                                              (line  60)
4072
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
4073
                                                              (line  57)
4074
* breaks (Interactive CLI):              Interactive Command Line.
4075
                                                              (line  60)
4076 440 jeremybenn
* bridge setup:                          Establishing a Bridge.
4077
                                                              (line   6)
4078 19 jeremybenn
* btic (branch prediction configuration): Branch Prediction Configuration.
4079
                                                              (line  19)
4080 440 jeremybenn
* BusyBox and Ethernet:                  Networking from OpenRISC Linux and BusyBox.
4081
                                                              (line   6)
4082 19 jeremybenn
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
4083
                                                              (line  48)
4084
* cache configuration:                   Cache Configuration. (line   6)
4085 346 jeremybenn
* calling_convention (CUC configuration): CUC Configuration.  (line  37)
4086 19 jeremybenn
* ce (memory configuration):             Memory Configuration.
4087 418 julius
                                                              (line 124)
4088 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
4089
* channel (UART configuration):          UART Configuration.  (line  29)
4090
* clear breakpoint (Interactive CLI):    Interactive Command Line.
4091
                                                              (line  57)
4092 432 jeremybenn
* clear_interrupt:                       Concepts.            (line  20)
4093 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
4094 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
4095
                                                              (line  54)
4096
* command line for Or1ksim standalone use: Standalone Simulator.
4097
                                                              (line   6)
4098
* complex model:                         Configuring the Build.
4099 552 julius
                                                              (line  36)
4100 19 jeremybenn
* config:                                Global Data Structures.
4101
                                                              (line   7)
4102
* config.bpb:                            Global Data Structures.
4103
                                                              (line  37)
4104
* config.cpu:                            Global Data Structures.
4105
                                                              (line  22)
4106
* config.cuc:                            Global Data Structures.
4107
                                                              (line  18)
4108
* config.dc:                             Global Data Structures.
4109
                                                              (line  25)
4110
* config.debug:                          Global Data Structures.
4111
                                                              (line  40)
4112
* config.pic:                            Global Data Structures.
4113
                                                              (line  33)
4114
* config.pm:                             Global Data Structures.
4115
                                                              (line  29)
4116
* config.sim:                            Global Data Structures.
4117
                                                              (line  11)
4118
* config.vapi:                           Global Data Structures.
4119
                                                              (line  14)
4120
* configuration dynamic structure:       Global Data Structures.
4121
                                                              (line  49)
4122
* configuration file structure:          Configuration File Format.
4123
                                                              (line   6)
4124
* configuration global structure:        Global Data Structures.
4125
                                                              (line   7)
4126
* configuration info (Interactive CLI):  Interactive Command Line.
4127
                                                              (line 119)
4128
* configuration of generic peripherals:  Generic Peripheral Configuration.
4129
                                                              (line   6)
4130
* configuration parameter setting (Interactive CLI): Interactive Command Line.
4131
                                                              (line 146)
4132
* configuring branch prediction:         Branch Prediction Configuration.
4133
                                                              (line   6)
4134
* configuring data & instruction caches: Cache Configuration. (line   6)
4135
* configuring data & instruction MMUs:   Memory Management Configuration.
4136
                                                              (line   6)
4137
* configuring DMA:                       DMA Configuration.   (line   6)
4138
* configuring memory:                    Memory Configuration.
4139
                                                              (line   6)
4140
* configuring Or1ksim:                   Configuration.       (line   6)
4141
* configuring power management:          Power Management Configuration.
4142
                                                              (line   6)
4143
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
4144
                                                              (line   6)
4145
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
4146
* configuring the CPU:                   CPU Configuration.   (line   6)
4147
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
4148
                                                              (line   6)
4149
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
4150
                                                              (line   6)
4151
* configuring the Ethernet interface:    Ethernet Configuration.
4152
                                                              (line   6)
4153 440 jeremybenn
* configuring the Ethernet TUN/TAP interface: Ethernet TUN/TAP Interface.
4154
                                                              (line   6)
4155 19 jeremybenn
* configuring the frame buffer:          Frame Buffer Configuration.
4156
                                                              (line   6)
4157
* configuring the GPIO:                  GPIO Configuration.  (line   6)
4158
* configuring the interrupt controller:  Interrupt Configuration.
4159
                                                              (line   6)
4160
* configuring the keyboard interface:    Keyboard Configuration.
4161
                                                              (line   6)
4162
* configuring the memory controller:     Memory Controller Configuration.
4163
                                                              (line   6)
4164 556 julius
* configuring the performance counters unit: Performance Counters Configuration.
4165
                                                              (line   6)
4166 19 jeremybenn
* configuring the processor:             CPU Configuration.   (line   6)
4167
* configuring the PS2 interface:         Keyboard Configuration.
4168
                                                              (line   6)
4169
* configuring the UART:                  UART Configuration.  (line   6)
4170
* configuring the Verification API (VAPI): Verification API Configuration.
4171
                                                              (line   6)
4172
* configuring the VGA interface:         Display Interface Configuration.
4173
                                                              (line   6)
4174
* copying memory (Interactive CLI):      Interactive Command Line.
4175
                                                              (line  54)
4176
* CPU configuration:                     CPU Configuration.   (line   6)
4177
* CUC configuration:                     CUC Configuration.   (line   6)
4178
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
4179
                                                              (line 162)
4180
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
4181
* data cache configuration:              Cache Configuration. (line   6)
4182
* data MMU configuration:                Memory Management Configuration.
4183
                                                              (line   6)
4184
* DCGE (power management register):      Power Management Configuration.
4185
                                                              (line  21)
4186
* debug (Interactive CLI):               Interactive Command Line.
4187 346 jeremybenn
                                                              (line 151)
4188 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
4189
* debug channel toggle (Interactive CLI): Interactive Command Line.
4190
                                                              (line 141)
4191
* debug interface configuration:         Debug Interface Configuration.
4192
                                                              (line   6)
4193
* debug mode toggle (Interactive CLI):   Interactive Command Line.
4194
                                                              (line 151)
4195
* debug unit configuration:              Debug Interface Configuration.
4196
                                                              (line   6)
4197
* Debug Unit verification (VAPI):        Verification API.    (line  34)
4198
* debugging enabled (Argtable2):         Configuring the Build.
4199 552 julius
                                                              (line  91)
4200 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
4201
* DejaGnu configuration:                 Regression Testing.  (line  21)
4202
* DejaGNU tests directories:             Regression Testing.  (line  50)
4203
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
4204 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
4205 418 julius
                                                              (line 144)
4206 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
4207 418 julius
                                                              (line 150)
4208 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
4209 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
4210 385 jeremybenn
                                                              (line  40)
4211 19 jeremybenn
* disassemble (Interactive CLI):         Interactive Command Line.
4212
                                                              (line  41)
4213
* disc interface configuration:          Disc Interface Configuration.
4214
                                                              (line   6)
4215
* disc interface device configuration:   Disc Interface Configuration.
4216 385 jeremybenn
                                                              (line  92)
4217 19 jeremybenn
* display interface configuration:       Display Interface Configuration.
4218
                                                              (line   6)
4219
* displaying memory (Interactive CLI):   Interactive Command Line.
4220
                                                              (line  31)
4221
* displaying registers (Interactive CLI): Interactive Command Line.
4222
                                                              (line  14)
4223
* dm (Interactive CLI):                  Interactive Command Line.
4224
                                                              (line  31)
4225
* dma (Ethernet configuration):          Ethernet Configuration.
4226 440 jeremybenn
                                                              (line  34)
4227 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
4228
* DMA verification (VAPI):               Verification API.    (line  73)
4229
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
4230 385 jeremybenn
                                                              (line  74)
4231 19 jeremybenn
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4232 385 jeremybenn
                                                              (line  75)
4233 19 jeremybenn
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
4234 385 jeremybenn
                                                              (line  73)
4235 19 jeremybenn
* DME (power management register):       Power Management Configuration.
4236
                                                              (line  15)
4237
* DMMU configuration:                    Memory Management Configuration.
4238
                                                              (line   6)
4239
* doze mode (power management register): Power Management Configuration.
4240
                                                              (line  15)
4241 451 jeremybenn
* dummy_crc (Ethernet configuration):    Ethernet Configuration.
4242
                                                              (line 104)
4243 19 jeremybenn
* dv (Interactive CLI):                  Interactive Command Line.
4244
                                                              (line 124)
4245
* dynamic clock gating (power management register): Power Management Configuration.
4246
                                                              (line  21)
4247
* dynamic ports, use of:                 Verification API Configuration.
4248
                                                              (line  23)
4249
* edge_trigger (interrupt controller):   Interrupt Configuration.
4250
                                                              (line  16)
4251 346 jeremybenn
* enable_bursts (CUC configuration):     CUC Configuration.   (line  41)
4252 19 jeremybenn
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
4253 385 jeremybenn
                                                              (line  22)
4254 19 jeremybenn
* enabled (branch prediction configuration): Branch Prediction Configuration.
4255
                                                              (line  15)
4256
* enabled (cache configuration):         Cache Configuration. (line  11)
4257
* enabled (debug interface configuration): Debug Interface Configuration.
4258
                                                              (line  11)
4259
* enabled (DMA configuration):           DMA Configuration.   (line  20)
4260
* enabled (Ethernet configuration):      Ethernet Configuration.
4261 440 jeremybenn
                                                              (line  19)
4262 19 jeremybenn
* enabled (frame buffer configuration):  Frame Buffer Configuration.
4263
                                                              (line  16)
4264
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
4265
                                                              (line  18)
4266
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
4267
* enabled (interrupt controller):        Interrupt Configuration.
4268
                                                              (line  12)
4269
* enabled (keyboard configuration):      Keyboard Configuration.
4270
                                                              (line  32)
4271
* enabled (memory controller configuration): Memory Controller Configuration.
4272 385 jeremybenn
                                                              (line  44)
4273 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
4274
                                                              (line  12)
4275 556 julius
* enabled (performance counters unit configuration): Performance Counters Configuration.
4276
                                                              (line  11)
4277 19 jeremybenn
* enabled (power management configuration): Power Management Configuration.
4278
                                                              (line  35)
4279
* enabled (UART configuration):          UART Configuration.  (line  18)
4280
* enabled (verification API configuration): Verification API Configuration.
4281
                                                              (line  15)
4282
* enabled (VGA configuration):           Display Interface Configuration.
4283
                                                              (line  22)
4284
* enabling Ethernet via socket:          Configuring the Build.
4285 552 julius
                                                              (line  52)
4286 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
4287
                                                              (line  32)
4288
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
4289
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
4290 440 jeremybenn
* Ethernet bridge setup:                 Establishing a Bridge.
4291
                                                              (line   6)
4292 19 jeremybenn
* Ethernet configuration:                Ethernet Configuration.
4293
                                                              (line   6)
4294
* Ethernet verification (VAPI):          Verification API.    (line  78)
4295
* Ethernet via socket, enabling:         Configuring the Build.
4296 552 julius
                                                              (line  52)
4297 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
4298 552 julius
                                                              (line  62)
4299 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
4300
                                                              (line 103)
4301
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
4302
                                                              (line 111)
4303 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
4304
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
4305
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
4306 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
4307 82 jeremybenn
                                                              (line  97)
4308 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
4309 82 jeremybenn
                                                              (line  93)
4310 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
4311 82 jeremybenn
                                                              (line  86)
4312
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
4313 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
4314 82 jeremybenn
                                                              (line  58)
4315 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
4316 82 jeremybenn
                                                              (line  62)
4317 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
4318 82 jeremybenn
                                                              (line  69)
4319 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
4320 82 jeremybenn
                                                              (line  74)
4321 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
4322
                                                              (line  23)
4323
* execution history (Interactive CLI):   Interactive Command Line.
4324
                                                              (line  67)
4325
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
4326 385 jeremybenn
                                                              (line 108)
4327 19 jeremybenn
* file (keyboard configuration):         Keyboard Configuration.
4328
                                                              (line  51)
4329
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
4330 82 jeremybenn
                                                              (line  36)
4331 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
4332
                                                              (line  47)
4333 440 jeremybenn
* firewall with Ethernet bridge and TAP/TUN: Opening the Firewall.
4334
                                                              (line   6)
4335 19 jeremybenn
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
4336 385 jeremybenn
                                                              (line 121)
4337 19 jeremybenn
* flag setting by instructions:          Configuring the Build.
4338 552 julius
                                                              (line 111)
4339 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
4340
                                                              (line   6)
4341
* generic peripheral configuration:      Generic Peripheral Configuration.
4342
                                                              (line   6)
4343
* GPIO configuration:                    GPIO Configuration.  (line   6)
4344
* GPIO verification (VAPI):              Verification API.    (line  88)
4345
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
4346
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
4347
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
4348
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
4349
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
4350
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
4351
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
4352 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
4353 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
4354 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
4355 385 jeremybenn
                                                              (line 125)
4356 19 jeremybenn
* help (Interactive CLI):                Interactive Command Line.
4357
                                                              (line 170)
4358
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
4359
                                                              (line 133)
4360
* hide_device_id (verification API configuration): Verification API Configuration.
4361
                                                              (line  36)
4362
* hist (Interactive CLI):                Interactive Command Line.
4363
                                                              (line  67)
4364 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
4365 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
4366
                                                              (line  67)
4367
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
4368
                                                              (line  33)
4369
* hitdelay (instruction cache configuration): Cache Configuration.
4370
                                                              (line  38)
4371
* hitdelay (MMU configuration):          Memory Management Configuration.
4372
                                                              (line  51)
4373 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
4374 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
4375
                                                              (line  49)
4376
* IMMU configuration:                    Memory Management Configuration.
4377
                                                              (line   6)
4378
* index (memory controller configuration): Memory Controller Configuration.
4379 385 jeremybenn
                                                              (line  77)
4380 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
4381
                                                              (line 119)
4382
* installing Or1ksim:                    Installation.        (line   6)
4383
* instruction cache configuration:       Cache Configuration. (line   6)
4384
* instruction MMU configuration:         Memory Management Configuration.
4385
                                                              (line   6)
4386
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
4387
* instruction profiling utility (Interactive CLI): Interactive Command Line.
4388
                                                              (line 178)
4389
* internal debugging:                    Internal Debugging.  (line   6)
4390
* interrupt controller configuration:    Interrupt Configuration.
4391
                                                              (line   6)
4392 432 jeremybenn
* interrupts:                            Concepts.            (line  20)
4393 19 jeremybenn
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
4394 385 jeremybenn
                                                              (line  36)
4395 19 jeremybenn
* irq (DMA configuration):               DMA Configuration.   (line  34)
4396
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
4397
* irq (keyboard configuration):          Keyboard Configuration.
4398
                                                              (line  47)
4399
* irq (UART configuration):              UART Configuration.  (line  70)
4400
* irq (VGA configuration):               Display Interface Configuration.
4401
                                                              (line  37)
4402
* jitter (UART configuration):           UART Configuration.  (line  78)
4403
* keyboard configuration:                Keyboard Configuration.
4404
                                                              (line   6)
4405 460 jeremybenn
* l.nop 0:                               l.nop Support.       (line  12)
4406
* l.nop 1 (end simulation):              l.nop Support.       (line  15)
4407 483 jeremybenn
* l.nop 10 (return a random number):     l.nop Support.       (line  51)
4408
* l.nop 11 (return a non-zero value):    l.nop Support.       (line  62)
4409 460 jeremybenn
* l.nop 2 (report):                      l.nop Support.       (line  19)
4410
* l.nop 3 (printf, now obsolete):        l.nop Support.       (line  22)
4411
* l.nop 4 (putc):                        l.nop Support.       (line  29)
4412
* l.nop 5 (reset statistics counters):   l.nop Support.       (line  34)
4413
* l.nop 6 (get clock ticks):             l.nop Support.       (line  37)
4414
* l.nop 7 (get picoseconds per cycle):   l.nop Support.       (line  41)
4415 472 jeremybenn
* l.nop 8 (turn off tracing):            Trace Generation.    (line  40)
4416
* l.nop 8 (turn on tracing) <1>:         l.nop Support.       (line  45)
4417
* l.nop 8 (turn on tracing):             Trace Generation.    (line  40)
4418 460 jeremybenn
* l.nop 9 (turn off tracing):            l.nop Support.       (line  48)
4419
* l.nop opcode effects:                  l.nop Support.       (line   6)
4420 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
4421
* license for Or1ksim:                   GNU Free Documentation License.
4422
                                                              (line   6)
4423 440 jeremybenn
* Linux (OpenRISC) and Ethernet:         Networking from OpenRISC Linux and BusyBox.
4424
                                                              (line   6)
4425 19 jeremybenn
* list breakpoints (Interactive CLI):    Interactive Command Line.
4426
                                                              (line  60)
4427
* load_hitdelay (data cache configuration): Cache Configuration.
4428
                                                              (line  46)
4429
* load_missdelay (data cache configuration): Cache Configuration.
4430
                                                              (line  50)
4431
* log (memory configuration):            Memory Configuration.
4432 418 julius
                                                              (line 156)
4433 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
4434
                                                              (line  28)
4435 432 jeremybenn
* long:                                  Simulator Library.   (line  94)
4436 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
4437 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
4438 418 julius
                                                              (line 133)
4439 19 jeremybenn
* memory configuration:                  Memory Configuration.
4440
                                                              (line   6)
4441
* memory controller configuration:       Memory Controller Configuration.
4442
                                                              (line   6)
4443
* memory copying (Interactive CLI):      Interactive Command Line.
4444
                                                              (line  54)
4445
* memory display (Interactive CLI):      Interactive Command Line.
4446
                                                              (line  31)
4447
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
4448
                                                              (line 133)
4449
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
4450
                                                              (line 124)
4451
* memory patching (Interactive CLI):     Interactive Command Line.
4452
                                                              (line  48)
4453
* memory profiling end address:          Memory Profiling Utility.
4454
                                                              (line  56)
4455
* memory profiling start address:        Memory Profiling Utility.
4456
                                                              (line  56)
4457
* memory profiling utility (Interactive CLI): Interactive Command Line.
4458
                                                              (line 173)
4459
* memory profiling version of Or1ksim:   Memory Profiling Utility.
4460
                                                              (line   6)
4461
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
4462 346 jeremybenn
* memory_order=exact (CUC configuration): CUC Configuration.  (line  30)
4463 19 jeremybenn
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
4464 346 jeremybenn
* memory_order=strong (CUC configuration): CUC Configuration. (line  27)
4465
* memory_order=weak (CUC configuration): CUC Configuration.   (line  22)
4466 19 jeremybenn
* missdelay (branch prediction configuration): Branch Prediction Configuration.
4467
                                                              (line  37)
4468
* missdelay (instruction cache configuration): Cache Configuration.
4469
                                                              (line  42)
4470
* missdelay (MMU configuration):         Memory Management Configuration.
4471
                                                              (line  55)
4472
* MMU configuration:                     Memory Management Configuration.
4473
                                                              (line   6)
4474 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
4475 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
4476 82 jeremybenn
                                                              (line  34)
4477 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
4478 346 jeremybenn
                                                              (line 173)
4479 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
4480 432 jeremybenn
* mtspr:                                 Concepts.            (line  20)
4481 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
4482 385 jeremybenn
                                                              (line 132)
4483 19 jeremybenn
* name (generic peripheral configuration): Generic Peripheral Configuration.
4484
                                                              (line  42)
4485
* name (memory configuration):           Memory Configuration.
4486 418 julius
                                                              (line 115)
4487 346 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  45)
4488 19 jeremybenn
* nsets (cache configuration):           Cache Configuration. (line  15)
4489
* nsets (MMU configuration):             Memory Management Configuration.
4490
                                                              (line  16)
4491
* nways (cache configuration):           Cache Configuration. (line  22)
4492
* nways (MMU configuration):             Memory Management Configuration.
4493
                                                              (line  22)
4494 432 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  84)
4495
* or1ksim_init:                          Simulator Library.   (line  19)
4496
* or1ksim_interrupt:                     Simulator Library.   (line  99)
4497
* or1ksim_interrupt_clear:               Simulator Library.   (line 121)
4498
* or1ksim_interrupt_set:                 Simulator Library.   (line 110)
4499
* or1ksim_is_le:                         Simulator Library.   (line  89)
4500
* or1ksim_jtag_reset:                    Simulator Library.   (line 130)
4501
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 152)
4502
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 139)
4503
* or1ksim_read_mem:                      Simulator Library.   (line 165)
4504
* or1ksim_read_reg:                      Simulator Library.   (line 197)
4505 346 jeremybenn
* or1ksim_read_spr:                      Simulator Library.   (line 181)
4506 432 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  69)
4507
* or1ksim_run:                           Simulator Library.   (line  58)
4508
* or1ksim_set_stall_state:               Simulator Library.   (line 212)
4509
* or1ksim_set_time_point:                Simulator Library.   (line  80)
4510
* or1ksim_write_mem:                     Simulator Library.   (line 173)
4511
* or1ksim_write_reg:                     Simulator Library.   (line 205)
4512
* or1ksim_write_spr:                     Simulator Library.   (line 189)
4513 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
4514
* overflow flag setting by instructions: Configuring the Build.
4515 552 julius
                                                              (line 126)
4516 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
4517 385 jeremybenn
                                                              (line 117)
4518 19 jeremybenn
* pagesize (MMU configuration):          Memory Management Configuration.
4519
                                                              (line  27)
4520
* patching memory (Interactive CLI):     Interactive Command Line.
4521
                                                              (line  48)
4522
* patching registers (Interactive CLI):  Interactive Command Line.
4523
                                                              (line  28)
4524
* patching the program counter (Interactive CLI): Interactive Command Line.
4525
                                                              (line  51)
4526
* pattern (memory configuration):        Memory Configuration.
4527 418 julius
                                                              (line  82)
4528 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4529
                                                              (line  51)
4530 556 julius
* performance counters unit configuration: Performance Counters Configuration.
4531
                                                              (line   6)
4532 440 jeremybenn
* persistent TAP device creation:        Setting Up a Persistent TAP device.
4533
                                                              (line   6)
4534 429 julius
* phy_addr:                              Ethernet Configuration.
4535 451 jeremybenn
                                                              (line  99)
4536 19 jeremybenn
* PIC configuration:                     Interrupt Configuration.
4537
                                                              (line   6)
4538
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4539 385 jeremybenn
                                                              (line 136)
4540 19 jeremybenn
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4541 385 jeremybenn
                                                              (line  55)
4542 19 jeremybenn
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4543 385 jeremybenn
                                                              (line  56)
4544 19 jeremybenn
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4545 385 jeremybenn
                                                              (line  57)
4546 19 jeremybenn
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4547 385 jeremybenn
                                                              (line  58)
4548 19 jeremybenn
* pm (Interactive CLI):                  Interactive Command Line.
4549
                                                              (line  48)
4550
* PMR - DGCE:                            Power Management Configuration.
4551
                                                              (line  21)
4552
* PMR - DME:                             Power Management Configuration.
4553
                                                              (line  15)
4554
* PMR - SDF:                             Power Management Configuration.
4555
                                                              (line  12)
4556
* PMR - SME:                             Power Management Configuration.
4557
                                                              (line  16)
4558
* PMR - SUME:                            Power Management Configuration.
4559
                                                              (line  24)
4560
* PMU configuration:                     Power Management Configuration.
4561
                                                              (line   6)
4562
* poc (memory controller configuration): Memory Controller Configuration.
4563 385 jeremybenn
                                                              (line  64)
4564 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4565
                                                              (line  23)
4566
* power management configuration:        Power Management Configuration.
4567
                                                              (line   6)
4568
* power management register, DGCE:       Power Management Configuration.
4569
                                                              (line  21)
4570
* power management register, DME:        Power Management Configuration.
4571
                                                              (line  15)
4572
* power management register, SDF:        Power Management Configuration.
4573
                                                              (line  12)
4574
* power management register, SME:        Power Management Configuration.
4575
                                                              (line  16)
4576
* power management register, SUME:       Power Management Configuration.
4577
                                                              (line  24)
4578
* pr (Interactive CLI):                  Interactive Command Line.
4579
                                                              (line  28)
4580
* private ports, use of:                 Verification API Configuration.
4581
                                                              (line  23)
4582
* processor configuration:               CPU Configuration.   (line   6)
4583
* processor stall (Interactive CLI):     Interactive Command Line.
4584
                                                              (line  72)
4585
* processor unstall (Interactive CLI):   Interactive Command Line.
4586
                                                              (line  78)
4587
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4588
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4589
                                                              (line  23)
4590
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4591
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4592
* profiling utility (Interactive CLI):   Interactive Command Line.
4593
                                                              (line 178)
4594
* program counter patching (Interactive CLI): Interactive Command Line.
4595
                                                              (line  51)
4596
* programmable interrupt controller configuration: Interrupt Configuration.
4597
                                                              (line   6)
4598
* PS2 configuration:                     Keyboard Configuration.
4599
                                                              (line   6)
4600
* q (Interactive CLI):                   Interactive Command Line.
4601
                                                              (line  11)
4602
* quitting (Interactive CLI):            Interactive Command Line.
4603
                                                              (line  11)
4604
* r (Interactive CLI):                   Interactive Command Line.
4605
                                                              (line  14)
4606
* random_seed (memory configuration):    Memory Configuration.
4607 418 julius
                                                              (line  72)
4608 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4609 82 jeremybenn
                                                              (line  30)
4610 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4611
                                                              (line  41)
4612
* reg_sim_reset:                         Concepts.            (line  13)
4613
* register display (Interactive CLI):    Interactive Command Line.
4614
                                                              (line  14)
4615
* register over time statistics:         Configuring the Build.
4616 552 julius
                                                              (line  85)
4617 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4618
                                                              (line  28)
4619 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4620 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4621
                                                              (line  20)
4622 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4623 472 jeremybenn
                                                              (line  65)
4624 235 jeremybenn
* Remote Serial Protocol, --srv:         Standalone Simulator.
4625 472 jeremybenn
                                                              (line  73)
4626 432 jeremybenn
* report_interrupt:                      Concepts.            (line  20)
4627 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4628
                                                              (line  63)
4629
* reset hooks:                           Concepts.            (line  13)
4630
* reset the simulator (Interactive CLI): Interactive Command Line.
4631
                                                              (line  63)
4632
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4633 385 jeremybenn
                                                              (line  48)
4634 19 jeremybenn
* rev (CPU configuration):               CPU Configuration.   (line  15)
4635
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4636
                                                              (line  20)
4637
* rsp_port (debug interface configuration): Debug Interface Configuration.
4638 235 jeremybenn
                                                              (line  32)
4639 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4640 440 jeremybenn
                                                              (line  47)
4641 19 jeremybenn
* run (Interactive CLI):                 Interactive Command Line.
4642
                                                              (line  23)
4643
* running code (Interactive CLI):        Interactive Command Line.
4644
                                                              (line  23)
4645
* running Or1ksim:                       Usage.               (line   6)
4646
* runtime:                               Global Data Structures.
4647
                                                              (line  58)
4648
* runtime global structure:              Global Data Structures.
4649
                                                              (line  58)
4650
* runtime.cpu:                           Global Data Structures.
4651
                                                              (line  62)
4652
* runtime.cpu.fout:                      Concepts.            (line   7)
4653
* runtime.cuc:                           Global Data Structures.
4654
                                                              (line  62)
4655
* runtime.vapi:                          Global Data Structures.
4656
                                                              (line  62)
4657
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4658 440 jeremybenn
                                                              (line  67)
4659 19 jeremybenn
* rxfile (Ethernet configuration):       Ethernet Configuration.
4660 440 jeremybenn
                                                              (line  76)
4661 19 jeremybenn
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4662
                                                              (line  23)
4663
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4664
                                                              (line  28)
4665 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4666 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4667
                                                              (line  12)
4668
* section ata:                           Disc Interface Configuration.
4669
                                                              (line   6)
4670
* section bpb:                           Branch Prediction Configuration.
4671
                                                              (line   6)
4672
* section cpio:                          GPIO Configuration.  (line   6)
4673
* section cpu:                           CPU Configuration.   (line   6)
4674
* section cuc:                           CUC Configuration.   (line   6)
4675
* section dc:                            Cache Configuration. (line   6)
4676
* section debug:                         Debug Interface Configuration.
4677
                                                              (line   6)
4678
* section dma:                           DMA Configuration.   (line   6)
4679
* section dmmu:                          Memory Management Configuration.
4680
                                                              (line   6)
4681
* section ethernet:                      Ethernet Configuration.
4682
                                                              (line   6)
4683
* section fb:                            Frame Buffer Configuration.
4684
                                                              (line   6)
4685
* section generic:                       Generic Peripheral Configuration.
4686
                                                              (line   6)
4687
* section ic:                            Cache Configuration. (line   6)
4688
* section immu:                          Memory Management Configuration.
4689
                                                              (line   6)
4690
* section kb:                            Keyboard Configuration.
4691
                                                              (line   6)
4692
* section mc:                            Memory Controller Configuration.
4693
                                                              (line   6)
4694
* section memory:                        Memory Configuration.
4695
                                                              (line   6)
4696 556 julius
* section pcu:                           Performance Counters Configuration.
4697
                                                              (line   6)
4698 19 jeremybenn
* section pic:                           Interrupt Configuration.
4699
                                                              (line   6)
4700
* section pmu:                           Power Management Configuration.
4701
                                                              (line   6)
4702
* section sim:                           Simulator Behavior.  (line   6)
4703
* section uart:                          UART Configuration.  (line   6)
4704
* section vapi:                          Verification API Configuration.
4705
                                                              (line   6)
4706
* section vga:                           Display Interface Configuration.
4707
                                                              (line   6)
4708
* sections:                              Global Data Structures.
4709
                                                              (line  49)
4710
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4711 385 jeremybenn
                                                              (line 129)
4712 19 jeremybenn
* server_port (verification API configuration): Verification API Configuration.
4713
                                                              (line  19)
4714
* set (Interactive CLI):                 Interactive Command Line.
4715
                                                              (line 146)
4716
* set breakpoint (Interactive CLI):      Interactive Command Line.
4717
                                                              (line  57)
4718
* setdbch (Interactive CLI):             Interactive Command Line.
4719
                                                              (line 141)
4720
* simple model:                          Configuring the Build.
4721 552 julius
                                                              (line  36)
4722 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4723
* simulator configuration info (Interactive CLI): Interactive Command Line.
4724
                                                              (line 119)
4725
* simulator reset (Interactive CLI):     Interactive Command Line.
4726
                                                              (line  63)
4727
* simulator statistics (Interactive CLI): Interactive Command Line.
4728
                                                              (line  83)
4729
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4730 385 jeremybenn
                                                              (line 113)
4731 19 jeremybenn
* size (generic peripheral configuration): Generic Peripheral Configuration.
4732
                                                              (line  30)
4733
* size (memory configuration):           Memory Configuration.
4734 418 julius
                                                              (line  99)
4735 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4736
                                                              (line  16)
4737
* slow down factor (power management register): Power Management Configuration.
4738
                                                              (line  12)
4739
* SME (power management register):       Power Management Configuration.
4740
                                                              (line  16)
4741
* sr (CPU configuration):                CPU Configuration.   (line  53)
4742
* stall (Interactive CLI):               Interactive Command Line.
4743
                                                              (line  72)
4744
* stall the processor (Interactive CLI): Interactive Command Line.
4745
                                                              (line  72)
4746
* statistics, register over time:        Configuring the Build.
4747 552 julius
                                                              (line  85)
4748 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4749
                                                              (line  83)
4750
* stats (Interactive CLI):               Interactive Command Line.
4751
                                                              (line  83)
4752
* stepping code (Interactive CLI):       Interactive Command Line.
4753
                                                              (line  19)
4754
* store_hitdelay (data cache configuration): Cache Configuration.
4755
                                                              (line  54)
4756
* store_missdelay (data cache configuration): Cache Configuration.
4757
                                                              (line  58)
4758
* SUME (power management register):      Power Management Configuration.
4759
                                                              (line  24)
4760 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4761 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4762
                                                              (line  24)
4763
* t (Interactive CLI):                   Interactive Command Line.
4764
                                                              (line  19)
4765 440 jeremybenn
* TAP device creation:                   Setting Up a Persistent TAP device.
4766
                                                              (line   6)
4767
* tap_dev (Ethernet configuration):      Ethernet Configuration.
4768
                                                              (line  93)
4769 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4770 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4771
                                                              (line  23)
4772
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4773 235 jeremybenn
                                                              (line  37)
4774 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4775
* test code for target:                  Regression Testing.  (line  63)
4776
* test make file:                        Regression Testing.  (line  27)
4777
* test README:                           Regression Testing.  (line  32)
4778
* testing:                               Regression Testing.  (line   6)
4779 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4780 552 julius
                                                              (line  98)
4781 346 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  49)
4782 19 jeremybenn
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4783 346 jeremybenn
                                                              (line  49)
4784 19 jeremybenn
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4785
                                                              (line  57)
4786
* toggle debug channels (Interactive CLI): Interactive Command Line.
4787
                                                              (line 141)
4788
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4789
                                                              (line 151)
4790 442 julius
* trace generation of Or1ksim:           Trace Generation.    (line   6)
4791 19 jeremybenn
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4792 440 jeremybenn
                                                              (line  68)
4793 19 jeremybenn
* txfile (Ethernet configuration):       Ethernet Configuration.
4794 440 jeremybenn
                                                              (line  77)
4795 19 jeremybenn
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4796 82 jeremybenn
                                                              (line  36)
4797 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4798
                                                              (line  47)
4799
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4800 385 jeremybenn
                                                              (line 103)
4801 19 jeremybenn
* type (memory configuration):           Memory Configuration.
4802 385 jeremybenn
                                                              (line  37)
4803 418 julius
* type=exitnops (memory configuration):  Memory Configuration.
4804 420 jeremybenn
                                                              (line  66)
4805 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4806 385 jeremybenn
                                                              (line  47)
4807 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4808 385 jeremybenn
                                                              (line  41)
4809 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4810 385 jeremybenn
                                                              (line  51)
4811 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4812 385 jeremybenn
                                                              (line  56)
4813 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4814
* UART I/O from/to a physical serial port: UART Configuration.
4815
                                                              (line  62)
4816
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4817
* UART I/O from/to files:                UART Configuration.  (line  33)
4818
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4819
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4820
* UART verification (VAPI):              Verification API.    (line  41)
4821
* unstall (Interactive CLI):             Interactive Command Line.
4822
                                                              (line  78)
4823
* unstall the processor (Interactive CLI): Interactive Command Line.
4824
                                                              (line  78)
4825
* upr (CPU configuration):               CPU Configuration.   (line  21)
4826 432 jeremybenn
* use_nmi (interrupt controller):        Interrupt Configuration.
4827
                                                              (line  30)
4828 19 jeremybenn
* ustates (cache configuration):         Cache Configuration. (line  33)
4829
* ustates (MMU configuration):           Memory Management Configuration.
4830
                                                              (line  41)
4831
* VAPI configuration:                    Verification API Configuration.
4832
                                                              (line   6)
4833
* VAPI for Debug Unit:                   Verification API.    (line  34)
4834
* VAPI for DMA:                          Verification API.    (line  73)
4835
* VAPI for Ethernet:                     Verification API.    (line  78)
4836
* VAPI for GPIO:                         Verification API.    (line  88)
4837
* VAPI for UART:                         Verification API.    (line  41)
4838
* vapi_id (debug interface configuration): Debug Interface Configuration.
4839 235 jeremybenn
                                                              (line  43)
4840 346 jeremybenn
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4841 451 jeremybenn
                                                              (line 119)
4842 346 jeremybenn
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4843 19 jeremybenn
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4844
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4845
* vapi_log_file (verification API configuration): Verification API Configuration.
4846
                                                              (line  41)
4847
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4848
                                                              (line  41)
4849
* ver (CPU configuration):               CPU Configuration.   (line  15)
4850
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4851
* Verification API configuration:        Verification API Configuration.
4852
                                                              (line   6)
4853
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4854
                                                              (line 124)
4855
* VGA configuration:                     Display Interface Configuration.
4856
 
4857
 
4858
                                                              (line  50)
4859
4860
4861

4862
Tag Table:
4863 538 julius
Node: Top826
4864
Node: Installation1236
4865
Node: Preparation1483
4866
Node: Configuring the Build1778
4867 552 julius
Node: Build and Install7614
4868
Node: Known Issues8380
4869
Node: Usage9435
4870
Node: Standalone Simulator9719
4871
Node: Profiling Utility14863
4872
Node: Memory Profiling Utility15769
4873
Node: Trace Generation17129
4874
Node: Simulator Library19314
4875
Node: Ethernet TUN/TAP Interface29746
4876
Node: Setting Up a Persistent TAP device30851
4877
Node: Establishing a Bridge31526
4878
Node: Opening the Firewall33209
4879
Node: Disabling Ethernet Filtering33700
4880
Node: Networking from OpenRISC Linux and BusyBox34325
4881
Node: Tearing Down a Bridge35987
4882
Node: l.nop Support36730
4883
Node: Configuration38892
4884
Node: Configuration File Format39504
4885
Node: Configuration File Preprocessing39889
4886
Node: Configuration File Syntax40186
4887
Node: Simulator Configuration42971
4888
Node: Simulator Behavior43262
4889
Node: Verification API Configuration47843
4890
Node: CUC Configuration49783
4891
Node: Core OpenRISC Configuration51775
4892 556 julius
Node: CPU Configuration52316
4893
Node: Memory Configuration56435
4894
Node: Memory Management Configuration63157
4895
Node: Cache Configuration65534
4896
Node: Interrupt Configuration67920
4897
Node: Power Management Configuration69753
4898
Node: Branch Prediction Configuration71030
4899
Node: Debug Interface Configuration72390
4900
Node: Performance Counters Configuration74776
4901
Node: Peripheral Configuration75261
4902
Node: Memory Controller Configuration75887
4903
Node: UART Configuration79667
4904
Node: DMA Configuration83186
4905
Node: Ethernet Configuration85053
4906
Node: GPIO Configuration90332
4907
Node: Display Interface Configuration91965
4908
Node: Frame Buffer Configuration94274
4909
Node: Keyboard Configuration96138
4910
Node: Disc Interface Configuration98376
4911
Node: Generic Peripheral Configuration103480
4912
Node: Interactive Command Line105775
4913
Node: Verification API112749
4914
Node: Code Internals117179
4915
Node: Coding Conventions117762
4916
Node: Global Data Structures122189
4917
Node: Concepts124846
4918
Ref: Output Redirection124991
4919
Ref: Interrupts Internal125529
4920
Node: Internal Debugging126682
4921
Node: Regression Testing127206
4922
Node: GNU Free Documentation License130995

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.