OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.texi] - Blame information for rev 48

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
\input texinfo   @c -*- texinfo -*-
2
@setfilename or1ksim.info
3
@afourpaper
4
@include version.texi
5
@include config.texi
6
@dircategory Embedded development
7
@direntry
8
* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
9
                                        Simulator
10
@end direntry
11
 
12
@copying
13
This file documents the OpenRISC Architectural Simulator, @value{OR1KSIM}.
14
 
15
Copyright @copyright{} 2008, 2009 Embecosm Limited.
16
 
17
@quotation
18
Permission is granted to copy, distribute and/or modify this document
19
under the terms of the GNU Free Documentation License, Version 1.2 or
20
any later version published by the Free Software Foundation; with no
21
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
22
Texts.  A copy of the license is included in the section entitled ``GNU
23
Free Documentation License''.
24
@end quotation
25
@end copying
26
 
27
@setchapternewpage on
28
@settitle @value{OR1KSIM} User Guide
29
 
30
@syncodeindex fn cp
31
@syncodeindex vr cp
32
 
33
@titlepage
34
@title @value{OR1KSIM} User Guide
35
@author Jeremy Bennett
36
@author Embecosm Limited
37
@author Issue 1 for @value{OR1KSIM} @value{VERSION}
38
 
39
@page
40
@vskip 0pt plus 1filll
41
@insertcopying
42
 
43
Published by Embecosm Limited
44
@end titlepage
45
 
46
@contents
47
 
48
@node Top
49
@c Perhaps this should be the title of the document (but only for info,
50
@c not for TeX).  Existing GNU manuals seem inconsistent on this point.
51
@top Scope of this Document
52
 
53
This document is the user guide for @value{OR1KSIM}, the OpenRISC 1000
54
Architectural Simulator.
55
 
56
@menu
57
* Installation::
58
* Usage::
59
* Configuration::
60
* Interactive Command Line::
61
* Verification API::
62
 
63
* Code Internals::
64
 
65
* GNU Free Documentation License::  The license for this documentation
66
* Index::
67
@end menu
68
 
69
@node Installation
70
@chapter Installation
71
@cindex installing @value{OR1KSIM}
72
 
73
Installation follows standard GNU protocols.
74
 
75
@menu
76
* Preparation::
77
* Configuring the Build::
78
* Build and Install::
79
* Known Issues::
80
@end menu
81
 
82
@node Preparation
83
@section Preparation
84
 
85
Unpack the software and create a @emph{separate} directory in which to
86
build it:
87
 
88
@example
89
@kbd{tar jxf or1ksim-@value{VERSION}.tar.bz2}
90
@kbd{mkdir builddir_or1ksim}
91
@kbd{cd builddir_or1ksim}
92
@end example
93
 
94
@node Configuring the Build
95
@section Configuring the Build
96
 
97
Configure the software using the @command{configure} script in the
98
main directory.
99
 
100
The most significant argument is @code{--target}, which should specify
101
the OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
102
default to OpenRISC 1000 32-bit with a warning
103
 
104
@example
105
@kbd{../or1ksim-@value{VERSION}/configure --target=or32-uclinux ...}
106
@end example
107
 
108
There are several other options available, many of which are standard
109
to GNU @command{configure} scripts. Use @kbd{configure --help} to see
110
all the options. The most useful is @code{--prefix} to specify a
111
directory for installation of the tools.
112
 
113
A number of @value{OR1KSIM} features in the simulator do require enabling at
114
configuration. These include
115
 
116
@table @code
117
@item --enable-profiling
118
@cindex @code{--enable-profiling}
119
@itemx --disable-profiling
120
@cindex @code{--disable-profiling}
121
If enabled, @value{OR1KSIM} is compiled for profiling with
122
@command{gprof}. This is disabled by default. Only really of value for
123
developers of @value{OR1KSIM}.
124
 
125
@item --enable-execution=simple
126
@itemx --enable-execution=complex
127
@itemx --enable-execution=dynamic
128
@cindex @code{--enable-execution}
129
@cindex simple model
130
@cindex complex model
131
@cindex dynamic model
132
@value{OR1KSIM} has developed to improve functionality and
133
performance. This feature allows three versions of @value{OR1KSIM} to be built
134
 
135
@table @code
136
 
137
@item --enable-execution=simple
138
Build the original simple interpreting simulator
139
 
140
@item --enable-execution=complex
141
Build a more complex interpreting simulator. Experiments suggest this
142
is 50% faster than the simple simulator. This is the default.
143
 
144
@item --enable-execution=dynamic
145
Build a dynamically compiling simulator. This is the way many modern ISS are
146
built. This represents a work in progress. Currently @value{OR1KSIM} will
147
compile, but segfaults if configured with this option.
148
 
149
@end table
150
 
151
The default is @code{--enable-execution=complex}.
152
 
153
@item --enable-ethphy
154
@cindex @code{--enable-ethphy}
155
@itemx --disable-ethphy
156
@cindex @code{--disable-ethphy}
157
@cindex Ethernet via socket, enabling
158
@cindex enabling Ethernet via socket
159
If enabled, this option allows the Ethernet to be simulated by connecting via a
160
socket (the alternative reads and writes, from and to files). This
161
must then be configured using the relevant fields in the
162
@code{ethernet} section of the configuration file. @xref{Ethernet
163
Configuration, , Ethernet Configuration}.
164
 
165
The default is for this to be disabled.
166
 
167
@item --enable-range-stats
168
@cindex @code{--enable-range-stats}
169
@itemx --disable-range-stats
170
@cindex @code{--disable-range-stats}
171
@cindex statistics, register over time
172
@cindex register over time statistics
173
If enabled, this option allows statistics to be collected to analyse
174
register access over time. The default is for this to be disabled.
175
 
176
@item --enable-ov-flag
177
@cindex @code{--enable-ov-flag}
178
@itemx --disable-ov-flag
179
@cindex @code{--disable-ov-flag}
180
@cindex overflow flag setting by instructions
181
If enabled, this option causes instructions to set the overflow
182
flag. The instructions affected by this are @code{l.add},
183
@code{l.addc}, @code{l.addi}, @code{l.and}, @code{l.andi},
184
@code{l.div}, @code{l.divu}, @code{l.mul}, @code{l.muli}, @code{l.or},
185
@code{l.ori}, @code{l.sll}, @code{l.slli}, @code{l.srl},
186
@code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.sub}, @code{l.xor}
187
and @code{l.xori}.
188
 
189
The default is for this to be disabled.
190
 
191
@quotation Caution
192
This appears a very dangerous option, to the extent of arguably being
193
a bug. Whether or not flags are set is part of the OpenRISC 1000
194
architectural specification. Within the above list, the arithmetic
195
instructions (@code{l.add}, @code{l.addc}, @code{l.addi},
196
@code{l.div}, @code{l.divu}, @code{l.mul}, @code{l.muli} and
197
@code{l.sub}), together with @code{l.addic} which is missed out, set
198
the overflow flag. All the others (@code{l.and}, @code{l.andi},
199
@code{l.or}, @code{l.ori}, @code{l.sll}, @code{l.slli}, @code{l.srl},
200
@code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.xor} and
201
@code{l.xori}) do not.
202
 
203
Thus it is impossible to get correct behavior whichever way this option is
204
set.
205
@end quotation
206
 
207
@item --enable-arith-flag
208
@cindex @code{--enable-arith-flag}
209
@itemx --disable-arith-flag
210
@cindex @code{--disable-arith-flag}
211
@cindex flag setting by instructions
212
If enabled, this option causes instructions to set the flag (@code{F} bit) in
213
the supervision register. The instructions affected by this are @code{l.add},
214
@code{l.addc}, @code{l.addi}, @code{l.and} and @code{l.andi}.
215
 
216
The default is for this to be disabled.
217
 
218
@quotation Caution
219
As with @code{--enable-ov-flag}, this appears another very dangerous option,
220
to the extent of arguably being a bug. It also appears to be only partially
221
implemented---why only the instructions early in the alphabet?
222
 
223
Whether or not flags are set is part of the OpenRISC 1000 architectural
224
specification. The only flags which should set this are the ``set flag''
225
instructions: @code{l.sfeq}, @code{l.sfeqi}, @code{l.sfges}, @code{l.sfgesi},
226
@code{l.sfgeu}, @code{l.sfgeui}, @code{l.sfgts}, @code{l.sfgtsi},
227
@code{l.sfgtu}, @code{l.sfgtui}, @code{l.sfles}, @code{l.sflesi},
228
@code{l.sfleu}, @code{l.sfleui}, @code{l.sflts}, @code{l.sfltsi},
229
@code{l.sfltu}, @code{l.sfltui}, @code{l.sfne} and @code{l.sfnei}.
230
 
231
The flags are correctly set (irrespective of @code{--enable-arith_flag}).
232
 
233
Correct behavior is thus achieved if this flag is not set.
234
@code{--enable-arith-flag} should never be used.
235
 
236
@end quotation
237
 
238
@item --enable-debug
239
@cindex @code{--enable-debug}
240
@itemx --disable-debug
241
@cindex @code{--disable-debug}
242
@cindex debugging enabled (Argtable2)
243
@cindex Argtable2 debugging
244
This is a feature of the Argtable2 package used to process arguments. If
245
enabled, some debugging features are turned on in Argtable2. It is provided for
246
completeness, but there is no reason why this feature should ever be needed by
247
any @value{OR1KSIM} user.
248
 
249
@end table
250
 
251
@node Build and Install
252
@section Building and Installing
253
The tool is then built with:
254
 
255
@example
256
@kbd{make all}
257
@kbd{make install}
258
@end example
259
 
260
This will install the three variations of the @value{OR1KSIM} tool,
261
@command{or32-uclinux-sim}, @command{or32-uclinux-psim} and
262
@command{or32-uclinux-mpsim}, the @value{OR1KSIM} library, @file{libsim}, the
263
header file, @file{or1ksim.h} and this documentation in @command{info} format.
264
 
265
@quotation Note
266
Testing @value{OR1KSIM} with @kbd{make check} is not yet supported.
267
@end quotation
268
 
269
The documentation may be created and installed in alternative formats (PDF,
270
Postscript, DVI, HTML) with for example:
271
 
272
@example
273
@kbd{make pdf}
274
@kbd{make install-pdf}
275
@end example
276
 
277
@node Known Issues
278
@section Known Problems and Issues
279
 
280
The following problems and issues are known about with @value{OR1KSIM}
281
@value{VERSION}. The OpenRISC tracker may be used to see the current
282
state of these issues and to raise new problems and feature requests. It
283
may be found at @url{http://www.opencores.org/ptracker.cgi/view/or1k/398}.
284
 
285
@itemize @bullet
286
@item
287
The Supervision Register Little Endian Enable (LEE) bit is
288
ignored. @value{OR1KSIM} can be built for either little endian or big endian
289
use, but that behavior cannot be changed dynamically.
290
 
291
@item
292
The NPC is a read/write register, but after being written it clears the
293
pipeline. This means that if the processor is stalled, the value should
294
subsequently read back as 0, until the processor is unstalled and able
295
to refill its pipeline. By default @value{OR1KSIM} always reports back the value
296
of NPC, even when it has been written while stalled.
297
 
298
There is now an option, @code{--strict-npc}, which will enforce this
299
behavior. At some stage in the future it will become the default
300
behavior, but for now it is an option, since its use will break GDB.
301
 
302
@item
303
The memory components are given names in the configuration file. However
304
there is currently no way for @value{OR1KSIM} to report that name back to the
305
user (for example to identify which memory block corresponds to a
306
particular access).
307
 
308
@item
309
@value{OR1KSIM} allows the processor to be stalled (from the command
310
line), even if there is no debugger present. This seems to be a
311
meaningless operation.
312
 
313
@item
314
@value{OR1KSIM} is not reentrant, so a program cannot instantiate
315
multiple instances using the library. This is clearly a problem when
316
considering multi-core applications. However it stems from the original
317
design, and can only be fixed by a complete rewrite. The entire source
318
code uses static global constants liberally!
319
 
320
@item
321
There is no support for floating point instructions currently in
322
@value{OR1KSIM}. However this is a work in progress and should be available in
323
the near future.
324
 
325
@end itemize
326
 
327
@node Usage
328
@chapter Usage
329
@cindex running @value{OR1KSIM}
330
 
331
@menu
332
* Standalone Simulator::
333
* Profiling Utility::
334
* Memory Profiling Utility::
335
* Simulator Library::
336
@end menu
337
 
338
@node Standalone Simulator
339
@section Standalone Simulator
340
@cindex command line for @value{OR1KSIM} standalone use
341
 
342
The general form the standalone command is:
343
 
344
@example
345
or32-uclinux-sim [-vhi] [-f @var{file}] [--nosrv] [--srv=[@var{n}]] [-d @var{str}]
346
                 [--enable-profile] [--enable-mprofile] [@var{file}]
347
@end example
348
 
349
Many of the options have both a short and a long form. For example
350
@code{-h} or @code{--help}.
351
 
352
@table @code
353
 
354
@item -v
355
@itemx --version
356
@cindex @code{-v}
357
@cindex @code{--version}
358
Print out the version and copyright notice for @value{OR1KSIM} and
359
exit.
360
 
361
@item -h
362
@itemx --help
363
@cindex @code{-h}
364
@cindex @code{--help}
365
Print out help about the command line options and what they mean.
366
 
367
@item -f @var{file}
368
@itemx --file @var{file}
369
@cindex @code{-f}
370
@cindex @code{--file}
371
Read configuration commands from the specified file, looking first in
372
the current directory, and otherwise in the @file{$HOME/.or1k}
373
directory. If this argument is not specified, the file @file{sim.cfg}
374
in those two locations is used. Failure to find the file is a fatal
375
error. @xref{Configuration, , Configuration}, for detailed information
376
on configuring @value{OR1KSIM}.
377
 
378
@item --nosrv
379
@cindex @code{--nosrv}
380
Do not start up the debug server. This overrides any setting specified
381
in the configuration file. This option may not be specified with
382
@code{--srv}. If it is, a rude message is printed and the
383
@code{--nosrv} option is ignored.
384
 
385
@item --srv
386
@item --srv=@var{n}
387
@cindex @code{--srv}
388
Start up the debug server. If the parameter, @var{n}, is specified,
389
use that as the TCP/IP port for the server, otherwise a random value
390
from the private port range (41920-65535) will be used. This option
391
may not be specified with @code{--nosrv}. If it is, a rude message is
392
printed and the @code{--nosrv} option is ignored.
393
 
394
@item -d=@var{config_string}
395
@itemx --debug-config=@var{config_string}
396
@cindex @code{-d}
397
@cindex @code{--debug-config}
398
Enable selected debug messages in @value{OR1KSIM}. This parameter is
399
for use by developers only, and is not covered further here. See the
400
source code for more details.
401
 
402
@item -i
403
@itemx --interactive
404
@cindex @code{-i}
405
@cindex @code{--interactive}
406
After starting, drop into the @value{OR1KSIM} interactive command
407
shell.
408
 
409
@item --strict-npc
410
@cindex @code{--strict-npc}
411
In real hardware, setting the next program counter (NPC, SPR 16),
412
flushes the processor pipeline. The consequence of this is that until
413
the pipeline refills, reading the NPC will return zero. This is typically
414
the case when debugging, since the processor is stalled.
415
 
416
Historically, @value{OR1KSIM} has always returned the value of the NPC,
417
irrespective of when it is changed. If the @code{--strict-npc} option is
418
used, then @value{OR1KSIM} will mirror real hardware more accurately. If the NPC
419
is changed while the processor is stalled, subsequent reads of its value
420
will return 0 until the processor is unstalled.
421
 
422
This is not currently the default behavior, since tools such as GDB have
423
been implemented assuming the historic @value{OR1KSIM} behavior. However at some
424
time in the future it will become the default.
425
 
426
@item --enable-profile
427
@cindex @code{--enable-profile}
428
Enable instruction profiling.
429
 
430
@item --enable-mprofile
431
@cindex @code{--enable-mprofile}
432
Enable memory profiling.
433
 
434
@end table
435
 
436
@node Profiling Utility
437
@section Profiling Utility
438
@cindex profiling for @value{OR1KSIM}
439
@cindex instruction profiling for @value{OR1KSIM}
440
 
441
This utility analyses instruction profile data generated by
442
@value{OR1KSIM}. It may be invoked as a standalone command, or from
443
the @value{OR1KSIM} CLI. The general form the standalone command is:
444
 
445
@example
446
or32-uclinux-profile [-vhcq] [-g=@var{file}]
447
@end example
448
 
449
Many of the options have both a short and a long form. For example
450
@code{-h} or @code{--help}.
451
 
452
@table @code
453
 
454
@item -v
455
@itemx --version
456
@cindex @code{-v} (profiling utility)
457
@cindex @code{--version} (profiling utility)
458
Print out the version and copyright notice for the @value{OR1KSIM}
459
profiling utility and exit.
460
 
461
@item -h
462
@itemx --help
463
@cindex @code{-h} (profiling utility)
464
@cindex @code{--help} (profiling utility)
465
Print out help about the command line options and what they mean.
466
 
467
@item -c
468
@itemx --cumulative
469
@cindex @code{-c}
470
@cindex @code{--cumulative}
471
Show cumulative sum of cycles in functions
472
 
473
@item -q
474
@itemx --quiet
475
@cindex @code{-q}
476
@cindex @code{--quiet}
477
Suppress messages
478
 
479
@item -g=@var{file}
480
@itemx --generate=@var{file}
481
@cindex @code{-g}
482
@cindex @code{--generate}
483
The data file to analyse. If omitted, the default file,
484
@file{sim.profile} is used.
485
 
486
@end table
487
 
488
@node Memory Profiling Utility
489
@section Memory Profiling Utility
490
@cindex memory profiling version of @value{OR1KSIM}
491
 
492
This utility analyses memory profile data generated by
493
@value{OR1KSIM}. It may be invoked as a standalone command, or from
494
the @value{OR1KSIM} CLI. The general form the standalone command is:
495
 
496
@example
497
or32-uclinux-mprofile  [-vh] [-m=@var{m}] [-g=@var{n}] [-f=@var{file}] @var{from} @var{to}
498
@end example
499
 
500
Many of the options have both a short and a long form. For example
501
@code{-h} or @code{--help}.
502
 
503
@table @code
504
 
505
@item -v
506
@itemx --version
507
@cindex @code{-v} (memory profiling utility)
508
@cindex @code{--version} (memory profiling utility)
509
Print out the version and copyright notice for the @value{OR1KSIM}
510
memory profiling utility and exit.
511
 
512
@item -h
513
@itemx --help
514
@cindex @code{-h} (memory profiling utility)
515
@cindex @code{--help} (memory profiling utility)
516
Print out help about the command line options and what they mean.
517
 
518
@item -m=@var{m}
519
@itemx --mode=@var{m}
520
@cindex @code{-m}
521
@cindex @code{--mode}
522
Specify the mode out output. Permitted options are
523
 
524
@table @code
525
 
526
@item detailed
527
@itemx d
528
Detailed output. This is the default if no mode is specified.
529
 
530
@item pretty
531
@itemx p
532
Pretty printed output.
533
 
534
@item access
535
@itemx a
536
Memory accesses only.
537
 
538
@item width
539
@itemx w
540
Access width only.
541
 
542
@end table
543
 
544
@item -g=@var{n}
545
@itemx --group=@var{n}
546
@cindex @code{-g}
547
@cindex @code{--group}
548
Group @math{2^n} bits of successive addresses together.
549
 
550
@item -f=@var{file}
551
@itemx --filename=@var{file}
552
@cindex @code{-f}
553
@cindex @code{--filename}
554
The data file to analyse. If not specified, the default,
555
@file{sim.profile} is used.
556
 
557
@item @var{from}
558
@itemx @var{to}
559
@cindex memory profiling start address
560
@cindex memory profiling end address
561
@var{from} and @var{to} are respectively the start and end address of
562
the region of memory to be analysed.
563
 
564
@end table
565
 
566
@node Simulator Library
567
@section Simulator Library
568
@cindex library version of @value{OR1KSIM}
569
 
570
@value{OR1KSIM} may be used as a static of dynamic library,
571
@file{libsim.a} or @file{libsim.so}. When compiling with the static
572
library, the flag, @code{-lsim} should be added to the link command.
573
 
574
The header file @file{or1ksim.h} contains appropriate declarations of
575
the functions exported by the @value{OR1KSIM} library. These are:
576
 
577
@deftypefn {@file{or1ksim.h}} int or1ksim_init (const char *@var{config_file}, const char *@var{image_file}, void *@var{class_ptr}, unsigned long int (*@var{upr})(void *@var{class_ptr}, unsigned long int @var{addr}, unsigned long int @var{mask}), void (*@var{upw})(void *@var{class_ptr}, unsigned long int @var{addr}, unsigned long int @var{mask}, unsigned long int @var{wdata}))
578
 
579
The initialization function is supplied with the name of a
580
configuration file, @var{config_file}, an executable image, @var{image_file}, a pointer to the calling
581
class, @var{class_ptr} (since the library may be used from C++) and
582
two up-call functions, one for reads, @var{upr}, and one for writes,
583
@var{upw}.
584
 
585
@xref{Configuration, , Configuration}, for detailed information on
586
configuring @value{OR1KSIM} and the format of the configuration file.
587
 
588
@var{upw} is called for any write to an address external to the model
589
(determined by a @code{generic} section in the configuration
590
file). @var{upr} is called for any reads to an external address. The
591
@var{class_ptr} is passed back with these upcalls, allowing the
592
function to associate the call with the class which originally
593
initialized the library.
594
 
595
@var{mask} indicates which bytes in the word are to be written or
596
read. Bytes to be read/written should have 0xff set in
597
@var{mask}. Otherwise the byte should be zero.
598
 
599
@var{addr}, @var{mask}, @var{wdata} and the result from @var{upr} all
600
use host-endianess, @emph{not} model-endianess. The internal
601
@value{OR1KSIM} routines manage all the conversion.
602
 
603
@end deftypefn
604
 
605
@deftypefn {@file{or1ksim.h}} int or1ksim_run (double  @var{duration})
606
 
607
Run the simulator for the simulated duration specified (in seconds).
608
 
609
@end deftypefn
610
 
611
@deftypefn {@file{or1ksim.h}} void or1ksim_reset_duration (double @var{duration})
612
 
613
Change the duration of a run specified in an earlier call to
614
@code{or1ksim_run}. Typically this is called from an upcall, which
615
realizes it needs to change the duration of the run specified in the
616
call to @code{or1ksim_run} that has been interrupted by the upcall.
617
 
618
The time specified is the amount of time that the run must continue
619
for (i.e the duration from @emph{now}, not the duration from the original
620
call to @code{or1ksim_run}).
621
 
622
@end deftypefn
623
 
624
@deftypefn {@file{or1ksim.h}} void  or1ksim_set_time_point ()
625
 
626
Set a timing point. For use with @code{or1ksim_get_time_period}.
627
 
628
@end deftypefn
629
 
630
@deftypefn {@file{or1ksim.h}} double  or1ksim_get_time_period ()
631
 
632
Return the simulated time (in seconds) that has elapsed since the last
633
call to @code{or1ksim_set_time_point}.
634
 
635
@end deftypefn
636
 
637
@deftypefn {@file{or1ksim.h}} int  or1ksim_is_le ()
638
 
639
Return 1 (logical true) if the @value{OR1KSIM} simulation is
640
little-endian, 0 otherwise.
641
 
642
@end deftypefn
643
 
644
@deftypefn {@file{or1ksim.h}} unsigned long int  or1ksim_clock_rate ()
645
 
646
Return the @value{OR1KSIM} clock rate (in Hz). This is the value
647
specified in the configuration file.
648
 
649
@end deftypefn
650
 
651
@deftypefn {@file{or1ksim.h}} void or1ksim_interrupt (int  @var{i})
652
 
653
Generate an edge-triggered interrupt on interrupt line @var{i}. The interrupt
654
is then immediately cleared automatically. A warning will be generated and the
655
interrupt request ignored if level sensitive interrupts have been configured
656
with the programmable interrupt controller (@pxref{Interrupt Configuration, ,
657
Interrupt Configuration}).
658
 
659
@end deftypefn
660
 
661
@deftypefn {@file{or1ksim.h}} void or1ksim_interrupt_set (int  @var{i})
662
 
663
Assert a level-triggered interrupt on interrupt line @var{i}. The interrupt
664
must be cleared separately by an explicit call to
665
@code{or1ksim_interrupt_clear}. A warning will be generated, and the interrupt
666
request ignored if edge sensitive interrupts have been configured with the
667
programmable interrupt controller (@pxref{Interrupt Configuration, , Interrupt
668
Configuration}).
669
 
670
@end deftypefn
671
 
672
@deftypefn {@file{or1ksim.h}} void or1ksim_interrupt_clear (int  @var{i})
673
 
674
Clear a level-triggered interrupt on interrupt line @var{i}, which was
675
previously asserted by a call to @code{or1ksim_interrupt_set}. A warning will
676
be generated, and the interrupt request ignored if edge sensitive interrupts
677
have been configured with the programmable interrupt controller
678
(@pxref{Interrupt Configuration, , Interrupt Configuration}).
679
 
680
@end deftypefn
681
 
682
The libraries will be installed in the @file{lib} sub-directory of the
683
main installation directory (as specified with the @option{--prefix}
684
option to the @command{configure} script).
685
 
686
For example if the main installation directory is @file{/opt/or1ksim},
687
the library will be found in the @file{/opt/or1ksim/lib} directory. It
688
is available as both a static library (@file{libsim.a}) and a shared
689
object (@file{libsim.so}).
690
 
691
To link against the library add the @option{-lsim} flag when linking
692
and do one of the following:
693
 
694
@itemize @bullet
695
 
696
@item
697
Add the library directory to the @code{LD_LIBRARY_PATH} environment
698
variable during execution. For example:
699
 
700
@example
701
export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
702
@end example
703
 
704
@item
705
Add the library directory to the @code{LD_RUN_PATH} environment
706
variable during linking. For example:
707
 
708
@example
709
export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
710
@end example
711
 
712
@item
713
Use the linker @option{--rpath} option and specify the library
714
directory when linking your program. For example
715
 
716
@example
717
gcc ... -Wl,--rpath -Wl,/opt/or1ksim/lib ...
718
@end example
719
 
720
@item
721
Add the library directory to @file{/etc/ld.so.conf}
722
 
723
@end itemize
724
 
725
@node Configuration
726
@chapter Configuration
727
@cindex configuring @value{OR1KSIM}
728
 
729
@value{OR1KSIM} is configured through a configuration file. This is specified
730
through the @code{-f} parameter to the @value{OR1KSIM} command, or passed as a
731
string when initializing the @value{OR1KSIM} library. If no file is specified,
732
the default @file{sim.cfg} is used. The file is looked for first in the
733
current directory, then in the @file{$HOME/.or1k} directory of the user.
734
 
735
@menu
736
* Configuration File Format::
737
* Simulator Configuration::
738
* Core OpenRISC Configuration::
739
* Peripheral Configuration::
740
@end menu
741
 
742
@node Configuration File Format
743
@section Configuration File Format
744
@cindex configuration file structure
745
 
746
The configuration file is a plain text file.
747
 
748
@menu
749
* Configuration File Preprocessing::
750
* Configuration File Syntax::
751
@end menu
752
 
753
@node Configuration File Preprocessing
754
@subsection Configuration File Preprocessing
755
 
756
The configuration file may include C style comments (i.e. delimited by
757
@code{/*} and @code{*/}).
758
 
759
Configure files may be included, using
760
 
761
@example
762
include @var{filename_to_include}
763
@end example
764
 
765
@node Configuration File Syntax
766
@subsection Configuration File Syntax
767
 
768
The configuration file is divided into a series of sections, with the general
769
form:
770
 
771
@example
772
section @var{section_name}
773
 
774
  <contents>...
775
 
776
end
777
@end example
778
 
779
Sections may also have sub-sections within them (currently only the
780
ATA/ATAPI disc interface uses this).
781
 
782
Within a section, or sub-section are a series of parameter assignments, one
783
per line, withe the general form
784
 
785
@example
786
  @var{parameter} = @var{value}
787
@end example
788
 
789
Depending on the parameter, the value may be a named value (an enumeration),
790
an integer (specified in any format acceptable in C) or a string in doubple
791
quotes. For flag parameters, the value 1 is used to mean ``true'' or ``on''
792
and the value ``0'' to mean ``false'' or ``off''. An example from a memory
793
section shows each of these
794
 
795
@example
796
section memory
797
  type    = random
798
  pattern = 0x00
799
  name    = "FLASH"
800
  ...
801
end
802
@end example
803
 
804
Many parameters are optional and take reasonable default values if not
805
specified. However there are some parameters (for example the
806
@code{ce} parameter in @code{@w{section memory}}) @emph{must} be
807
specified.
808
 
809
Subsections are introduced by a keyword, with a parameter value (no
810
@code{=} sign), and end with the same keyword prefixed by
811
@code{end}. Thus the ATA/ATAPI inteface (@code{@w{section ata}}) has a
812
@code{device} subsection, thus:
813
 
814
@example
815
section ata
816
  ...
817
  device 0
818
    type    = 1
819
    file = "@var{filename}"
820
    ...
821
  enddevice
822
  ...
823
end
824
@end example
825
 
826
Some sections (for example @code{@w{section sim}}) should appear only
827
once. Others (for example @code{@w{section memory}} may appear
828
multiple times.
829
 
830
Sections may be omitted, @emph{unless they contain parameters which
831
are non-optional}. If the section describes a part of the simulator
832
which is optional (for example whether it has a UART), then that
833
functionality will not be provided. If the section describes a part of
834
the simulator which is not optional (for example the CPU), then all the
835
parameters of that section will take their default values.
836
 
837
All optional parts of the functionality are always described by
838
sections including a @code{enabled} parameter, which can be set to 0
839
to ensure that functionality is explicitly omitted.
840
 
841
Even if a section is disabled, all its parameters will be read and
842
stored. This is helpful if the section is subsequently enabled from
843
the @value{OR1KSIM} command line (@pxref{Interactive Command Line, ,
844
Interactive Command Line}).
845
 
846
@quotation Tip
847
It generally clearer to have sections describing @emph{all}
848
components, with omitted functionality explicitly indicated by setting
849
the @code{enabled} parameter to 0
850
@end quotation
851
 
852
The following sections describe the various configuration sections and the
853
parameters which may be set in each.
854
 
855
@node Simulator Configuration
856
@section Simulator Configuration
857
 
858
@menu
859
* Simulator Behavior::
860
* Verification API Configuration::
861
* CUC Configuration::
862
@end menu
863
 
864
@node Simulator Behavior
865
@subsection Simulator Behavior
866
@cindex configuring the behavior of @value{OR1KSIM}
867
@cindex simulator configuration
868
@cindex @code{section sim}
869
Simulator behavior is described in @code{section sim}. This section
870
should appear only once. The following parameters may be specified.
871
 
872
@table @code
873
 
874
@item verbose = 0|1
875
@cindex @code{verbose} (simulator configuration)
876
If 1 (true), print extra messages. Default 0.
877
 
878
@item debug = 0-9
879
@cindex @code{debug} (simulator configuration)
880
 
881
value the greater the number of messages. Default 0. Negative values
882
will be treated as 0 (with a warning). Values that are too large will
883
be treated as 9 (with a warning).
884
 
885
@item profile = 0|1
886
@cindex @code{profile} (simulator configuration)
887
If 1 (true) generate a profiling file using the file specified in the
888
@code{prof_file} parameter or otherwise @file{sim.profile}. Default 0.
889
 
890
@item prof_file = ``@var{filename}''
891
@cindex @code{prof_file} (simulator configuration)
892
@cindex @code{prof_fn} (simulator configuration - deprecated)
893
Specifies the file to be used with the @code{profile} parameter. Default
894
@file{sim.profile}. For backwards compatibility, the alternative name
895
@code{prof_fn} is supported for this parameter, but deprecated.
896
 
897
@item mprofile = 0|1
898
@cindex @code{mprofile} (simulator configuration)
899
If 1 (true) generate a memory profiling file using the file specified in the
900
@code{mprof_file} parameter or otherwise @file{sim.mprofile}. Default 0.
901
 
902
@item mprof_fn = ``@var{filename}''
903
@cindex @code{mprof_file} (simulator configuration)
904
@cindex @code{mprof_fn} (simulator configuration - deprecated)
905
Specifies the file to be used with the @code{mprofile} parameter. Default
906
@file{sim.mprofile}. For backwards compatibility, the alternative name
907
@code{mprof_fn} is supported for this parameter, but deprecated.
908
 
909
@item history = 0|1
910
@cindex @code{history} (simulator configuration)
911
If 1 (true) track execution flow. Default 0.
912
 
913
@quotation Note
914
Setting this parameter seriously degrades performance.
915
@end quotation
916
 
917
@quotation Note
918
If this execution flow tracking is enabled, then @code{dependstats}
919
must be enabled in the CPU configuration section (@pxref{CPU
920
Configuration, , CPU Configuration}).
921
@end quotation
922
 
923
@item exe_log = 0|1
924
@cindex @code{exe_log} (simulator configuration)
925
If 1 (true), generate an execution log. Log is written to the file specified
926
in parameter @code{exe_log_file}. Default 0.
927
 
928
@quotation Note
929
Setting this parameter seriously degrades performance.
930
@end quotation
931
 
932
@item exe_log_type = default|hardware|simple|software
933
@cindex @code{exe_log_type} (simulator configuration)
934
Type of execution log to produce.
935
 
936
@table @code
937
 
938
@item default
939
@cindex @code{exe_log_type=default} (simulator configuration)
940
Produce default output for the execution log. In the current implementation
941
this is the equivalent of @code{hardware}.
942
 
943
@item hardware
944
@cindex @code{exe_log_type=hardware} (simulator configuration)
945
After each instruction execution, log the number of instructions executed so
946
far, the next instruction to execute (in hex), the general purpose registers
947
(GPRs), status register, exception program counter, exception, effective
948
address register and exception status register.
949
 
950
@item simple
951
@cindex @code{exe_log_type=simple} (simulator configuration)
952
After each instruction execution, log the number of instructions executed so
953
far and the next instruction to execute, symbolically disassembled.
954
 
955
@item software
956
@cindex @code{exe_log_type=software} (simulator configuration)
957
After each instruction execution, log the number of instructions executed so
958
far and the next instruction to execute, symbolically disassembled. Also show
959
the value of each operand to the instruction.
960
 
961
@end table
962
 
963
Default value @code{hardware}. Any unrecognized keyword (case
964
insensitive) will be treated as the default with a warning.
965
 
966
@quotation Note
967
Execution logs can be @emph{very} big.
968
@end quotation
969
 
970
@item exe_log_start = @var{value}
971
@cindex @code{exe_log_start} (simulator configuration)
972
Address of the first instruction to start logging. Default 0.
973
 
974
@item exe_log_end = @var{value}
975
@cindex @code{exe_log_end} (simulator configuration)
976
Address of the last instruction to log. Default no limit (i.e once started
977
logging will continue until the simulator exits).
978
 
979
@item exe_log_marker = @var{value}
980
@cindex @code{exe_log_marker} (simulator configuration)
981
Specifies the number of instructions between printing horizontal
982
markers. Default is to produce no markers.
983
 
984
@item exe_log_file = @var{filename}
985
@cindex @code{exe_log_file} (simulator configuration)
986
@cindex @code{exe_log_fn} (simulator configuration - deprecated)
987
Filename for the execution log filename if @code{exe_log} is enabled. Default
988
@file{executed.log}. For backwards compatibility, the alternative name
989
@code{exe_log_fn} is supported for this parameter, but deprecated.
990
 
991
@item clkcycle = @var{value}[ps|ns|us|ms]
992
@cindex @code{clkcycle} (simulator configuration)
993
Specify the time taken by one clock cycle. If no units are specified,
994
@code{ps} is assumed. Default 4000ps (250MHz).
995
 
996
@end table
997
 
998
@node Verification API Configuration
999
@subsection Verification API (VAPI) Configuration
1000
@cindex configuring the Verification API (VAPI)
1001
@cindex Verification API configuration
1002
@cindex VAPI configuration
1003
@cindex @code{section vapi}
1004
The Verification API (VAPI) provides a TCP/IP interface to allow
1005
components of the simulation to be controlled
1006
externally. @xref{Verification API, , Verification API}, for more
1007
details.
1008
 
1009
Verification API configuration is described in @code{section
1010
vapi}. This section may appear at most once. The following parameters
1011
may be specified.
1012
 
1013
@table @code
1014
 
1015
@item enabled = 0|1
1016
@cindex @code{enabled} (verification API configuration)
1017
If 1 (true), verification API is enabled and its server started. If 0
1018
(the default), it is disabled.
1019
 
1020
@item server_port = @var{value}
1021
@cindex @code{server_port} (verification API configuration)
1022
When VAPI is enabled, communication will be via TCP/IP on the port
1023
specified by @var{value}. The value must lie in the range 1 to 65535.
1024
The default value is 50000.
1025
 
1026
@quotation Tip
1027
@cindex TCP/IP port range
1028
@cindex port range for TCP/IP
1029
@cindex dynamic ports, use of
1030
@cindex private ports, use of
1031
There is no registered port for @value{OR1KSIM} VAPI. Good practice
1032
suggests users should adopt port values in the @dfn{Dynamic} or
1033
@dfn{Private} port range, i.e. 49152-65535.
1034
@end quotation
1035
 
1036
@item log_enabled = 0|1
1037
@cindex @code{log_enabled} (verification API configuration)
1038
If 1 (true), all VAPI requests and sent commands will be logged. If 0
1039
(the default), logging is diabled. Logs are written to the file
1040
specified by the @code{vapi_log_file} field (see below).
1041
 
1042
@quotation Caution
1043
This can generate a substantial amount of file I/O and seriously
1044
degrade simulator performance.
1045
@end quotation
1046
 
1047
@item hide_device_id = 0|1
1048
@cindex @code{hide_device_id} (verification API configuration)
1049
If 1 (true) don't log the device ID. If 0 (the default), log the
1050
device ID. This feature (when set to 1) is provided for backwards
1051
compatibility with an old version of VAPI.
1052
 
1053
@item vapi_log_file = "@var{filename}"
1054
@cindex @code{vapi_log_file} (verification API configuration)
1055
@cindex @code{vapi_log_fn} (verification API configuration - deprecated)
1056
Use @file{filename} as the file for logged data is logging is enabled
1057
(see @code{log_enabled} above). The default is @code{"vapi.log"}. For
1058
backwards compatibility, the alternative name @code{vapi_log_fn} is
1059
supported for this parameter, but deprecated.
1060
 
1061
@end table
1062
 
1063
@node CUC Configuration
1064
@subsection Custom Unit Compiler (CUC) Configuration
1065
@cindex configuring the Custom Unit Compiler (CUC)
1066
@cindex Custom Unit Compiler Configuration
1067
@cindex CUC configuration
1068
@cindex @code{section cuc}
1069
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1070
Verilog from ANSI C functions. The project seems to not have progressed
1071
beyond the initial prototype phase. The configuration parameters are
1072
described here for the record.
1073
 
1074
CUC configuration is described in @code{@w{section cuc}}. This section
1075
may appear at most once. The following parameters may be specified.
1076
 
1077
@table @code
1078
 
1079
@item memory_order = none|weak|strong|exact
1080
@cindex @code{memory_order} (CUC configuration)
1081
This parameter specifies the memory ordering required:
1082
 
1083
@table @code
1084
 
1085
@item memory_order=none
1086
@cindex @code{memory_order=none} (CUC configuration)
1087
Different memory ordering, even if there are dependencies. Bursts can
1088
be made, width can change.
1089
 
1090
@cindex @code{memory_order=weak} (CUC configuration)
1091
Different memory ordering, even if there are dependencies. If
1092
dependencies cannot occur, then bursts can be made, width can change.
1093
 
1094
@cindex @code{memory_order=strong} (CUC configuration)
1095
Same memory ordering. Bursts can be made, width can change.
1096
 
1097
@cindex @code{memory_order=exact} (CUC configuration)
1098
Exactly the same memory ordering and widths.
1099
 
1100
@end table
1101
 
1102
The default value is @code{memory_order=exact}. Invalid memory
1103
orderings are ignored with a warning.
1104
 
1105
@item calling_convention = 0|1
1106
@cindex @code{calling_convention} (CUC configuration)
1107
If 1 (true), programs follow OpenRISC calling conventions. If 0 (the
1108
default), they may use other convenitions.
1109
 
1110
@item enable_bursts = 0 | 1
1111
@cindex @code{enable_bursts} (CUC configuration)
1112
If 1 (true), bursts are detected. If 0 (the default), bursts are not
1113
detected.
1114
 
1115
@item no_multicycle = 0 | 1
1116
@cindex @code{no_multicycle} (CUC configuration)
1117
If 1 (true), no multicycle logic paths will be generated. If 0 (the
1118
default), multicycle logic paths will be generated.
1119
 
1120
@item timings_file = "@var{filename}"
1121
@cindex @code{timings_file} (CUC configuration)
1122
@cindex @code{timings_fn} (CUC configuration - deprecated)
1123
@var{filename} specifies a file containing timing information. The
1124
default value is @code{"virtex.tim"}. For backwards compatibility, the
1125
alternative name @code{timings_fn} is supported for this parameter,
1126
but deprecated.
1127
 
1128
@end table
1129
 
1130
@node Core OpenRISC Configuration
1131
@section Configuring the OpenRISC Architectural Components
1132
 
1133
@menu
1134
* CPU Configuration::
1135
* Memory Configuration::
1136
* Memory Management Configuration::
1137
* Cache Configuration::
1138
* Interrupt Configuration::
1139
* Power Management Configuration::
1140
* Branch Prediction Configuration::
1141
* Debug Interface Configuration::
1142
@end menu
1143
 
1144
@node CPU Configuration
1145
@subsection CPU Configuration
1146
@cindex configuring the CPU
1147
@cindex configuring the processor
1148
@cindex CPU configuration
1149
@cindex processor configuration
1150
@cindex @code{section cpu}
1151
CPU configuration is described in @code{section cpu}. This section
1152
should appear only once. At present @value{OR1KSIM} does not model multi-CPU
1153
systems. The following parameters may be specified.
1154
 
1155
@table @code
1156
 
1157
@item ver = @var{value}
1158
@item cfg = @var{value}
1159
@item rev = @var{value}
1160
@cindex @code{ver} (CPU configuration)
1161
@cindex @code{rev} (CPU configuration)
1162
The values are used to form the corresponding fields in the @code{VR}
1163
Special Purpose Register (SPR 0). Default values 0. A warning is given
1164
and the value truncated if it is too large (8 bits for @code{ver} and
1165
@code{cfg}, 6 bits for @code{rev}).
1166
 
1167
@item upr = @var{value}
1168
@cindex @code{upr} (CPU configuration)
1169
Used as the value of the Unit Present Register (UPR) Special Purpose Register
1170
(SPR 1) to @var{value}. Default value is 0x0000075f, i.e.
1171
@itemize @bullet
1172
@item
1173
UPR present (0x00000001)
1174
@item
1175
Data cache present (0x00000002)
1176
@item
1177
Instruction cache present (0x00000004)
1178
@item
1179
Data MMY present (0x00000008)
1180
@item
1181
Instruction MMU present (0x00000010)
1182
@item
1183
Debug unit present (0x00000040)
1184
@item
1185
Power management unit present (0x00000100)
1186
@item
1187
Programmable interrupt controller present (0x00000200)
1188
@item
1189
Tick timer present (0x00000400)
1190
@end itemize
1191
 
1192
However, with the exection of the UPR present (0x00000001) and tick
1193
timer present, the various
1194
fields will be modified with the values specified in their corresponding
1195
configuration sections.
1196
 
1197
@item cfgr = @var{value}
1198
@cindex @code{cfgr} (CPU configuration)
1199
Sets the CPU configuration register (Special Purpose Register 2) to
1200
@var{value}. Default value is 0x00000020, i.e. support for the ORBIS32
1201
instruction set. Attempts to set any other value are accepted, but
1202
issue a warning that there is no support for the instruction set.
1203
 
1204
@item sr = @var{value}
1205
@cindex @code{sr} (CPU configuration)
1206
Sets the supervision register Special Purpose Register (SPR 0x11) to
1207
@var{value}. Default value is 0x00008001, i.e. start in supervision
1208
mode (0x00000001) and set the ``Fixed One'' bit (0x00008000).
1209
 
1210
@item superscalar = 0|1
1211
@cindex @code{superscalar} (CPU configuration)
1212
If 1, the processor operates in superscalar mode. Default value is
1213
0.
1214
 
1215
In the current simulator, the only functional effect of superscalar
1216
mode is to affect the calculation of the number of cycles taken to
1217
execute an instruction.
1218
 
1219
@quotation Caution
1220
The code for this does not appear to be complete or well tested, so
1221
users are advised not to use this option.
1222
@end quotation
1223
 
1224
@item hazards = 0|1
1225
@cindex @code{hazards} (CPU configuration)
1226
If 1, data hazards are tracked in a superscalar CPU. Default value is
1227
0.
1228
 
1229
In the current simulator, the only functional effect is to cause
1230
logging of hazard waiting information if the CPU is
1231
superscalar. However nowhere in the simulator is this data actually
1232
computed, so the net result is probably to have no effect.
1233
 
1234
if harzards are tracked, current hazards can be displayed using the
1235
simulator's @command{r} command.
1236
 
1237
@quotation Caution
1238
The code for this does not appear to be complete or well tested, so
1239
users are advised not to use this option.
1240
@end quotation
1241
 
1242
@item dependstats = 0|1
1243
@cindex @code{dependstats} (CPU configuration)
1244
If 1, inter-instruction dependencies are calculated. Default value 0.
1245
 
1246
If these values are calculated, the depencies can be displayed using
1247
the simulator's @command{stat} command.
1248
 
1249
@quotation Note
1250
This field must be enabled, if execution execution flow tracking
1251
(field @code{history}) has been requested in the simulator
1252
configuration section (@pxref{Simulator Behavior, , Simulator
1253
Behavior}).
1254
@end quotation
1255
 
1256
@item sbuf_len = @var{value}
1257
@cindex @code{sbuf_len} (CPU configuration)
1258
The length of the store buffer is set to @var{value}, which must be no
1259
greater than 256. Larger values will be truncated to 256 with a
1260
warning. Negative values will be treated as 0 with a warning. Use 0 to
1261
disable the store buffer.
1262
 
1263
When the store buffer is active, stores are accumulated and committed
1264
when I/O is idle.
1265
 
1266
@end table
1267
 
1268
@node Memory Configuration
1269
@subsection Memory Configuration
1270
@cindex configuring memory
1271
@cindex memory configuration
1272
@cindex @code{section memory}
1273
Memory configuration is described in @code{section memory}. This
1274
section may appear multiple times, specifying multiple blocks of
1275
memory. The following parameters may be specified.
1276
 
1277
@table @code
1278
 
1279
@item type=random|pattern|unknown|zero
1280
@cindex @code{type} (memory configuration)
1281
Specifies the values to which memory should be initialized. The
1282
default value is @code{unknown}.
1283
 
1284
@table @code
1285
 
1286
@item random
1287
@cindex @code{type=random} (memory configuration)
1288
Set the memory values to be a random value. A seed for the random
1289
generator may be set using the @code{random_seed} field in this
1290
section (see below), thus ensuring the same ``random'' values are used
1291
each time.
1292
 
1293
@item pattern
1294
@cindex @code{type=pattern} (memory configuration)
1295
Set the memory values to be a pattern value, which is set using the
1296
@code{pattern} field in this section (see below).
1297
 
1298
@item unknown
1299
@cindex @code{type=unknown} (memory configuration)
1300
The memory values are not initialized (i.e. left ``unknown''). This
1301
option will yield faster initialization of the simulator.
1302
 
1303
@item zero
1304
@cindex @code{type=zero} (memory configuration)
1305
Set the memory values to be 0. This is the equivalent of
1306
@code{type=pattern} and a @code{pattern} value of 0, and implemented
1307
as such.
1308
 
1309
@quotation Note
1310
As a consequence, if the @code{pattern} field is @emph{subsequently}
1311
specified in this section, the value in that field will be used
1312
instead of zero to initialize the memory.
1313
@end quotation
1314
 
1315
@end table
1316
 
1317
@item random_seed = @var{value}
1318
@cindex @code{random_seed} (memory configuration)
1319
Set the seed for the random number generator to @var{value}. This only
1320
has any effect for memory type @code{random}.
1321
 
1322
The default value is -1,
1323
which means the seed will be set from a call to the @code{time}
1324
function, thus ensuring different random values are used on each
1325
run. The simulator prints out the seed used in this case, allowing
1326
repeat runs to regenerate the same random values used in any
1327
particular run.
1328
 
1329
@item pattern = @var{value}
1330
@cindex @code{pattern} (memory configuration)
1331
Set the pattern to be used when initializing memory to
1332
@var{value}. The default value is 0. This only has any effect for
1333
memory type @code{pattern}. The least significant 8 bits of this value
1334
is used to initialize each byte. More than 8 bits can be specified,
1335
but will ignored with a warning.
1336
 
1337
@quotation Tip
1338
The default value, is equivalent to setting the memory @code{type} to
1339
be @code{zero}. If that is what is intended, then using
1340
@code{type=zero} explicitly is better than using @code{type=pattern}
1341
and not specifying a value for @code{pattern}.
1342
@end quotation
1343
 
1344
@item baseaddr = @var{value}
1345
@cindex @code{baseaddr} (memory configuration)
1346
Set the base address of the memory to @var{value}. It should be
1347
aligned to a multiple of the memory size rounded up to the nearest
1348
@math{2^n}. The default value is 0.
1349
 
1350
@item size = @var{value}
1351
@cindex @code{size} (memory configuration)
1352
Set the size of the memory block to be @var{value} bytes. This should be a
1353
multiple of 4 (i.e. word aligned). The default value is 1024.
1354
 
1355
@quotation Note
1356
When allocating memory, the simulator will allocate the nearest
1357
@math{2^n} bytes greater than or equal to @var{value}, and will not
1358
notice memory misses in any part of the memory between @var{value} and
1359
the amount allocated.
1360
 
1361
As a consequence users are strongly recommended to specify memory
1362
sizes that are an exact power of 2. If some other amount of memory is
1363
required, it should be specified as separate, contiguous blocks, each
1364
of which is a power of 2 in size.
1365
@end quotation
1366
 
1367
@item name = "@var{text}"
1368
@cindex @code{name} (memory configuration)
1369
Name the block. Typically these describe the type of memory being
1370
modeled (thus @code{"SRAM"} or @code{"Flash"}. The default is
1371
@code{@w{"anonymous memory block"}}.
1372
 
1373
@quotation Note
1374
It is not clear that this information is currently ever used in normal
1375
operation of the simulator. Even the @command{info} command of the simulator
1376
ignores it.
1377
@end quotation
1378
 
1379
@item ce = @var{value}
1380
@cindex @code{ce} (memory configuration)
1381
Set the chip enable index of the memory instance. Each memory instance
1382
should have a unique chip enable index, which should be greater
1383
than or equal to zero. This is used by the memory controller when
1384
identifying different memory instances.
1385
 
1386
The default value is -1 (invalid).
1387
 
1388
@item mc = @var{value}
1389
@cindex @code{mc} (memory configuration)
1390
Specifies the memory controller this memory is connected to. It should
1391
correspond to the @code{index} field specified in a @code{@w{section
1392
mc}} for a memory controller (@pxref{Memory Controller Configuration,
1393
, Memory Controller Configuration}).
1394
 
1395
Default value is 0, which is also the default value of a memory
1396
controller @code{index} field. This is suitable therefore for designs
1397
with just one memory controller.
1398
 
1399
@item delayr = @var{value}
1400
@cindex @code{delayr} (memory configuration)
1401
The number of cycles required for a read access. Set to -1 if the
1402
memory does not support reading. Default value 1. The simulator will
1403
add this number of cycles to the total instruction cycle count when
1404
reading from main memory.
1405
 
1406
@item delayw = @var{value}
1407
@cindex @code{delayw} (memory configuration)
1408
The number of cycles required for a write access. Set to -1 if the
1409
memory does not support writing. Default value 1. The simulator will
1410
add this number of cycles to the total instruction cycle count when
1411
writing to main memory.
1412
 
1413
@item log = "@var{file}"
1414
@cindex @code{log} (memory configuration)
1415
If specified, @file{file} names a file for all memory accesses to be
1416
logged. If not specified, the default value, NULL is used, meaning
1417
that the memory is not logged.
1418
 
1419
@end table
1420
 
1421
@node Memory Management Configuration
1422
@subsection Memory Management Configuration
1423
@cindex configuring data & instruction MMUs
1424
@cindex MMU configuration
1425
@cindex DMMU configuration
1426
@cindex data MMU configuration
1427
@cindex IMMU configuration
1428
@cindex instruction MMU configuration
1429
@cindex @code{section dmmu}
1430
@cindex @code{section immu}
1431
Memory Management Unit (MMU) configuration is described in
1432
@code{section dmmu} (for the data MMU) and @code{section immu} (for
1433
the instruction MMU). Each section should appear at most once. The
1434
following parameters may be specified.
1435
 
1436
@table @code
1437
 
1438
@item enabled = 0|1
1439
@cindex @code{enabled} (MMU configuration)
1440
If 1 (true), the data or instruction (as appropriate) MMU is
1441
enabled. If 0 (the default), it is disabled.
1442
 
1443
@item nsets = @var{value}
1444
@cindex @code{nsets} (MMU configuration)
1445
Sets the number of data or instruction (as appropriate) TLB sets to
1446
@var{value}, which must be a power of two, not exceeding 128. Values
1447
which do not fit these criteria are ignored with a warning. The
1448
default value is 1.
1449
 
1450
@item nways = @var{value}
1451
@cindex @code{nways} (MMU configuration)
1452
Sets the number of data or instruction (as appropriate) TLB ways to
1453
@var{value}. The value must be in the range 1 to 4. Values outside
1454
this range are ignored with a warning. The default value is 1.
1455
 
1456
@item pagesize = @var{value}
1457
@cindex @code{pagesize} (MMU configuration)
1458
The data or instruction (as appropriate) MMU page size is set to
1459
@var{value}, which must be a power of 2. Values which are not a power
1460
of 2 are ignored with a warning. The default is 8192 (0x2000).
1461
 
1462
@item entrysize = @var{value}
1463
@cindex @code{entrysize} (MMU configuration)
1464
The data or instruction (as appropriate) MMU entry size is set to
1465
@var{value}, which must be a power of 2. Values which are not a power
1466
of 2 are ignored with a warning. The default value is 1.
1467
 
1468
@quotation Note
1469
@value{OR1KSIM} does not appear to use the @code{entrysize} parameter
1470
in its simulation of the MMUs. Thus setting this value does not seem
1471
to matter.
1472
@end quotation
1473
 
1474
@item ustates = @var{value}
1475
@cindex @code{ustates} (MMU configuration)
1476
The number of instruction usage states for the data or instruction (as
1477
appropriate) MMU is set to @var{value}, which must be 2, 3 or
1478
4. Values outside this range are ignored with a warning. The default
1479
value is 2.
1480
 
1481
@quotation Note
1482
@value{OR1KSIM} does not appear to use the @code{ustates} parameter in
1483
its simulation of the MMUs. Thus setting this value does not seem to
1484
matter.
1485
@end quotation
1486
 
1487
@item hitdelay = @var{value}
1488
@cindex @code{hitdelay} (MMU configuration)
1489
Set the number of cycles a data or instruction (as appropriate) MMU
1490
hit costs. Default value 1.
1491
 
1492
@item missdelay = @var{value}
1493
@cindex @code{missdelay} (MMU configuration)
1494
Set the number of cycles a data or instruction (as appropriate) MMU
1495
miss costs. Default value 1.
1496
 
1497
@end table
1498
 
1499
@node Cache Configuration
1500
@subsection Cache Configuration
1501
@cindex configuring data & instruction caches
1502
@cindex cache configuration
1503
@cindex data cache configuration
1504
@cindex instruction cache configuration
1505
@cindex @code{section dc}
1506
@cindex @code{section ic}
1507
Cache configuration is described in @code{section dc} (for the data
1508
cache) and @code{seciton ic} (for the instruction cache). Each section
1509
should appear at most once. The following parameters may be specified.
1510
 
1511
@table @code
1512
 
1513
@item enabled = 0|1
1514
@cindex @code{enabled} (cache configuration)
1515
If 1 (true), the data or instruction (as appropriate) cache is
1516
enabled. If 0 (the default), it is disabled.
1517
 
1518
@item nsets = @var{value}
1519
@cindex @code{nsets} (cache configuration)
1520
Sets the number of data or instruction (as appropriate) cache sets to
1521
@var{value}, which must be a power of two, not exceeding
1522
@code{MAX_DC_SETS} (for the data cache) or @code{MAX_IC_SETS} (for the
1523
instruction cache). At the time of writing, these constants are
1524
both defined in the code to be 1024). The default value is 1.
1525
 
1526
@item nways = @var{value}
1527
@cindex @code{nways} (cache configuration)
1528
Sets the number of data or instruction (as appropriate) cache ways to
1529
@var{value}, which must be a power of two, not exceeding
1530
@code{MAX_DC_WAYS} (for the data cache) or @code{MAX_IC_WAYS} (for the
1531
instruction cache). At the time of writing, these constants are both
1532
defined in the code to be 32). The default value is 1.
1533
 
1534
@item blocksize = @var{value}
1535
@cindex @code{blocksize} (cache configuration)
1536
The data or instruction (as appropriate) cache block size is set to
1537
@var{value} bytes, which must be either 16 or 32. The default is 16.
1538
 
1539
@item ustates = @var{value}
1540
@cindex @code{ustates} (cache configuration)
1541
The number of instruction usage states for the data or instruction (as
1542
appropriate) cache is set to @var{value}, which must be 2, 3 or 4. The
1543
default value is 2.
1544
 
1545
@item hitdelay = @var{value}
1546
@cindex @code{hitdelay} (instruction cache configuration)
1547
@emph{Instruction cache only}. Set the number of cycles an instruction
1548
cache hit costs. Default value 1.
1549
 
1550
@item missdelay = @var{value}
1551
@cindex @code{missdelay} (instruction cache configuration)
1552
@emph{Instruction cache only}. Set the number of cycles an instruction
1553
cache miss costs. Default value 1.
1554
 
1555
@item load_hitdelay = @var{value}
1556
@cindex @code{load_hitdelay} (data cache configuration)
1557
@emph{Data cache only}. Set the number of cycles a data load cache hit
1558
costs. Default value 2.
1559
 
1560
@item load_missdelay = @var{value}
1561
@cindex @code{load_missdelay} (data cache configuration)
1562
@emph{Data cache only}. Set the number of cycles a data load cache
1563
miss costs. Default value 2.
1564
 
1565
@item store_hitdelay = @var{value}
1566
@cindex @code{store_hitdelay} (data cache configuration)
1567
@emph{Data cache only}. Set the number of cycles a data store cache hit
1568
costs. Default value 0.
1569
 
1570
@item store_missdelay = @var{value}
1571
@cindex @code{store_missdelay} (data cache configuration)
1572
@emph{Data cache only}. Set the number of cycles a data store cache
1573
miss costs. Default value 0.
1574
 
1575
@end table
1576
 
1577
@node Interrupt Configuration
1578
@subsection Interrupt Configuration
1579
@cindex configuring the interrupt controller
1580
@cindex interrupt controller configuration
1581
@cindex programmable interrupt controller configuration
1582
@cindex PIC configuration
1583
@cindex @code{section pic}
1584
Programmable Interrupt Controller (PIC) configuration is described in
1585
@code{section pic}. This section may appear at most
1586
once---@value{OR1KSIM} has no mechanism for handling multiple
1587
interrupt controllers. The following parameters may be specified.
1588
 
1589
@table @code
1590
 
1591
@item enabled = 0|1
1592
@cindex @code{enabled} (interrupt controller)
1593
If 1 (true), the programmable interrupt controller is enabled. If 0
1594
(the default), it is disabled.
1595
 
1596
@item edge_trigger = 0|1
1597
@cindex @code{edge_trigger} (interrupt controller)
1598
If 1 (true, the default), the programmable interrupt controller is
1599
edge triggered. If 0 (false), it is level triggered.
1600
 
1601
@end table
1602
 
1603
@node Power Management Configuration
1604
@subsection Power Management Configuration
1605
@cindex configuring power management
1606
@cindex power management configuration
1607
@cindex PMU configuration
1608
@cindex @code{section pmu}
1609
Power management implementation is incomplete. At present the effect
1610
(which only happens when the power management unit is enabled) of
1611
setting the different bits in the power management Special Purpose
1612
Register (PMR, SPR 0x4000) is
1613
 
1614
@table @code
1615
 
1616
@item SDF (bit mask 0x0000000f)
1617
@cindex SDF (power management register)
1618
@cindex slow down factor (power management register)
1619
@cindex power management register, SDF
1620
@cindex PMR - SDF
1621
No effect - these bits are ignored
1622
 
1623
@item DME (bit mask 0x00000010)
1624
@cindex DME (power management register)
1625
@cindex doze mode (power management register)
1626
@cindex power management register, DME
1627
@cindex PMR - DME
1628
@itemx SME (bit mask 0x00000020)
1629
@cindex SME (power management register)
1630
@cindex sleep mode (power management register)
1631
@cindex power management register, SME
1632
@cindex PMR - SME
1633
Both these bits cause the processor to stop executing
1634
instructions. However all other functions (debug interaction, CLI,
1635
VAPI etc) carry on as normal.
1636
 
1637
@item DCGE (bit mask 0x00000004)
1638
@cindex DCGE (power management register)
1639
@cindex dynamic clock gating (power management register)
1640
@cindex power management register, DGCE
1641
@cindex PMR - DGCE
1642
No effect - this bit is ignored
1643
 
1644
@item SUME (bit mask 0x00000008)
1645
@cindex SUME (power management register)
1646
@cindex suspend mode (power management register)
1647
@cindex power management register, SUME
1648
@cindex PMR - SUME
1649
Enabling this bit causes a message to be printed, advising that the
1650
processor is suspending and the simulator exits.
1651
 
1652
@end table
1653
 
1654
On reset all bits are cleared.
1655
 
1656
Power management configuration is described in @code{section pm}. This
1657
section may appear at most once. The following parameter may be specified.
1658
 
1659
@table @code
1660
 
1661
@item enabled = 0|1
1662
@cindex @code{enabled} (power management configuration)
1663
If 1 (true), power management is enabled. If 0 (the default), it is
1664
disabled.
1665
 
1666
@end table
1667
 
1668
@node Branch Prediction Configuration
1669
@subsection Branch Prediction Configuration
1670
@cindex configuring branch prediction
1671
@cindex branch prediction configuration
1672
@cindex BPB configuration
1673
@cindex @code{section bpb}
1674
From examining the code base, it seems the branch prediction function
1675
is not fully implemented. At present the functionality seems
1676
restricted to collection of statistics.
1677
 
1678
Branch prediction configuration is described in @code{section bpb}. This
1679
section may appear at most once. The following parameters may be specified.
1680
 
1681
@table @code
1682
 
1683
@item enabled = 0|1
1684
@cindex @code{enabled} (branch prediction configuration)
1685
If 1 (true), branch prediction is enabled. If 0 (the default), it is
1686
disabled.
1687
 
1688
@item btic = 0|1
1689
@cindex @code{btic} (branch prediction configuration)
1690
If 1 (true), the branch target instruction cache model is enabled. If
1691
 
1692
 
1693
@item sbp_bf_fwd = 0|1
1694
@cindex @code{sbp_bf_fwd} (branch prediction configuration)
1695
If 1 (true), use forward prediction for the @code{l.bf} instruction. If
1696
 
1697
 
1698
@item sbp_bnf_fwd = 0|1
1699
@cindex @code{sbp_bnf_fwd} (branch prediction configuration)
1700
If 1 (true), use forward prediction for the @code{l.bnf} instruction. If
1701
 
1702
 
1703
@item hitdelay = @var{value}
1704
@cindex @code{hitdelay} (branch prediction configuration)
1705
Set the number of cycles a branch prediction hit costs. Default value
1706
0.
1707
 
1708
@item missdelay = @var{value}
1709
@cindex @code{missdelay} (branch prediction configuration)
1710
Set the number of cycles a branch prediction miss costs. Default value
1711
0.
1712
 
1713
@end table
1714
 
1715
@node Debug Interface Configuration
1716
@subsection Debug Interface Configuration
1717
@cindex configuring the debug unit and interface to external debuggers
1718
@cindex debug unit configuration
1719
@cindex debug interface configuration
1720
@cindex @code{section debug}
1721
The debug unit and debug interface configuration is described in
1722
@code{@w{section debug}}. This section may appear at most once. The
1723
following parameters may be specified.
1724
 
1725
@table @code
1726
 
1727
@item enabled = 0|1
1728
@cindex @code{enabled} (debug interface configuration)
1729
If 1 (true), the debug unit is enabled. If 0 (the default), it is disabled.
1730
 
1731
@quotation Note
1732
This enables the functionality of the debug unit (its registers etc) within
1733
the mode. It does not provide any external interface to the debug unit. For
1734
that, see @code{gdb_enabled} and @code{rsp_enabled} below.
1735
@end quotation
1736
 
1737
@item rsp_enabled = 0|1
1738
@cindex @code{rsp_enabled} (debug interface configuration)
1739
@cindex Remote Serial Protocol
1740
If 1 (true), the GDB @dfn{Remote Serial Protocol} server is started, provding
1741
an interface to an external GNU debugger, using the port specified in the
1742
@code{rsp_port} field (see below), or the @code{or1ksim-rsp} TCP/IP
1743
service. If 0 (the default), the server is not started, and no external
1744
interface is provided.
1745
 
1746
For more detailed information on the interface to the GNU Debugger see
1747
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger Practical
1748
Experience with the OpenRISC 1000 Architecture}, by Jeremy Bennett, published
1749
by Embecosm Limited (@url{www.embecosm.com}).
1750
 
1751
@quotation Note
1752
@code{rsp_enabled} may not be enabled with @code{gdb_enabled} (see below). If
1753
both are enabled, a warning is issued and only the @dfn{Remote Serial
1754
Protocol} interface is enabled.
1755
@end quotation
1756
 
1757
@item rsp_port = @var{value}
1758
@cindex @code{rsp_port} (debug interface configuration)
1759
@var{value} specifies the port to be used for the GDB @dfn{Remote Serial
1760
Protocol} interface to the GNU Debugger (GDB). Default value 51000. If
1761
the value 0 is specified, @value{OR1KSIM} will instead look for a TCP/IP
1762
service named @code{or1ksim-rsp}.
1763
 
1764
@quotation Tip
1765
@cindex TCP/IP port range for @code{or1ksim-rsp} service
1766
There is no registered port for @value{OR1KSIM} @dfn{Remote Serial Protocol}
1767
service @code{or1ksim-rsp}. Good practice suggests users should adopt port
1768
values in the @dfn{Dynamic} or @dfn{Private} port range, i.e. 49152-65535.
1769
@end quotation
1770
 
1771
@item gdb_enabled = 0|1
1772
@cindex @code{gdb_enabled} (debug interface configuration)
1773
If 1 (true), the OpenRISC Remote JTAG protocol server is started, provding an
1774
interface to an external GNU debugger, using the port specified in the
1775
@code{server_port} field (see below), or the @code{or1ksim} TCP/IP service. If
1776
 
1777
provided.
1778
 
1779
For more detailed information on the interface to the GNU Debugger see
1780
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger Practical
1781
Experience with the OpenRISC 1000 Architecture}, by Jeremy Bennett, published
1782
by Embecosm Limited (@url{www.embecosm.com}).
1783
 
1784
@quotation Note
1785
The OpenRISC Remote JTAG protocol is unique to OpenRISC, and remains only for
1786
backward compatibility. New users should adopt the standard GDB @dfn{Remote
1787
Serial Protocol} interface (see @code{rsp_enabled} above) providing access to
1788
a wider range of GDB functionality.
1789
@end quotation
1790
 
1791
@quotation Note
1792
@code{gdb_enabled} may not be enabled with @code{rsp_enabled}. If both are
1793
enabled, a warning is issued and only the @dfn{Remote Serial Protocol}
1794
interface is enabled.
1795
@end quotation
1796
 
1797
@item server_port = @var{value}
1798
@cindex @code{server_port} (debug interface configuration)
1799
@var{value} specifies the port to be used for the OpenRISC Rmote JTAG
1800
protocol interface to the GNU Debugger (GDB). Default value 51000. If
1801
the value 0 is specified, @value{OR1KSIM} will instead look for a TCP/IP
1802
service named @code{or1ksim}.
1803
 
1804
@quotation Tip
1805
@cindex TCP/IP port range for @code{or1ksim} service
1806
There is no registered port for @value{OR1KSIM} Remote JTAG Interface
1807
or service @code{or1ksim}. Good practice suggests users should adopt
1808
port values in the @dfn{Dynamic} or @dfn{Private} port range,
1809
i.e. 49152-65535.
1810
@end quotation
1811
 
1812
@item vapi_id = @var{value}
1813
@cindex @code{vapi_id} (debug interface configuration)
1814
@var{value} specifies the value of the Verification API (VAPI) base
1815
address to be used with the debug unit. @xref{Verification API, ,
1816
Verification API}, for more details.
1817
 
1818
If this is specified and @var{value} is non-zero, all OpenRISC Remote
1819
JTAG protocol transactions will be logged to the VAPI log file, if
1820
enabled. This is the only functionality associated with VAPI for the
1821
debug unit. No VAPI commands are sent, nor requests handled.
1822
 
1823
@end table
1824
 
1825
@node Peripheral Configuration
1826
@section Configuring Memory Mapped Peripherals
1827
 
1828
All peripheral components are optional. If they are specified, then
1829
(unlike other components) by default they are enabled.
1830
 
1831
@menu
1832
* Memory Controller Configuration::
1833
* UART Configuration::
1834
* DMA Configuration::
1835
* Ethernet Configuration::
1836
* GPIO Configuration::
1837
* Display Interface Configuration::
1838
* Frame Buffer Configuration::
1839
* Keyboard Configuration::
1840
* Disc Interface Configuration::
1841
* Generic Peripheral Configuration::
1842
@end menu
1843
 
1844
@node Memory Controller Configuration
1845
@subsection Memory Controller Configuration
1846
@cindex configuring the memory controller
1847
@cindex memory controller configuration
1848
@cindex @code{section mc}
1849
The memory controller used in @value{OR1KSIM} is the component
1850
implemented at OpenCores, and found in the top level CVS directory,
1851
@file{mem_ctrl}. It is described in the document @cite{Memory
1852
Controller IP Core} by Rudolf Usselmann, which can be found in the
1853
@file{doc} subdirectory. It is a memory mapped component, which
1854
resides on the main OpenRISC Wishbone data bus.
1855
 
1856
The memory controller configuration is described in @code{@w{section
1857
mc}}. This section may appear multiple times, specifying multiple
1858
memory controllers. The following parameters may be specified.
1859
 
1860
@table @code
1861
 
1862
@item enabled = 0|1
1863
@cindex @code{enabled} (memory controller configuration)
1864
If 1 (true, the default), this memory controller is enabled. If 0, it is
1865
disabled.
1866
 
1867
@quotation Note
1868
The memory controller can effectively also be disabled by setting an
1869
appropriate power on control register value (see below). However this
1870
should only be used if it is desired to specifically model this
1871
behavior of the memory controller, not as a way of disabling the
1872
memory controller in general.
1873
@end quotation
1874
 
1875
@item baseaddr = @var{value}
1876
@cindex @code{baseaddr} (memory controller configuration)
1877
Set the base address of the memory controller's memory mapped
1878
registers to @var{value}. The default is 0, which is probably not a
1879
sensible value.
1880
 
1881
The memory controller has a 7 bit address bus, with a total of 19
1882
32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1883
addresses 0x50 through 0x7c are not used).
1884
 
1885
@item poc = @var{value}
1886
@cindex @code{poc} (memory controller configuration)
1887
Specifies the value of the power on control register, The least
1888
signficant two bits specify the bus width (use 0 for an 8-bit bus, 1
1889
for a 16-bit bus and 2 for a 32-bit bus) and the next two bits the
1890
type of memory connected (use 0 for a disabled interface, 1 for SSRAM,
1891
2 for asyncrhonous devices and 3 for synchronous devices).
1892
 
1893
If other bits are specified, they are ignored with a warning.
1894
 
1895
@quotation Caution
1896
The default value, 0, corresponds to a disabled 8-bit bus, and
1897
is likely not the most suitable value
1898
@end quotation
1899
 
1900
@item index = @var{value}
1901
@cindex @code{index} (memory controller configuration)
1902
Specify the index of this memory controller amongst all the memory
1903
controllers. This value should be unique for each memory controller,
1904
and is used to associate specific memories with the controller,
1905
through the @code{mc} field in the @code{@w{section memory}}
1906
configuration (@pxref{Memory Configuration, , Memory Configuration}).
1907
 
1908
The default value, 0, is suitable when there is only one memory controller.
1909
 
1910
@end table
1911
 
1912
@node UART Configuration
1913
@subsection UART Configuration
1914
@cindex configuring the UART
1915
@cindex UART configuration
1916
@cindex @code{section uart}
1917
The UART implemented in @value{OR1KSIM} follows the specification of the
1918
National Semiconductor 16450 and 16550 parts. It is a memory mapped
1919
component, which resides on the main OpenRISC Wishbone data bus.
1920
 
1921
The component provides a number of interfaces to emulate the behavior
1922
of an external terminal connected to the UART.
1923
 
1924
UART configuration is described in @code{section uart}. This section
1925
may appear multiple times, specifying multiple UARTs. The following
1926
parameters may be specified.
1927
 
1928
@table @code
1929
 
1930
@item enabled = 0|1
1931
@cindex @code{enabled} (UART configuration)
1932
If 1 (true, the default), this UART is enabled. If 0, it is disabled.
1933
 
1934
@item baseaddr = @var{value}
1935
@cindex @code{baseaddr} (UART configuration)
1936
Set the base address of the UART's memory mapped
1937
registers to @var{value}. The default is 0, which is probably not a
1938
sensible value.
1939
 
1940
The UART has a 3 bit address bus, with a total of 8 8-bit registers,
1941
at addresses 0x0 through 0x7.
1942
 
1943
@item channel = "@var{type}:@var{args}"
1944
@cindex @code{channel} (UART configuration)
1945
Specify the channel representing the terminal connected to the UART
1946
Rx & Tx pins.
1947
 
1948
@table @code
1949
 
1950
@item channel="file:@file{rxfile},@file{txfile}"
1951
@cindex UART I/O from/to files
1952
Read input characters from the file @file{rxfile} and write output
1953
characters to the file @file{txfile} (which will be created if
1954
required).
1955
 
1956
@item channel="xterm:@var{args}"
1957
@cindex UART I/O from/to an @command{xterm}
1958
Create an xterm on startup, write UART Tx traffic to the xterm and
1959
take Rx traffic from the keyboard when the xterm window is
1960
selected. Additional arguments to the xterm command (for example
1961
specifying window size may be specified in @var{args}, or this may be
1962
left blank.
1963
 
1964
@item channel="tcp:@var{value}"
1965
@cindex UART I/O from/to TCP/IP
1966
Open the TCP/IP port specified by @var{value} and read and write UART
1967
traffic from and to it.
1968
 
1969
Typically a telnet session is connected to the other end of this port.
1970
 
1971
@quotation Tip
1972
There is no registered port for @value{OR1KSIM} telnet UART
1973
connection. Priviledged access is required to read traffic on the
1974
registered ``well-known'' telnet port (23). Instead users should use
1975
port values in the @dfn{Dynamic} or @dfn{Private} port range,
1976
i.e. 49152-65535.
1977
@end quotation
1978
 
1979
@item channel="fd:@code{rxfd},@code{txfd}"
1980
@cindex UART I/O from/to open file descriptors
1981
Read and write characters from and to the existing open numerical file
1982
descriptors, file @code{rxfd} and @code{txfd}.
1983
 
1984
@item channel="tty:device=/dev/ttyS0,baud=9600"
1985
@cindex UART I/O from/to a physical serial port
1986
Read and write characters from and to a physical serial port. The
1987
precise device (shown here as @code{/dev/ttyS0}) may vary from machine
1988
to machine.
1989
 
1990
@end table
1991
 
1992
The default value for this field is @code{"xterm:"}.
1993
 
1994
@item irq = @var{value}
1995
@cindex @code{irq} (UART configuration)
1996
Use @var{value} as the IRQ number of this UART. Default value 0.
1997
 
1998
@item 16550 = 0|1
1999
@cindex @code{16550} (UART configuration)
2000
If 1 (true), the UART has the functionality of a 16550. If 0 (the
2001
default), it has the functionality of a 16450. The principal
2002
difference is that the 16550 can buffer multiple characters.
2003
 
2004
@item jitter = @var{value}
2005
@cindex @code{jitter} (UART configuration)
2006
Set the jitter, modeled as a time to block, to @var{value}
2007
milliseconds. Set to -1 to disable jitter modeling. Default value 0.
2008
 
2009
@quotation Note
2010
This functionality has yet to be implemented, so this parameter has no
2011
effect.
2012
@end quotation
2013
 
2014
@item vapi_id = @var{value}
2015
@cindex @code{vapi_id} (UART configuration)
2016
@var{value} specifies the value of the Verification API (VAPI) base
2017
address to be used with the UART. @xref{Verification API, ,
2018
Verification API}, for more details, which details the use of the VAPI
2019
with the UART.
2020
 
2021
@end table
2022
 
2023
@node DMA Configuration
2024
@subsection DMA Configuration
2025
@cindex configuring DMA
2026
@cindex DMA configuration
2027
@cindex @code{section dma}
2028
The DMA controller used in @value{OR1KSIM} is the component
2029
implemented at OpenCores, and found in the top level CVS directory,
2030
@file{wb_dma}. It is described in the document @cite{Wishbone
2031
DMA/Bridge IP Core} by Rudolf Usselmann, which can be found in the
2032
@file{doc} subdirectory. It is a memory mapped component, which
2033
resides on the main OpenRISC Wishbone data bus. The present
2034
implementation is incomplete, intended only to support the Ethernet
2035
interface (@pxref{Ethernet Configuration}), although the Ethernet
2036
interface is not yet completed.
2037
 
2038
DMA configuration is described in @code{@w{section dma}}. This section
2039
may appear multiple times, specifying multiple DMA controllers. The
2040
following parameters may be specified.
2041
 
2042
@table @code
2043
 
2044
@item enabled = 0|1
2045
@cindex @code{enabled} (DMA configuration)
2046
If 1 (true, the default), this DMA controller is enabled. If 0, it is disabled.
2047
 
2048
@item baseaddr = @var{value}
2049
@cindex @code{baseaddr} (DMA configuration)
2050
Set the base address of the DMA's memory mapped
2051
registers to @var{value}. The default is 0, which is probably not a
2052
sensible value.
2053
 
2054
The DMA controller has a 10 bit address bus, with a total of 253
2055
32-bit registers. The first 5 registers at addresses 0x000 through
2056
0x010 control the overall behavior of the DMA controller. There are
2057
then 31 blocks of 8 registers, controlling each of the 31 DMA channels
2058
available. Addresses 0x014 through 0x01c are not used.
2059
 
2060
@item irq = @var{value}
2061
@cindex @code{irq} (DMA configuration)
2062
Use @var{value} as the IRQ number of this DMA controller. Default value 0.
2063
 
2064
@item vapi_id = @var{value}
2065
@cindex @code{vapi_id} (DMA configuration)
2066
@var{value} specifies the value of the Verification API (VAPI) base
2067
address to be used with the DMA controller. @xref{Verification API, ,
2068
Verification API}, for more details, which details the use of the VAPI
2069
with the DMA controller.
2070
 
2071
@end table
2072
 
2073
@node Ethernet Configuration
2074
@subsection Ethernet Configuration
2075
@cindex configuring the Ethernet interface
2076
@cindex Ethernet configuration
2077
@cindex @code{section ethernet}
2078
The Ethernet MAC used in @value{OR1KSIM} is the component implemented
2079
at OpenCores, and found in the top level CVS directory,
2080
@file{ethernet}. It also forms part of the OpenRISC SoC, ORPSoC. It is
2081
described in the document @cite{Ethernet IP Core Specification} by
2082
Igor Mohor, which can be found in the @file{doc} subdirectory. It is a
2083
memory mapped component, which resides on the main OpenRISC Wishbone
2084
data bus.
2085
 
2086
Ethernet configuration is described in @code{section ethernet}. This
2087
section may appear multiple times, specifying multiple Ethernet
2088
interfaces. The following parameters may be specified.
2089
 
2090
@table @code
2091
 
2092
@item enabled = 0|1
2093
@cindex @code{enabled} (Ethernet configuration)
2094
If 1 (true, the default), this Ethernet MAC is enabled. If 0, it is
2095
disabled.
2096
 
2097
@item baseaddr = @var{value}
2098
@cindex @code{baseaddr} (Ethernet configuration)
2099
Set the base address of the MAC's memory mapped registers to
2100
@var{value}. The default is 0, which is probably not a sensible value.
2101
 
2102
The Ethernet MAC has a 7-bit address bus, with a total of 21
2103
32-bit registers. Addresses 0x54 through 0x7c are not used.
2104
 
2105
@quotation Note
2106
The Ethernet specification describes a Tx control register,
2107
@code{TXCTRL}, at address 0x50. However this register is not
2108
implemented in the @value{OR1KSIM} model.
2109
@end quotation
2110
 
2111
@item dma = @var{value}
2112
@cindex @code{dma} (Ethernet configuration)
2113
@var{value} specifies the DMA controller with which this Ethernet is
2114
associated. The default value is 0.
2115
 
2116
@quotation Note
2117
Support for external DMA is not provided in the current
2118
implementation, and this value is ignored. In any case there is no
2119
equivalent field to which this can be matched in the current DMA
2120
component implementation (@pxref{DMA Configuration, , DMA
2121
Configuration}).
2122
@end quotation
2123
 
2124
@item irq = @var{value}
2125
@cindex @code{dma} (Ethernet configuration)
2126
Use @var{value} as the IRQ number of this Ethernet MAC. Default value 0.
2127
 
2128
@item rtx_type = 0|1
2129
@cindex @code{rtx_type} (Ethernet configuration)
2130
If 1 (true) use a socket interface to the Ethernet (see parameter
2131
@code{sockif} below). If 0 (the default), use a file interface,
2132
reading and writing from and to the files specified in the
2133
@code{rxfile} and @code{txfile} parameters (see below).
2134
 
2135
@quotation Note
2136
By default the socket interface is not provided in @value{OR1KSIM}. If
2137
it is required, this must be requested when configuring, by use of the
2138
@code{--enable-ethphy} option to @command{configure}.
2139
 
2140
@example
2141
configure --target=or32-uclinux --enable-ethphy ...
2142
@end example
2143
@end quotation
2144
 
2145
@item rx_channel = @var{rxvalue}
2146
@cindex @code{rx_channel} (Ethernet configuration)
2147
@itemx tx_channel = @var{txvalue}
2148
@cindex @code{tx_channel} (Ethernet configuration)
2149
@var{rxvalue} specifies the DMA channel to use for receive and
2150
@var{txvalue} the DMA channel to use for transmit. Both default to 0.
2151
 
2152
@quotation Note
2153
As noted above, support for external DMA is not provided in the
2154
current implementation, and so these values are ignored.
2155
@end quotation
2156
 
2157
@item rxfile = "@var{rxfile}"
2158
@cindex @code{rxfile} (Ethernet configuration)
2159
@itemx txfile = "@var{txfile}"
2160
@cindex @code{txfile} (Ethernet configuration)
2161
When @code{rtx_type} is 0 (see above), @var{rxfile} specifies the file
2162
to use as input and @var{txfile} specifies the fie to use as
2163
output.
2164
 
2165
The file contains a sequence of packets. Each packet consists of a
2166
packet length (32 bits), followed by that many bytes of data. Once the
2167
input file is empty, the Ethernet MAC behaves as though there were no
2168
data on the Ethernet. The default values of these parameters are
2169
@code{"eth_rx"} and @code{"eth_tx"} respectively.
2170
 
2171
The input file must exist and be readable. The output file must be
2172
writable and will be created if necessary. If either of these
2173
conditions is not met, a warning will be given.
2174
 
2175
@item sockif = "@var{service}"
2176
@cindex @code{sockif} (Ethernet configuration)
2177
When @code{rtx_type} is 1 (see above), @var{service} specifies the
2178
service to use for communication. This may be TCP/IP or UDP/IP. The
2179
default value of this parameter is @code{"or1ksim_eth"}.
2180
 
2181
@item vapi_id = @var{value}
2182
@cindex @code{vapi_id} (DMA configuration)
2183
@var{value} specifies the value of the Verification API (VAPI) base
2184
address to be used with the Ethernet PHY. @xref{Verification API, ,
2185
Verification API}, for more details, which details the use of the VAPI
2186
with the DMA controller.
2187
 
2188
@end table
2189
 
2190
@node GPIO Configuration
2191
@subsection GPIO Configuration
2192
@cindex configuring the GPIO
2193
@cindex GPIO configuration
2194
@cindex @code{section cpio}
2195
The GPIO used in @value{OR1KSIM} is the component implemented at
2196
OpenCores, and found in the top level CVS directory, @file{gpio}. It
2197
is described in the document @cite{GPIO IP Core Specification} by
2198
Damjan Lampret and Goran Djakovic, which can be found in the
2199
@file{doc} subdirectory. It is a memory mapped component, which
2200
resides on the main OpenRISC Wishbone data bus.
2201
 
2202
GPIO configuration is described in @code{@w{section gpio}}. This section
2203
may appear multiple times, specifying multiple GPIO devices. The
2204
following parameters may be specified.
2205
 
2206
@table @code
2207
 
2208
@item enabled = 0|1
2209
@cindex @code{enabled} (GPIO configuration)
2210
If 1 (true, the default), this GPIO is enabled. If 0, it is disabled.
2211
 
2212
@item baseaddr = @var{value}
2213
@cindex @code{baseaddr} (GPIO configuration)
2214
Set the base address of the GPIO's memory mapped
2215
registers to @var{value}. The default is 0, which is probably not a
2216
sensible value.
2217
 
2218
The GPIO has a 6 bit address bus, with a total of 10 32-bit registers,
2219
although the number of bits that are actively used varies. Addresses
2220
0x28 through 0x3c are not used.
2221
 
2222
@item irq = @var{value}
2223
@cindex @code{irq} (GPIO configuration)
2224
Use @var{value} as the IRQ number of this GPIO. Default value 0.
2225
 
2226
@item vapi_id = @var{value}
2227
@cindex @code{vapi_id} (GPIO configuration)
2228
@cindex @code{base_vapi_id} (GPIO configuration - deprecated)
2229
@var{value} specifies the value of the Verification API (VAPI) base
2230
address to be used with the GPIO. @xref{Verification API, ,
2231
Verification API}, for more details, which details the use of the VAPI
2232
with the GPIO controller. For backwards compatibility, the
2233
alternative name @code{base_vapi_id} is supported for this parameter,
2234
but deprecated.
2235
 
2236
@end table
2237
 
2238
@node Display Interface Configuration
2239
@subsection Display Interface Configuration
2240
@cindex configuring the VGA interface
2241
@cindex display interface configuration
2242
@cindex VGA configuration
2243
@cindex @code{section vga}
2244
@value{OR1KSIM} models a VGA interface to an external monitor.  The
2245
VGA controller used in @value{OR1KSIM} is the component implemented at
2246
OpenCores, and found in the top level CVS directory, @file{vga_lcd},
2247
with no support for the optional hardware cursors. It is described in
2248
the document @cite{VGA/LCD Core v2.0 Specifications} by Richard
2249
Herveille, which can be found in the @file{doc} subdirectory. It is a
2250
memory mapped component, which resides on the main OpenRISC Wishbone
2251
data bus.
2252
 
2253
The current implementation provides only functionality to dump the
2254
screen to a file at intervals.
2255
 
2256
VGA controller configuration is described in @code{@w{section
2257
vga}}. This section may appear multiple times, specifying multiple
2258
VGA controllers. The following parameters may be specified.
2259
 
2260
@table @code
2261
 
2262
@item enabled = 0|1
2263
@cindex @code{enabled} (VGA configuration)
2264
If 1 (true, the default), this VGA is enabled. If 0, it is disabled.
2265
 
2266
@item baseaddr = @var{value}
2267
@cindex @code{baseaddr} (VGA configuration)
2268
Set the base address of the VGA controller's memory mapped
2269
registers to @var{value}. The default is 0, which is probably not a
2270
sensible value.
2271
 
2272
The VGA controller has a 12-bit address bus, with 7 32-bit registers, at
2273
addresses 0x000 through 0x018, and two color lookup tables at
2274
addresses 0x800 through 0xfff. The hardware cursor registers are not
2275
implemented, so addresses 0x01c through 0x7fc are not used.
2276
 
2277
@item irq = @var{value}
2278
@cindex @code{irq} (VGA configuration)
2279
Use @var{value} as the IRQ number of this VGA controller. Default
2280
value 0.
2281
 
2282
@item refresh_rate = @var{value}
2283
@cindex @code{refresh_rate} (VGA configuration)
2284
@var{value} specifies number of cycles between screen dumps. Default
2285
value is derived from the simulation clock cycle time
2286
(@pxref{Simulator Behavior, , Simulator Behavior}), to correspond
2287
to dumping 50 times per simulated second.
2288
 
2289
@item txfile = "@var{file}"
2290
@cindex @code{txfile} (VGA configuration)
2291
@cindex @code{filename} (VGA configuration - deprecated)
2292
@var{file} specifies the base of the filename for screen
2293
dumps. Successive screen dumps will be in BMP format, in files with
2294
the name @file{@var{file}@var{nnnn}.bmp}, where @var{nnnn} is a
2295
sequential count of the screen dumps starting at zero. The default
2296
value is @code{"vga_out"}. For backwards compatibility, the
2297
alternative name @code{filename} is supported for this parameter,
2298
but deprecated.
2299
 
2300
@end table
2301
 
2302
@node Frame Buffer Configuration
2303
@subsection Frame Buffer Configuration
2304
@cindex configuring the frame buffer
2305
@cindex frame buffer configuration
2306
@cindex @code{section fb}
2307
@quotation Caution
2308
The frame buffer is only partially implemented. Its configuration
2309
fields are described here, but the component should not be used at
2310
this time. Like the VGA controller, it is designed to make screen
2311
dumps to file.
2312
@end quotation
2313
 
2314
Frame buffer configuration is described in @code{section fb}. This
2315
section may appear multiple times, specifying multiple frame
2316
buffers. The following parameters may be specified.
2317
 
2318
@table @code
2319
 
2320
@item enabled = 0|1
2321
@cindex @code{enabled} (frame buffer configuration)
2322
If 1 (true, the default), this frame buffer is enabled. If 0, it is disabled.
2323
 
2324
@item baseaddr = @var{value}
2325
@cindex @code{baseaddr} (frame buffer configuration)
2326
Set the base address of the frame buffer's memory mapped registers to
2327
@var{value}. The default is 0, which is probably not a sensible value.
2328
 
2329
The frame buffer has an 121-bit address bus, with 4 32-bit registers,
2330
at addresses 0x000 through 0x00c, and a PAL lookup table at addresses
2331
0x400 through 0x4ff. Addresses 0x010 through 0x3fc and addresses 0x500
2332
through 0x7ff are not used.
2333
 
2334
@item refresh_rate = @var{value}
2335
@cindex @code{refresh_rate} (frame buffer configuration)
2336
@var{value} specifies number of cycles between screen dumps. Default
2337
value is derived from the simulation clock cycle time
2338
(@pxref{Simulator Behavior, , Simulator Behavior}), to correspond to
2339
dumping 50 times per simulated second.
2340
 
2341
@item txfile = "@var{file}"
2342
@cindex @code{txfile} (frame buffer configuration)
2343
@cindex @code{filename} (frame buffer configuration - deprecated)
2344
@var{file} specifies the base of the filename for screen
2345
dumps. Successive screen dumps will be in BMP format, in files with
2346
the name @file{@var{file}@var{nnnn}.bmp}, where @var{nnnn} is a
2347
sequential count of the screen dumps starting at zero. The default
2348
value is @code{"fb_out"}. For backwards compatibility, the
2349
alternative name @code{filename} is supported for this parameter,
2350
but deprecated.
2351
 
2352
@end table
2353
 
2354
@node Keyboard Configuration
2355
@subsection Keyboard Configuration (PS2)
2356
@cindex configuring the keyboard interface
2357
@cindex configuring the PS2 interface
2358
@cindex keyboard configuration
2359
@cindex PS2 configuration
2360
@cindex @code{section kb}
2361
The PS2 interface provided by @value{OR1KSIM} is not documented. It
2362
may be based on the PS2 project at OpenCores, and found in
2363
the top level CVS directory, @file{ps2}. However this project lacks
2364
any documentation beyond its project webpage. Since most PS2
2365
interfaces follow the Intel i8042 standard, this is presumably what is
2366
expected with this device.
2367
 
2368
The implementation only provides for keyboard support, which is
2369
modelled as a file of keystrokes. There is no mouse support.
2370
 
2371
@quotation Caution
2372
A standard i8042 device has two registers at addresses 0x60 (command)
2373
and 0x64 (status). Inspection of the code, suggests that the
2374
@value{OR1KSIM} component places these registers at addresses 0x00 and
2375
0x04.
2376
 
2377
The port of Linux for the OpenRISC 1000, which runs on @value{OR1KSIM}
2378
implements the i8042 device driver, anticipating these registers
2379
reside at their conventional address. It seems unlikel that this code
2380
will work.
2381
 
2382
This component should be used with caution.
2383
@end quotation
2384
 
2385
Keyboard configuration is described in @code{section kbd}. This
2386
section may appear multiple times, specifying multiple keyboard
2387
interfaces. The following parameters may be specified.
2388
 
2389
@table @code
2390
 
2391
@item enabled = 0|1
2392
@cindex @code{enabled} (keyboard configuration)
2393
If 1 (true, the default), this keyboard is enabled. If 0, it is disabled.
2394
 
2395
@item baseaddr = @var{value}
2396
@cindex @code{baseaddr} (keyboard configuration)
2397
Set the base address of the keyboard's memory mapped registers to
2398
@var{value}. The default is 0, which is probably not a sensible value.
2399
 
2400
The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit registers,
2401
at addresses 0x000 and 0x004.
2402
 
2403
@quotation Caution
2404
As noted above, a standard Intel 8042 interface would expect to find
2405
these registers at locations 0x60 and 0x64, thus requiring at least a
2406
7-bit bus.
2407
@end quotation
2408
 
2409
@item irq = @var{value}
2410
@cindex @code{irq} (keyboard configuration)
2411
Use @var{value} as the IRQ number of this Keyboard interface. Default
2412
value 0.
2413
 
2414
@item rxfile = "@var{file}"
2415
@cindex @code{file} (keyboard configuration)
2416
@file{file} specifies a file containing raw key stroke data, which
2417
models the input from a physical keyboard. The default value is
2418
@code{"kbd_in"}.
2419
 
2420
@end table
2421
 
2422
@node Disc Interface Configuration
2423
@subsection Disc Interface Configuration
2424
@cindex configuring the ATA/ATAPI interfaces
2425
@cindex disc interface configuration
2426
@cindex ATA/ATAPI configuration
2427
@cindex @code{section ata}
2428
The ATA/ATAPI disc controller used in @value{OR1KSIM} is the OCIDEC
2429
(OpenCores IDE Controller) component implemented at OpenCores, and
2430
found in the top level CVS directory, @file{ata}. It is described in
2431
the document @cite{ATA/ATAPI-5 Core Specification} by Richard
2432
Herveille, which can be found in the @file{doc} subdirectory. It is a
2433
memory mapped component, which resides on the main OpenRISC Wishbone
2434
data bus.
2435
 
2436
ATA/ATAPI configuration is described in @code{@w{section ata}}. This section
2437
may appear multiple times, specifying multiple disc controllers. The
2438
following parameters may be specified.
2439
 
2440
@table @code
2441
 
2442
@item enabled = 0|1
2443
@cindex @code{enabled} (ATA/ATAPI configuration)
2444
If 1 (true, the default), this ATA/ATAPI interface is enabled. If 0,
2445
it is disabled.
2446
 
2447
@item baseaddr = @var{value}
2448
@cindex @code{baseaddr} (ATA/ATAPI configuration)
2449
Set the base address of the ATA/ATAPI interface's memory mapped
2450
registers to @var{value}. The default is 0, which is probably not a
2451
sensible value.
2452
 
2453
The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8 32-bit
2454
registers. Depending on the version of the OCIDEC ATA/ATAPI interface
2455
selected (see @code{dev_id} below), not all registers will be available.
2456
 
2457
@item irq = @var{value}
2458
@cindex @code{irq} (ATA/ATAPI configuration)
2459
Use @var{value} as the IRQ number of this ATA/ATAPI interface. Default
2460
value 0.
2461
 
2462
@item dev_id = 1|2|3
2463
@cindex @code{dev_id} (ATA/ATAPI configuration)
2464
This parameter specifies which version of the OCIDEC ATA/ATAPI
2465
interface to model. The default value is 1.
2466
 
2467
Version 1 supports only the @code{CTRL}, @code{STAT} and @code{PCTR}
2468
registers. Versions 2 & 3 add the @code{FCTR} registers, Version 3
2469
adds the @code{DTR} registers and the @code{RXD}/@code{TXD} registers.
2470
 
2471
@item rev = @var{value}
2472
@cindex @code{rev} (ATA/ATAPI configuration)
2473
Set the @var{value} as the revision of the OCIDEC ATA/ATAPI
2474
interface. The default value is 1. The default value is 0. Its value
2475
should be in the range 0-15. Larger values are truncated with a
2476
warning. This only affects the reset value of the @code{STAT}
2477
register, where it forms bits 24-27.
2478
 
2479
@item pio_mode0_t1 = @var{value}
2480
@cindex @code{pio_mode0_t1} (ATA/ATAPI configuration)
2481
@itemx pio_mode0_t2 = @var{value}
2482
@cindex @code{pio_mode0_t2} (ATA/ATAPI configuration)
2483
@itemx pio_mode0_t4 = @var{value}
2484
@cindex @code{pio_mode0_t4} (ATA/ATAPI configuration)
2485
@itemx pio_mode0_teoc = @var{value}
2486
@cindex @code{pio_mode0_teoc} (ATA/ATAPI configuration)
2487
These parameters specify the timings for use with Programmed
2488
Input/Output (PIO) transfers. They are specified as the number of
2489
clock cycles - 2, rounded up to the next highest integer, or zero if
2490
that would be negative. The values should not exceed 255. If they do,
2491
they will be ignored with a warning.
2492
 
2493
See the ATA/ATAPI-5 specification for explanations of each of these
2494
timing parameters. The default values are:
2495
 
2496
@example
2497
pio_mode0_t1   =  6
2498
pio_mode0_t2   = 28
2499
pio_mode0_t4   =  2
2500
pio_mode0_teoc = 23
2501
@end example
2502
 
2503
@item dma_mode0_tm = @var{value}
2504
@cindex @code{dma_mode0_tm} (ATA/ATAPI configuration)
2505
@itemx dma_mode0_td = @var{value}
2506
@cindex @code{dma_mode0_td} (ATA/ATAPI configuration)
2507
@itemx dma_mode0_teoc = @var{value}
2508
@cindex @code{dma_mode0_teoc} (ATA/ATAPI configuration)
2509
These parameters specify the timings for use with DMA transfers. They
2510
are specified as the number of clock cycles - 2, rounded up to the
2511
next highest integer, or zero if that would be negative. The values
2512
should not exceed 255. If they do, they will be ignored with a
2513
warning.
2514
 
2515
See the ATA/ATAPI-5 specification for explanations of each of these
2516
timing parameters. The default values are:
2517
 
2518
@example
2519
dma_mode0_tm   =  4
2520
dma_mode0_td   = 21
2521
dma_mode0_teoc = 21
2522
@end example
2523
 
2524
@end table
2525
 
2526
@subsubsection ATA/ATAPI Device Configuration
2527
@cindex disc interface device configuration
2528
@cindex ATA/ATAPI device configuration
2529
Within the @code{@w{section ata}}, each device is specified
2530
separately. The device subsection is introduced by
2531
 
2532
@example
2533
device @var{value}
2534
@end example
2535
 
2536
@var{value} is the device number, which should be 0 or 1. The
2537
subsection ends with @code{enddevice}. Note that if the same device
2538
number is specified more than once, the previous values will be
2539
overwritten. Within the @code{device} subsection, the following
2540
parameters may appear:
2541
 
2542
@table @code
2543
 
2544
@item type = @var{value}
2545
@cindex @code{type} (ATA/ATAPI device configuration)
2546
@var{value}specifies the type of device: 0 (the default) for ``not
2547
connected'', 1 for hard disk simulated in a file and 2 for local system
2548
hard disk.
2549
 
2550
@item file = "@var{filename}"
2551
@cindex @code{file} (ATA/ATAPI device configuration)
2552
@file{filename} specifies the file to be used for a simulated ATA
2553
device if the file type (see @code{type} above) is 1. Default value
2554
@code{"ata-File@var{n}"}, where @var{n} is the device number.
2555
 
2556
@item size = @var{value}
2557
@cindex @code{size} (ATA/ATAPI device configuration)
2558
@var{value} specifies the size of a simulated ATA device if the file
2559
type (see @code{type} above) is 1. The default value is zero.
2560
 
2561
@item packet = 0|1
2562
@cindex @code{packet} (ATA/ATAPI device configuration)
2563
If 1 (true), implement the PACKET command feature set. If 0 (the
2564
default), do not implement the PACKET command feature set.
2565
 
2566
@item firmware = "@var{str}"
2567
@cindex @code{firmware} (ATA/ATAPI device configuration)
2568
Firmware to report in response to the ``Identify Device''
2569
command. Default @code{"02207031"}.
2570
 
2571
@item heads = @var{value}
2572
@cindex @code{heads} (ATA/ATAPI device configuration)
2573
Number of heads in the device. Default 7, use -1 to disable all heads.
2574
 
2575
@item sectors = @var{value}
2576
@cindex @code{sectors} (ATA/ATAPI device configuration)
2577
Number of sectors per track in the device. Default 32.
2578
 
2579
@item mwdma = 0|1|2|-1
2580
@cindex @code{mwdma} (ATA/ATAPI device configuration)
2581
Highest multi-word DMA mode supported. Default 2, use -1 to disable.
2582
 
2583
@item pio = 0|1|2|3|4
2584
@cindex @code{pio} (ATA/ATAPI device configuration)
2585
Highest PIO mode supported. Default 4.
2586
 
2587
@end table
2588
 
2589
@node Generic Peripheral Configuration
2590
@subsection Generic Peripheral Configuration
2591
@cindex generic peripheral configuration
2592
@cindex configuration of generic peripherals
2593
@cindex @code{section generic}
2594
When used as a library (@pxref{Simulator Library, , Simulator
2595
Library}), @value{OR1KSIM} makes provision for any additional peripheral to be
2596
implemented externally. Any read or write access to this peripheral's
2597
memory map generates @dfn{upcall}s to an external handler. This
2598
interface can support either C or C++, and was particularly designed
2599
to facilitate support for OSCI SystemC (see @url{http://www.systemc.org}).
2600
 
2601
Generic peripheral configuration is described in @code{@w{section
2602
generic}}. This section may appear multiple times, specifying multiple
2603
external peripherals. The following parameters may be specified.
2604
 
2605
@table @code
2606
 
2607
@item enabled = 0|1
2608
@cindex @code{enabled} (generic peripheral configuration)
2609
If 1 (true, the default), this ATA/ATAPI interface is enabled. If 0,
2610
it is disabled.
2611
 
2612
@item baseaddr = @var{value}
2613
@cindex @code{baseaddr} (generic peripheral configuration)
2614
Set the base address of the generic peripheral's memory mapped
2615
registers to @var{value}. The default is 0, which is probably not a
2616
sensible value.
2617
 
2618
The size of the memory mapped register space is controlled by the
2619
@code{size} paramter, described below.
2620
 
2621
@item size = @var{value}
2622
@cindex @code{size} (generic peripheral configuration)
2623
Set the size of the generic peripheral's memory mapped register space
2624
to @var{value} bytes. Any read or write accesses to addresses with
2625
offsets of 0 to @var{value}-1 bytes from the base address specified in
2626
parameter @code{baseaddr} (see above) will be directed to the external
2627
interface.
2628
 
2629
@var{value} will be rounded up the nearest power of 2. It's default
2630
value is zero. If @var{value} is not an exact power of two, accesses
2631
to address offsets of @var{value} or above up to the next power of 2
2632
will generate a warning, and have no effect (reads will return zero).
2633
 
2634
@item name = "@var{str}"
2635
@cindex @code{name} (generic peripheral configuration)
2636
This gives the peripheral the name @code{"@var{str}"}. This is used to
2637
identify the peripheral in error messages and warnings, and when
2638
reporting its status. The default value is @code{@w{"anonymous
2639
external peripheral"}}.
2640
 
2641
@item byte_enabled = 0|1
2642
@cindex @code{byte_enabled} (generic peripheral configuration)
2643
@itemx hw_enabled = 0|1
2644
@cindex @code{hw_enabled} (generic peripheral configuration)
2645
@itemx word_enabled = 0|1
2646
@cindex @code{word_enabled} (generic peripheral configuration)
2647
If 1 (true, the default), these parameters respectively enable the
2648
device for byte wide, half-word wide and word wide accesses. If 0,
2649
accesses of that width will fail.
2650
 
2651
@end table
2652
 
2653
@node Interactive Command Line
2654
@chapter Interactive Command Line
2655
 
2656
If started with the @code{-f} flag, or if interrupted with
2657
@kbd{ctrl-C}, @value{OR1KSIM} provides the user with an interactive
2658
command line. The commands available, which may not be abbreviated, are:
2659
 
2660
@table @code
2661
 
2662
@item q
2663
@cindex @code{q} (Interactive CLI)
2664
@cindex quitting (Interactive CLI)
2665
Exit the simulator
2666
 
2667
@item r
2668
@cindex @code{r} (Interactive CLI)
2669
@cindex displaying registers (Interactive CLI)
2670
@cindex register display (Interactive CLI)
2671
Display all the General Purpose Registers (GPRs). Also shows the just
2672
executed and next to be executed instructions symbolically and the
2673
state of the flag in the Supervision Register.
2674
 
2675
@item t
2676
@cindex @code{t} (Interactive CLI)
2677
@cindex stepping code (Interactive CLI)
2678
Execute the next instruction and then display register/instruction
2679
information as with the @code{r} command (see above).
2680
 
2681
@item run @var{num} [ hush ]
2682
@cindex @code{run} (Interactive CLI)
2683
@cindex running code (Interactive CLI)
2684
@cindex executing code (Interactive CLI)
2685
Execute @var{num} instructions. The register/instruction information
2686
is displayed after each instruction, as with the @code{r} command (see
2687
above) @emph{unless} @code{hush} is specified.
2688
 
2689
@item pr @var{reg} @var{value}
2690
@cindex @code{pr} (Interactive CLI)
2691
@cindex patching registers (Interactive CLI)
2692
@cindex register patching (Interactive CLI)
2693
Patch register @var{reg} with @var{value}.
2694
 
2695
@item dm @var{fromaddr} [ @var{toaddr} ]
2696
@cindex @code{dm} (Interactive CLI)
2697
@cindex displaying memory (Interactive CLI)
2698
@cindex memory display (Interactive CLI)
2699
Display memory bytes between @var{fromaddr} and @var{toaddr}. If
2700
@var{toaddr} is not given, 64 bytes are displayed, starting at
2701
@var{fromaddr}.
2702
 
2703
@quotation Caution
2704
The output from this command is broken (a bug). @value{OR1KSIM}
2705
attempts to print out 16 bytes per row. However, instead of printing
2706
out the address at the start of each row, it prints the address (of
2707
the first of the 16 bytes) before @emph{each} byte.
2708
@end quotation
2709
 
2710
@item de @var{fromaddr} [ @var{toaddr} ]
2711
@cindex @code{dm} (Interactive CLI)
2712
@cindex disassemble (Interactive CLI)
2713
Disassemble code between @var{fromaddr} and @var{toaddr}. If
2714
@var{toaddr} is not given, 16 instructions are disassembled.
2715
 
2716
The disassembly is entirely numerical, and gives no symbolic
2717
information.
2718
 
2719
@item pm @var{addr} @var{value}
2720
@cindex @code{pm} (Interactive CLI)
2721
@cindex patching memory (Interactive CLI)
2722
@cindex memory patching (Interactive CLI)
2723
Patch the 4 bytes in memory starting at @var{addr} with the 32-bit
2724
@var{value}.
2725
 
2726
@item pc @var{value}
2727
@cindex @code{pc} (Interactive CLI)
2728
@cindex patching the program counter (Interactive CLI)
2729
@cindex program counter patching (Interactive CLI)
2730
Patch the program counter with @var{value}.
2731
 
2732
@item cm @var{fromaddr} @var{toaddr} @var{size}
2733
@cindex @code{cm} (Interactive CLI)
2734
@cindex copying memory (Interactive CLI)
2735
@cindex memory copying (Interactive CLI)
2736
Copy @var{size} bytes in memory from @var{fromaddr} to @var{toaddr}.
2737
 
2738
@item break @var{addr}
2739
@cindex @code{break} (Interactive CLI)
2740
@cindex breakpoint set/clear (Interactive CLI)
2741
@cindex set breakpoint (Interactive CLI)
2742
@cindex clear breakpoint (Interactive CLI)
2743
@cindex toggle breakpoint (Interactive CLI)
2744
Toggle the breakpoint set at @var{addr}.
2745
 
2746
@item breaks
2747
@cindex @code{breaks} (Interactive CLI)
2748
@cindex breakpoint list (Interactive CLI)
2749
@cindex list breakpoints (Interactive CLI)
2750
List all set breakpoints
2751
 
2752
@item reset
2753
@cindex @code{reset} (Interactive CLI)
2754
@cindex simulator reset (Interactive CLI)
2755
@cindex reset the simulator (Interactive CLI)
2756
Reset the simulator. Includes modeling a reset of the processor, so
2757
execution will restart from the reset vector location, 0x100.
2758
 
2759
@item hist
2760
@cindex @code{hist} (Interactive CLI)
2761
@cindex execution history (Interactive CLI)
2762
@cindex history of execution (Interactive CLI)
2763
If saving the execution history has been configured (@pxref{Simulator
2764
Behavior, , Simulator Behavior}), display the execution history.
2765
 
2766
@item stall
2767
@cindex @code{stall} (Interactive CLI)
2768
@cindex processor stall (Interactive CLI)
2769
@cindex stall the processor (Interactive CLI)
2770
Stall the processor, so that control is passed to the debug unit. When
2771
stalled, the processor can execute no instructions. This command is
2772
useful when debugging the JTAG interface, used by debuggers such as
2773
GDB.
2774
 
2775
@item unstall
2776
@cindex @code{unstall} (Interactive CLI)
2777
@cindex processor unstall (Interactive CLI)
2778
@cindex unstall the processor (Interactive CLI)
2779
Unstall the processor, so that normal execution can continue. This command is
2780
useful when debugging the JTAG interface, used by debuggers such as GDB.
2781
 
2782
@item stats @var{category} | clear
2783
@cindex @code{stats} (Interactive CLI)
2784
@cindex simulator statistics (Interactive CLI)
2785
@cindex statistics, simulation (Interactive CLI)
2786
Print the statistics for the given @var{category}, if available, or
2787
clear if @code{clear} is specified. The categories are:
2788
 
2789
@table @asis
2790
 
2791
@item 1
2792
Miscellaneous statistics: branch predictions (if branch predictions
2793
are enabled), branch target cache model (if enabled), cache (if
2794
enbaled), MMU (if enabled) and number of addtional load & store
2795
cycles.
2796
 
2797
@xref{Core OpenRISC Configuration, , Configuring the OpenRisc
2798
Achitectural Components}, for details of how to enable these various
2799
features.
2800
 
2801
@item 2
2802
Instruction usage statistics. Requires hazard analysis to be enabled
2803
(@pxref{CPU Configuration, ,CPU Configuration}).
2804
 
2805
@item 3
2806
Instruction dependency statistics. Requires hazard analysis to be enabled
2807
(@pxref{CPU Configuration, ,CPU Configuration}).
2808
 
2809
@item 4
2810
Functional unit dependency statistics. Requires hazard analysis to be enabled
2811
(@pxref{CPU Configuration, ,CPU Configuration}).
2812
 
2813
@item 5
2814
Raw register usage over time. Requires hazard analysis to be enabled
2815
(@pxref{CPU Configuration, ,CPU Configuration}).
2816
 
2817
@item 6
2818
Store buffer statistics. Requires the store buffer to be enabled
2819
(@pxref{CPU Configuration, ,CPU Configuration}).
2820
 
2821
@end table
2822
 
2823
@item info
2824
@cindex @code{info} (Interactive CLI)
2825
@cindex simulator configuration info (Interactive CLI)
2826
@cindex configuration info (Interactive CLI)
2827
Display detailed information about the simulator configuration. This
2828
is quite a lengthy about, because all MMU TLB information is displayed.
2829
 
2830
@item dv @var{fromaddr} [ @var{toaddr} ] [ @var{module} ]
2831
@cindex @code{dv} (Interactive CLI)
2832
@cindex Verilog memory dump (Interactive CLI)
2833
@cindex memory dump, Verilog (Interactive CLI)
2834
Dump the area of memory between @var{fromaddr} and @var{toaddr} as
2835
Verilog code for a synchronous, 23-bit wide SRAM module, named
2836
@var{module}. If @var{toaddr} is not specified, then 64 bytes are
2837
dumped (as 16 32-bit words). If @var{module} is not specified,
2838
@code{or1k_mem} is used.
2839
 
2840
To save to a file, use the redirection function (described after this
2841
table, below).
2842
 
2843
@item dh @var{fromaddr} [ @var{toaddr} ]
2844
@cindex @code{dv} (Interactive CLI)
2845
@cindex hexadecimal memory dump (Interactive CLI)
2846
@cindex memory dump, hexadecimal (Interactive CLI)
2847
Dump the area of memory between @var{fromaddr} and @var{toaddr} as
2848
32-bit hex numbers (no @code{0x}, or @code{32'h} prefix). If
2849
@var{toaddr} is not specified, then 64 bytes are dumped (as 16 32-bit
2850
words).
2851
 
2852
To save to a file, use the redirection function (described after this
2853
table, below).
2854
 
2855
@item setdbch
2856
@cindex @code{setdbch} (Interactive CLI)
2857
@cindex debug channel toggle (Interactive CLI)
2858
@cindex toggle debug channels (Interactive CLI)
2859
Toggle debug channels on/off. @xref{Standalone Simulator, , Standalone
2860
Simulator}, for a description of specifying debug channels on the
2861
command line.
2862
 
2863
@item set @var{section} @var{param} = @var{value}
2864
@cindex @code{set} (Interactive CLI)
2865
@cindex configuration parameter setting (Interactive CLI)
2866
Set the configuration parameter @var{para} in section @var{section} to
2867
@var{value}. @xref{Configuration, , Configuration}, for details of
2868
configuration parameters and their settings.
2869
 
2870
@item debug
2871
@cindex @code{debug} (Interactive CLI)
2872
@cindex debug mode toggle (Interactive CLI)
2873
@cindex toggle debug mode (Interactive CLI)
2874
Toggle the simulator debug mode. @xref{Debug Interface Configuration,
2875
, Debug Interface Configuration}, for information on this parameter.
2876
 
2877
@quotation Caution
2878
This is effectively enabling or disabling the debug unit. It does not
2879
effect the remote GDB debug interface. However using the remote debug
2880
interface while the debug unit is disabled will lead to undefined
2881
behavior and likely crash @value{OR1KSIM}
2882
@end quotation
2883
 
2884
@item cuc
2885
@cindex @code{debug} (Interactive CLI)
2886
@cindex Custom Unit Compiler (Interactive CLI)
2887
Enter the the Custom Unit Compiler command prompt (@pxref{CUC
2888
Configuration, , CUC Configuration}).
2889
 
2890
@quotation Caution
2891
The CUC must be properly configured, for this to succeed. In
2892
particular a timing file must be available and readable. Otherwise
2893
@value{OR1KSIM} will crash.
2894
@end quotation
2895
 
2896
@item help
2897
@cindex @code{help} (Interactive CLI)
2898
@cindex Custom Unit Compiler (Interactive CLI)
2899
Print out brief information about each command available.
2900
 
2901
@item mprofile [-vh] [-m @var{m}] [-g @var{n}] [-f @var{file}] @var{from} @var{to}
2902
@cindex @code{mprofile} (Interactive CLI)
2903
@cindex memory profiling utility (Interactive CLI)
2904
Run the memory profiling utility. This follows the same usage as the
2905
standalone command (@pxref{Memory Profiling Utility, , Memory
2906
Profiling Utility}).
2907
 
2908
@item profile [-vhcq] [-g @var{file}]
2909
@cindex @code{mprofile} (Interactive CLI)
2910
@cindex profiling utility (Interactive CLI)
2911
@cindex instruction profiling utility (Interactive CLI)
2912
Run the instruction profiling utility. This follows the same usage as the
2913
standalone command (@pxref{Profiling Utility, , Profiling Utility}).
2914
 
2915
@end table
2916
 
2917
For all commands, it is possible to redirect the output to a file, by
2918
using the redirection operator, @code{>}.
2919
 
2920
@example
2921
@var{command} > @var{filename}
2922
@end example
2923
 
2924
This is particularly useful for commands dumping a large amount of
2925
output, such as @code{dv}.
2926
 
2927
@quotation Caution
2928
Unfortunately there is a serious bug with the redirection operator. It
2929
does not return output to standard output after the command
2930
completes. Until this bug is fixed, file redirection should not be
2931
used.
2932
@end quotation
2933
 
2934
@node Verification API
2935
@chapter Verification API (VAPI)
2936
 
2937
The Verification API (VAPI) provides a TCP/IP interface to allow
2938
components of the simulation to be controlled externally. The
2939
interface is polled for new requests on each simulated clock
2940
cycle. Components within the simulator may send responses to such
2941
requests.
2942
 
2943
The inteface is an asynchronous duplex protocol. On the request side
2944
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2945
with a single piece of data (also a 32 bit integer). On the send side,
2946
it provides for sending a single VAPI ID and data. However there is no
2947
explicit command-response structure. Some components just accept
2948
requests (e.g. to set values), some just generate sends (to report
2949
values), and some do both.
2950
 
2951
Each component has a base ID (32 bit) and its commands will start from
2952
that base ID. This provides a simple partitioning of the command space
2953
amongst components. Request commands will be directed to the component with
2954
the closest base ID lower than the VAPI ID of the command.
2955
 
2956
Thus if there are two components with base IDs of 0x200 and 0x300, and
2957
a request with VAPI ID of 0x203 is received, it will be directed to
2958
the first component as its command #3.
2959
 
2960
The results of VAPI interactions are logged (by default in
2961
@file{vapi.log} unless an alternative is specified in @code{@w{section
2962
vapi}}).
2963
 
2964
Currently the following components support VAPI:
2965
 
2966
@table @asis
2967
 
2968
@item Debug Unit
2969
@cindex Debug Unit verification (VAPI)
2970
@cindex VAPI for Debug Unit
2971
Although the Debug Unit can specify a base VAPI ID, it is not used to
2972
send commands or receive requests.
2973
 
2974
Instead, if the base VAPI ID is set, all remote JTAG protocol exchanges are
2975
logged in the VAPI log file.
2976
 
2977
@item UART
2978
@cindex UART verification (VAPI)
2979
@cindex VAPI for UART
2980
If a base VAPI ID is specified, the UART sends details of any chars or
2981
break characters sent, with dteails of the line control register etc
2982
encoded in the data packet sent.
2983
 
2984
This supports a single VAPI command request, but encodes a sub-command in the
2985
top 8 bits of the associated data.
2986
 
2987
@table @code
2988
 
2989
@item 0x00
2990
@cindex 0x00 UART VAPI sub-command (UART verification)
2991
This stuffs the least significant 8 bits of the data into the serial
2992
register of the UART and the next 8 bits into the line control
2993
register, effectively providing control of the next character to be
2994
sent or received.
2995
 
2996
@item 0x01
2997
@cindex 0x01 UART VAPI sub-command (UART verification)
2998
The divisor latch bytes are set from the least significant 16 bits of
2999
the data.
3000
 
3001
@item 0x02
3002
@cindex 0x02 UART VAPI sub-command (UART verification)
3003
The line control register is set from bits 15-8 of the data.
3004
 
3005
@item 0x03
3006
@cindex 0x03 UART VAPI sub-command (UART verification)
3007
The UART skew is set from the least significant 16 bits of the data
3008
 
3009
@item 0x04
3010
@cindex 0x04 UART VAPI sub-command (UART verification)
3011
If the 16th most significant bit of the data is 1, start sending
3012
breaks, otherwise stop sending breaks. The breaks are sent or cleared
3013
after the number of UART clock divider ticks specified by the data
3014
(immediately if the data is zero).
3015
 
3016
@end table
3017
 
3018
@item DMA
3019
@cindex DMA verification (VAPI)
3020
@cindex VAPI for DMA
3021
Although the DMA unit supports a base VAPI ID in its configuration
3022
(@code{@w{section dma}}), no VAPI data is sent, nor VAPI requests
3023
currently implemented.
3024
 
3025
@item Ethernet
3026
@cindex Ethernet verification (VAPI)
3027
@cindex VAPI for Ethernet
3028
The following requests are handled by the Ethernet. Specified
3029
symbolically, these are the increments from the base VAPI ID of the
3030
Ethernet. At present no implementation is provided behind these VAPI
3031
requests.
3032
 
3033
@table @code
3034
 
3035
@item ETH_VAPI_DATA (0)
3036
@cindex @code{ETH_VAPI_DATA} (Ethernet verification)
3037
 
3038
@item ETH_VAPI_CTRL (0)
3039
@cindex @code{ETH_VAPI_CTRL} (Ethernet verification)
3040
 
3041
@end table
3042
 
3043
@item GPIO
3044
@cindex GPIO verification (VAPI)
3045
@cindex VAPI for GPIO
3046
If a base VAPI ID is specified, the GPIO sends out on its base VAPI ID
3047
(symbolically, GPIO_VAPI_DATA (0) offset from the base VAPI ID) any
3048
changes in outputs.
3049
 
3050
The following requests are handled by the GPIO. Specified
3051
symbolically, these are the increments from the VAPI base ID of the
3052
GPIO.
3053
 
3054
@table @code
3055
 
3056
@item GPIO_VAPI_DATA (0)
3057
@cindex @code{GPIO_VAPI_DATA} (GPIO verification)
3058
Set the next input to the commands data field
3059
 
3060
@item GPIO_VAPI_AUX (1)
3061
@cindex @code{GPIO_VAPI_AUX} (GPIO verification)
3062
Set the GPIO auxiliary inputs to the data field
3063
 
3064
@item GPIO_VAPI_CLOCK (2)
3065
@cindex @code{GPIO_VAPI_CLOCK} (GPIO verification)
3066
Add an external GPIO clock trigger of period specified in the data field.
3067
 
3068
@item GPIO_VAPI_RGPIO_OE (3)
3069
@cindex @code{GPIO_VAPI_RGPIO} (GPIO verification)
3070
Set the GPIO output enable to the data field
3071
 
3072
@item GPIO_VAPI_RGPIO_INTE (4)
3073
@cindex @code{GPIO_VAPI_INTE} (GPIO verification)
3074
Set the next interrupt to the data field
3075
 
3076
@item GPIO_VAPI_RGPIO_PTRIG (5)
3077
@cindex @code{GPIO_VAPI_PTRIG} (GPIO verification)
3078
Set the next trigger to the data field
3079
 
3080
@item GPIO_VAPI_RGPIO_AUX (6)
3081
@cindex @code{GPIO_VAPI_AUX} (GPIO verification)
3082
Set the next auxiliary input to the data field
3083
 
3084
@item GPIO_VAPI_RGPIO_CTRL (7)
3085
@cindex @code{GPIO_VAPI_CTRL} (GPIO verification)
3086
Set th next control input to the data field
3087
 
3088
@end table
3089
 
3090
@end table
3091
 
3092
@node Code Internals
3093
@chapter A Guide to @value{OR1KSIM} Internals
3094
 
3095
These are notes to help those wanting to extend @value{OR1KSIM}. This
3096
section assumes the use of a tag file, so file locations of entities'
3097
definitions are not in general provided. For more on tags, see the
3098
Linux manual page for @command{etags}. A tag file can be created
3099
with:
3100
 
3101
@example
3102
make tags
3103
@end example
3104
 
3105
@menu
3106
* Coding Conventions::
3107
* Global Data Structures::
3108
* Concepts::
3109
* Internal Debugging::
3110
@end menu
3111
 
3112
@node Coding Conventions
3113
@section Coding Conventions for @value{OR1KSIM}
3114
 
3115
This chapter provides some guidelines for coding, to facilitate
3116
extensions to @value{OR1KSIM}
3117
 
3118
@table @emph
3119
 
3120
@item GNU Coding Standard
3121
Code should follow the GNU coding standard for C
3122
(@url{http://www.gnu.org/prep/standards/}. If in doubt, put your code
3123
through the @command{indent} program.
3124
 
3125
@item @code{#include} headers
3126
All C source code files should include @file{config.h} before any
3127
other file.
3128
 
3129
This should be followed by inclusion of any system headers (but see
3130
the comments about portability and @file{port.h} below) and then by
3131
any @value{OR1KSIM} package headers.
3132
 
3133
If @file{port.h} is required, it should be the first package header to
3134
be included after the system headers.
3135
 
3136
All C source code and header files should directly include any system
3137
or package header they depend on, i.e. not rely on any other header
3138
having already included it. The two exceptions are
3139
 
3140
@enumerate
3141
@item
3142
All header files may assume that @file{config.h} has already been
3143
included.
3144
 
3145
@item
3146
System headers which impose portability problems should be included by
3147
using the package header @file{port.h}, rather than the system headers
3148
themselves. This is the case for code requiring
3149
 
3150
@itemize @bullet
3151
 
3152
@item
3153
@code{strndup} (from @file{string.h})
3154
 
3155
@item
3156
Integer types (@code{int@var{n}_t}, @code{uint@var{n}_t}) (from
3157
@file{inttypes.h}).
3158
 
3159
@item
3160
@code{isblank} (from @file{ctype.h})
3161
 
3162
@end itemize
3163
 
3164
@end enumerate
3165
 
3166
@item @code{#include} files once only
3167
All include files should be protected by @code{#ifndef} to ensure
3168
their definitions are only included once. For instance a header file
3169
@file{@var{x-y.h}} should surround its contents with:
3170
 
3171
@example
3172
#ifndef X_Y__H
3173
#define X_Y__H
3174
 
3175
<body of the include file>
3176
 
3177
#endif  /* X_Y__H */
3178
@end example
3179
 
3180
@item Avoid @code{typedef}
3181
The GNU coding style for C does not have a clear way to distinguish
3182
between user type name and user variables. For this reason
3183
@code{typedef} should be avoided except for the most ubiquitous user
3184
defined types. This makes the code much easier to read.
3185
 
3186
There are some @code{typedef} declarations in the @command{argtable2}
3187
library and the @acronym{ELF} and @acronym{COFF} headers, because this
3188
code is taken from other places.
3189
 
3190
Within @value{OR1KSIM} legacy uses of @code{typedef} have largely been
3191
purged, except in the Custom Unit Compiler (@pxref{CUC Configuration,
3192
, Custom Unit Compiler (CUC) Configuration}).
3193
 
3194
The remaining uses of @code{typedef} occur in two places:
3195
 
3196
@itemize @bullet
3197
 
3198
@item
3199
@file{port/port.h} defines types to replace those in header files that
3200
are not available (character functions, string duplication, integer
3201
types).
3202
 
3203
@file{cpu/or1k/arch.h} defines types for the key @value{OR1KSIM}
3204
entities: addresses (@code{oraddr_t}), unsigned register values
3205
(@code{uorreg_t}) and signed register (@code{orreg_t}) values.
3206
 
3207
@end itemize
3208
 
3209
Where new types are defined, they should appear in one of these two
3210
files as appropriate. @value{OR1KSIM} specific types appearing in
3211
@file{arch.h} should always have the suffix @file{_h}.
3212
 
3213
@item Don't begin names with underscore
3214
Names beginning with @code{_} are intended to be part of the C
3215
infrastructure. They should not be used in the simulator code.
3216
 
3217
@item Keep Non-global top level entities static
3218
All top level entities (functions, variables), which are not
3219
explicitly part of a global interface should be declared static. This
3220
ensures that unwanted connections are not inadvertently built across
3221
the program.
3222
 
3223
@item Use of @code{inline}
3224
Code should not be declared @code{inline}. Modern compilers can work
3225
out for themselves what is best in this respect.
3226
 
3227
@item Initialization
3228
All data structures should be explicitly initialized. In particular
3229
code should not rely on static data structures being initialized to
3230
zero.
3231
 
3232
The rationale is that in future static data structures may become
3233
dynamic. This has been a particular source of bugs in @value{OR1KSIM}
3234
historically.
3235
 
3236
A specific case is with new peripherals, which should always include a
3237
@code{start} function to pre-initialize all configuration parameters
3238
to sensible defaults
3239
 
3240
@item Configuration Validation
3241
All configuration values should be validated, preferably when
3242
encountered, if not when the @code{section} is closed, or otherwise
3243
at run time when the parameter is first used.
3244
 
3245
@end table
3246
 
3247
@node Global Data Structures
3248
@section Global Data Structures
3249
 
3250
@table @code
3251
 
3252
@item config
3253
@cindex configuration global structure
3254
@vindex config
3255
The global variable @code{config} of type @code{struct config} holds
3256
the configuration data for some of the @value{OR1KSIM} components which
3257
are always present. At present the components are:
3258
 
3259
@itemize @bullet
3260
 
3261
@item
3262
@vindex config.sim
3263
The simulator defined in @code{@w{section sim}} (@pxref{Simulator
3264
Configuration, , Simulator Configuration}).
3265
 
3266
@item
3267
@vindex config.vapi
3268
The Verification API (VAPI) defined  in @code{@w{section vapi}}
3269
(@pxref{Verification API Configuration, , Verification API (VAPI)
3270
Configuration}).
3271
 
3272
@item
3273
@vindex config.cuc
3274
The Custom Unit Compiler (CUC), defined in @code{@w{section cuc}}
3275
(@pxref{CUC Configuration, , Custom Unit Compiler (CUC)
3276
Configuration}).
3277
 
3278
@item
3279
@vindex config.cpu
3280
The CPU, defined in @code{@w{section cpu}} (@pxref{CPU Configuration,
3281
, CPU Configuration}).
3282
 
3283
@item
3284
@vindex config.dc
3285
The data cache (but not the instruction cache), defined in
3286
@code{@w{section dc}} (@pxref{Cache Configuration, , Cache
3287
Configuration}).
3288
 
3289
@item
3290
@vindex config.pm
3291
The power management unit, defined in @code{@w{section pm}}
3292
(@pxref{Power Management Configuration, , Power Management
3293
Configuration}).
3294
 
3295
@item
3296
@vindex config.pic
3297
The programmable interrupt controller, defined in @code{@w{section pic}}
3298
(@pxref{Interrupt Configuration, , Interrupt Configuration}).
3299
 
3300
@item
3301
@vindex config.bpb
3302
Branch prediciton, defined in @code{@w{section bpb}} (@pxref{Branch
3303
Prediction Configuration, , Branch Prediction Configuration}).
3304
 
3305
@item
3306
@vindex config.debug
3307
The debug unit, defined in @code{@w{section debug}} (@pxref{Debug
3308
Interface Configuration, , Debug Interface Configuration}).
3309
 
3310
@end itemize
3311
 
3312
This struct is made of a collection of structs, one for each
3313
component. For example the simulator configuration is held in
3314
@code{config.sim}.
3315
 
3316
@item config
3317
@cindex configuration dynamic structure
3318
@vindex sections
3319
This is a linked list of data structures holding configuration data
3320
for all sections which are not held in the main @code{config} data
3321
structure. In general these are components (such as peripherals and
3322
memory) which may occur multiple times. However it also handles some
3323
architectural components which may occur only once, such as the memory
3324
management units, the instruction cache, the interrupt controller and
3325
branch prediction.
3326
 
3327
@item runtime
3328
@cindex runtime global structure
3329
@vindex runtime
3330
The global variable @code{runtime} of type @code{struct runtime} holds
3331
all the runtime information about the simulation. To access this
3332
variable, @file{sim-config.h} must be included.
3333
 
3334
@vindex runtime.cpu
3335
@vindex runtime.vapi
3336
@vindex runtime.cuc
3337
This struct is itself made of 3 other structs, @code{cpu} (for CPU run
3338
time state), @code{vapi} (for Verification API state) and @code{cuc}
3339
(for Custom Unit Compiler state).
3340
 
3341
@end table
3342
 
3343
@node Concepts
3344
@section Concepts
3345
 
3346
@table @emph
3347
 
3348
@anchor{Output Redirection}
3349
@item Output Redirection
3350
@cindex output rediretion
3351
@vindex runtime.cpu.fout
3352
The current output stream is held in @code{runtime.cpu.fout}. Output
3353
should be explicitly written to this stream, or may use the
3354
@code{PRINTF} macro, which will write its arguments to this output stream.
3355
 
3356
@item Reset Hooks
3357
@cindex reset hooks
3358
@findex reg_sim_reset
3359
Any peripheral may register a routine to be called when the the
3360
processor is reset by calling @code{reg_sim_reset}, providing a
3361
function and pointer to a data structure as arguments. On reset that
3362
function will be called with the data stucture pointer as argument.
3363
 
3364
@end table
3365
 
3366
@node Internal Debugging
3367
@section Internal Debugging
3368
@cindex internal debugging
3369
 
3370
The function @code{debug} is like @code{printf}, but with an extra
3371
first argument, which is the debug level. If the debug level specified
3372
in the simulator configuration (@pxref{Simulator Behavior, , Simulator
3373
Behavior}) is greater than or equal to this value, the remaining
3374
arguments are printed to the current output stream (@pxref{Output
3375
Redirection, , Output Redirection}).
3376
 
3377
@node  GNU Free Documentation License
3378
@chapter GNU Free Documentation License
3379
@cindex license for @value{OR1KSIM}
3380
 
3381
@include fdl-1.2.texi
3382
 
3383
@node Index
3384
 
3385
@unnumbered Index
3386
 
3387
@printindex cp
3388
 
3389
@bye

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.