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\input texinfo   @c -*- texinfo -*-
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@setfilename or1ksim.info
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@afourpaper
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@include version.texi
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@include config.texi
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@dircategory Embedded development
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@direntry
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* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
9
                                        Simulator
10
@end direntry
11
 
12
@copying
13
This file documents the OpenRISC Architectural Simulator, @value{OR1KSIM}.
14
 
15
Copyright @copyright{} 2008, 2009 Embecosm Limited.
16
 
17
@quotation
18
Permission is granted to copy, distribute and/or modify this document
19
under the terms of the GNU Free Documentation License, Version 1.2 or
20
any later version published by the Free Software Foundation; with no
21
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
22
Texts.  A copy of the license is included in the section entitled ``GNU
23
Free Documentation License''.
24
@end quotation
25
@end copying
26
 
27
@setchapternewpage on
28
@settitle @value{OR1KSIM} User Guide
29
 
30
@syncodeindex fn cp
31
@syncodeindex vr cp
32
 
33
@titlepage
34
@title @value{OR1KSIM} User Guide
35
@author Jeremy Bennett
36
@author Embecosm Limited
37
@author Issue 1 for @value{OR1KSIM} @value{VERSION}
38
 
39
@page
40
@vskip 0pt plus 1filll
41
@insertcopying
42
 
43
Published by Embecosm Limited
44
@end titlepage
45
 
46
@contents
47
 
48
@node Top
49
@c Perhaps this should be the title of the document (but only for info,
50
@c not for TeX).  Existing GNU manuals seem inconsistent on this point.
51
@top Scope of this Document
52
 
53
This document is the user guide for @value{OR1KSIM}, the OpenRISC 1000
54
Architectural Simulator.
55
 
56
@menu
57
* Installation::
58
* Usage::
59
* Configuration::
60
* Interactive Command Line::
61
* Verification API::
62
 
63
* Code Internals::
64
 
65
* GNU Free Documentation License::  The license for this documentation
66
* Index::
67
@end menu
68
 
69
@node Installation
70
@chapter Installation
71
@cindex installing @value{OR1KSIM}
72
 
73
Installation follows standard GNU protocols.
74
 
75
@menu
76
* Preparation::
77
* Configuring the Build::
78
* Build and Install::
79
* Known Issues::
80
@end menu
81
 
82
@node Preparation
83
@section Preparation
84
 
85
Unpack the software and create a @emph{separate} directory in which to
86
build it:
87
 
88
@example
89
@kbd{tar jxf or1ksim-@value{VERSION}.tar.bz2}
90
@kbd{mkdir builddir_or1ksim}
91
@kbd{cd builddir_or1ksim}
92
@end example
93
 
94
@node Configuring the Build
95
@section Configuring the Build
96
 
97
Configure the software using the @command{configure} script in the
98
main directory.
99
 
100
The most significant argument is @code{--target}, which should specify
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the OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
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default to OpenRISC 1000 32-bit with a warning
103
 
104
@example
105
@kbd{../or1ksim-@value{VERSION}/configure --target=or32-uclinux ...}
106
@end example
107
 
108
There are several other options available, many of which are standard
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to GNU @command{configure} scripts.  Use @kbd{configure --help} to see
110
all the options.  The most useful is @code{--prefix} to specify a
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directory for installation of the tools.
112
 
113
A number of @value{OR1KSIM} features in the simulator do require enabling at
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configuration.  These include
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116
@table @code
117
@item --enable-profiling
118
@cindex @code{--enable-profiling}
119
@itemx --disable-profiling
120
@cindex @code{--disable-profiling}
121
If enabled, @value{OR1KSIM} is compiled for profiling with
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@command{gprof}.  This is disabled by default.  Only really of value for
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developers of @value{OR1KSIM}.
124
 
125
@item --enable-execution=simple
126
@itemx --enable-execution=complex
127
@itemx --enable-execution=dynamic
128
@cindex @code{--enable-execution}
129
@cindex simple model
130
@cindex complex model
131
@cindex dynamic model
132
@value{OR1KSIM} has developed to improve functionality and
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performance.  This feature allows three versions of @value{OR1KSIM} to be built
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135
@table @code
136
 
137
@item --enable-execution=simple
138
Build the original simple interpreting simulator
139
 
140
@item --enable-execution=complex
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Build a more complex interpreting simulator.  Experiments suggest this
142
is 50% faster than the simple simulator.  This is the default.
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144
@item --enable-execution=dynamic
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Build a dynamically compiling simulator.  This is the way many modern ISS are
146
built.  This represents a work in progress.  Currently @value{OR1KSIM} will
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compile, but segfaults if configured with this option.
148
 
149
@end table
150
 
151
The default is @code{--enable-execution=complex}.
152
 
153
@item --enable-ethphy
154
@cindex @code{--enable-ethphy}
155
@itemx --disable-ethphy
156
@cindex @code{--disable-ethphy}
157
@cindex Ethernet via socket, enabling
158
@cindex enabling Ethernet via socket
159
If enabled, this option allows the Ethernet to be simulated by connecting via a
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socket (the alternative reads and writes, from and to files).  This
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must then be configured using the relevant fields in the
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@code{ethernet} section of the configuration file.  @xref{Ethernet
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Configuration, , Ethernet Configuration}.
164
 
165
The default is for this to be disabled.
166
 
167
@item --enable-range-stats
168
@cindex @code{--enable-range-stats}
169
@itemx --disable-range-stats
170
@cindex @code{--disable-range-stats}
171
@cindex statistics, register over time
172
@cindex register over time statistics
173
If enabled, this option allows statistics to be collected to analyse
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register access over time.  The default is for this to be disabled.
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176
@item --enable-ov-flag
177
@cindex @code{--enable-ov-flag}
178
@itemx --disable-ov-flag
179
@cindex @code{--disable-ov-flag}
180
@cindex overflow flag setting by instructions
181
If enabled, this option causes instructions to set the overflow
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flag.  The instructions affected by this are @code{l.add},
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@code{l.addc}, @code{l.addi}, @code{l.and}, @code{l.andi},
184
@code{l.div}, @code{l.divu}, @code{l.mul}, @code{l.muli}, @code{l.or},
185
@code{l.ori}, @code{l.sll}, @code{l.slli}, @code{l.srl},
186
@code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.sub}, @code{l.xor}
187
and @code{l.xori}.
188
 
189
The default is for this to be disabled.
190
 
191
@quotation Caution
192
This appears a very dangerous option, to the extent of arguably being
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a bug.  Whether or not flags are set is part of the OpenRISC 1000
194
architectural specification.  Within the above list, the arithmetic
195 19 jeremybenn
instructions (@code{l.add}, @code{l.addc}, @code{l.addi},
196
@code{l.div}, @code{l.divu}, @code{l.mul}, @code{l.muli} and
197
@code{l.sub}), together with @code{l.addic} which is missed out, set
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the overflow flag.  All the others (@code{l.and}, @code{l.andi},
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@code{l.or}, @code{l.ori}, @code{l.sll}, @code{l.slli}, @code{l.srl},
200
@code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.xor} and
201
@code{l.xori}) do not.
202
 
203
Thus it is impossible to get correct behavior whichever way this option is
204
set.
205
@end quotation
206
 
207
@item --enable-arith-flag
208
@cindex @code{--enable-arith-flag}
209
@itemx --disable-arith-flag
210
@cindex @code{--disable-arith-flag}
211
@cindex flag setting by instructions
212
If enabled, this option causes instructions to set the flag (@code{F} bit) in
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the supervision register.  The instructions affected by this are @code{l.add},
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@code{l.addc}, @code{l.addi}, @code{l.and} and @code{l.andi}.
215
 
216
The default is for this to be disabled.
217
 
218
@quotation Caution
219
As with @code{--enable-ov-flag}, this appears another very dangerous option,
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to the extent of arguably being a bug.  It also appears to be only partially
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implemented---why only the instructions early in the alphabet?
222
 
223
Whether or not flags are set is part of the OpenRISC 1000 architectural
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specification.  The only flags which should set this are the ``set flag''
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instructions: @code{l.sfeq}, @code{l.sfeqi}, @code{l.sfges}, @code{l.sfgesi},
226
@code{l.sfgeu}, @code{l.sfgeui}, @code{l.sfgts}, @code{l.sfgtsi},
227
@code{l.sfgtu}, @code{l.sfgtui}, @code{l.sfles}, @code{l.sflesi},
228
@code{l.sfleu}, @code{l.sfleui}, @code{l.sflts}, @code{l.sfltsi},
229
@code{l.sfltu}, @code{l.sfltui}, @code{l.sfne} and @code{l.sfnei}.
230
 
231
The flags are correctly set (irrespective of @code{--enable-arith_flag}).
232
 
233
Correct behavior is thus achieved if this flag is not set.
234
@code{--enable-arith-flag} should never be used.
235
 
236
@end quotation
237
 
238
@item --enable-debug
239
@cindex @code{--enable-debug}
240
@itemx --disable-debug
241
@cindex @code{--disable-debug}
242
@cindex debugging enabled (Argtable2)
243
@cindex Argtable2 debugging
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This is a feature of the Argtable2 package used to process arguments.  If
245
enabled, some debugging features are turned on in Argtable2.  It is provided for
246 19 jeremybenn
completeness, but there is no reason why this feature should ever be needed by
247
any @value{OR1KSIM} user.
248
 
249 82 jeremybenn
@item --enable-all-tests
250
@cindex @code{--enable-all-tests}
251
@itemx --disable-all-tests
252
@cindex @code{--disable-all-tests}
253
@cindex all tests enabled
254
@cindex tests, all enabled.
255
Some of the tests (at the time of writing just one) will not compile
256
without error.  If enabled with this flag, all test programs will be
257
compiled with @command{make check}.
258
 
259
This flag is intended for those working on the test package, who wish to
260
get the missing test(s) working.
261
 
262 19 jeremybenn
@end table
263
 
264
@node Build and Install
265
@section Building and Installing
266 82 jeremybenn
Build the tool with:
267 19 jeremybenn
 
268
@example
269
@kbd{make all}
270 82 jeremybenn
@end example
271
 
272
If you have the OpenRISC tool chain and DejaGNU installed, you can
273
verify the tool as follows (otherwise omit this step):
274
 
275
@example
276
@kbd{make check}
277
@end example
278
 
279
Install the tool with:
280
 
281
@example
282 19 jeremybenn
@kbd{make install}
283
@end example
284
 
285
This will install the three variations of the @value{OR1KSIM} tool,
286
@command{or32-uclinux-sim}, @command{or32-uclinux-psim} and
287
@command{or32-uclinux-mpsim}, the @value{OR1KSIM} library, @file{libsim}, the
288
header file, @file{or1ksim.h} and this documentation in @command{info} format.
289
 
290
@quotation Note
291
Testing @value{OR1KSIM} with @kbd{make check} is not yet supported.
292
@end quotation
293
 
294
The documentation may be created and installed in alternative formats (PDF,
295
Postscript, DVI, HTML) with for example:
296
 
297
@example
298
@kbd{make pdf}
299
@kbd{make install-pdf}
300
@end example
301
 
302
@node Known Issues
303
@section Known Problems and Issues
304
 
305
The following problems and issues are known about with @value{OR1KSIM}
306 82 jeremybenn
@value{VERSION}.  The OpenRISC tracker may be used to see the current
307
state of these issues and to raise new problems and feature requests.  It
308 19 jeremybenn
may be found at @url{http://www.opencores.org/ptracker.cgi/view/or1k/398}.
309
 
310
@itemize @bullet
311
@item
312
The Supervision Register Little Endian Enable (LEE) bit is
313 82 jeremybenn
ignored.  @value{OR1KSIM} can be built for either little endian or big endian
314 19 jeremybenn
use, but that behavior cannot be changed dynamically.
315
 
316
@item
317
The NPC is a read/write register, but after being written it clears the
318 82 jeremybenn
pipeline.  This means that if the processor is stalled, the value should
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subsequently read back as 0, until the processor is unstalled and able
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to refill its pipeline.  By default @value{OR1KSIM} always reports back the value
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of NPC, even when it has been written while stalled.
322
 
323
There is now an option, @code{--strict-npc}, which will enforce this
324 82 jeremybenn
behavior.  At some stage in the future it will become the default
325 19 jeremybenn
behavior, but for now it is an option, since its use will break GDB.
326
 
327
@item
328 82 jeremybenn
The memory components are given names in the configuration file.  However
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there is currently no way for @value{OR1KSIM} to report that name back to the
330
user (for example to identify which memory block corresponds to a
331
particular access).
332
 
333
@item
334
@value{OR1KSIM} allows the processor to be stalled (from the command
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line), even if there is no debugger present.  This seems to be a
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meaningless operation.
337
 
338
@item
339
@value{OR1KSIM} is not reentrant, so a program cannot instantiate
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multiple instances using the library.  This is clearly a problem when
341
considering multi-core applications.  However it stems from the original
342
design, and can only be fixed by a complete rewrite.  The entire source
343 19 jeremybenn
code uses static global constants liberally!
344
 
345
@item
346
There is no support for floating point instructions currently in
347 82 jeremybenn
@value{OR1KSIM}.  However this is a work in progress and should be available in
348
the future.
349 19 jeremybenn
 
350
@end itemize
351
 
352
@node Usage
353
@chapter Usage
354
@cindex running @value{OR1KSIM}
355
 
356
@menu
357
* Standalone Simulator::
358
* Profiling Utility::
359
* Memory Profiling Utility::
360
* Simulator Library::
361
@end menu
362
 
363
@node Standalone Simulator
364
@section Standalone Simulator
365
@cindex command line for @value{OR1KSIM} standalone use
366
 
367
The general form the standalone command is:
368
 
369
@example
370
or32-uclinux-sim [-vhi] [-f @var{file}] [--nosrv] [--srv=[@var{n}]] [-d @var{str}]
371
                 [--enable-profile] [--enable-mprofile] [@var{file}]
372
@end example
373
 
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Many of the options have both a short and a long form.  For example
375 19 jeremybenn
@code{-h} or @code{--help}.
376
 
377
@table @code
378
 
379
@item -v
380
@itemx --version
381
@cindex @code{-v}
382
@cindex @code{--version}
383
Print out the version and copyright notice for @value{OR1KSIM} and
384
exit.
385
 
386
@item -h
387
@itemx --help
388
@cindex @code{-h}
389
@cindex @code{--help}
390
Print out help about the command line options and what they mean.
391
 
392
@item -f @var{file}
393
@itemx --file @var{file}
394
@cindex @code{-f}
395
@cindex @code{--file}
396
Read configuration commands from the specified file, looking first in
397
the current directory, and otherwise in the @file{$HOME/.or1k}
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directory.  If this argument is not specified, the file @file{sim.cfg}
399
in those two locations is used.  Failure to find the file is a fatal
400
error.  @xref{Configuration, , Configuration}, for detailed information
401 19 jeremybenn
on configuring @value{OR1KSIM}.
402
 
403
@item --nosrv
404
@cindex @code{--nosrv}
405 82 jeremybenn
Do not start up the debug server.  This overrides any setting specified
406
in the configuration file.  This option may not be specified with
407
@code{--srv}.  If it is, a rude message is printed and the
408 19 jeremybenn
@code{--nosrv} option is ignored.
409
 
410
@item --srv
411
@item --srv=@var{n}
412
@cindex @code{--srv}
413 82 jeremybenn
Start up the debug server.  If the parameter, @var{n}, is specified,
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use that as the TCP/IP port for the server, otherwise a random value
415 82 jeremybenn
from the private port range (41920-65535) will be used.  This option
416
may not be specified with @code{--nosrv}.  If it is, a rude message is
417 19 jeremybenn
printed and the @code{--nosrv} option is ignored.
418
 
419
@item -d=@var{config_string}
420
@itemx --debug-config=@var{config_string}
421
@cindex @code{-d}
422
@cindex @code{--debug-config}
423 82 jeremybenn
Enable selected debug messages in @value{OR1KSIM}.  This parameter is
424
for use by developers only, and is not covered further here.  See the
425 19 jeremybenn
source code for more details.
426
 
427
@item -i
428
@itemx --interactive
429
@cindex @code{-i}
430
@cindex @code{--interactive}
431
After starting, drop into the @value{OR1KSIM} interactive command
432
shell.
433
 
434
@item --strict-npc
435
@cindex @code{--strict-npc}
436
In real hardware, setting the next program counter (NPC, SPR 16),
437 82 jeremybenn
flushes the processor pipeline.  The consequence of this is that until
438
the pipeline refills, reading the NPC will return zero.  This is typically
439 19 jeremybenn
the case when debugging, since the processor is stalled.
440
 
441
Historically, @value{OR1KSIM} has always returned the value of the NPC,
442 82 jeremybenn
irrespective of when it is changed.  If the @code{--strict-npc} option is
443
used, then @value{OR1KSIM} will mirror real hardware more accurately.  If the NPC
444 19 jeremybenn
is changed while the processor is stalled, subsequent reads of its value
445
will return 0 until the processor is unstalled.
446
 
447
This is not currently the default behavior, since tools such as GDB have
448 82 jeremybenn
been implemented assuming the historic @value{OR1KSIM} behavior.  However at some
449 19 jeremybenn
time in the future it will become the default.
450
 
451
@item --enable-profile
452
@cindex @code{--enable-profile}
453
Enable instruction profiling.
454
 
455
@item --enable-mprofile
456
@cindex @code{--enable-mprofile}
457
Enable memory profiling.
458
 
459
@end table
460
 
461
@node Profiling Utility
462
@section Profiling Utility
463
@cindex profiling for @value{OR1KSIM}
464
@cindex instruction profiling for @value{OR1KSIM}
465
 
466
This utility analyses instruction profile data generated by
467 82 jeremybenn
@value{OR1KSIM}.  It may be invoked as a standalone command, or from
468
the @value{OR1KSIM} CLI.  The general form the standalone command is:
469 19 jeremybenn
 
470
@example
471
or32-uclinux-profile [-vhcq] [-g=@var{file}]
472
@end example
473
 
474 82 jeremybenn
Many of the options have both a short and a long form.  For example
475 19 jeremybenn
@code{-h} or @code{--help}.
476
 
477
@table @code
478
 
479
@item -v
480
@itemx --version
481
@cindex @code{-v} (profiling utility)
482
@cindex @code{--version} (profiling utility)
483
Print out the version and copyright notice for the @value{OR1KSIM}
484
profiling utility and exit.
485
 
486
@item -h
487
@itemx --help
488
@cindex @code{-h} (profiling utility)
489
@cindex @code{--help} (profiling utility)
490
Print out help about the command line options and what they mean.
491
 
492
@item -c
493
@itemx --cumulative
494
@cindex @code{-c}
495
@cindex @code{--cumulative}
496
Show cumulative sum of cycles in functions
497
 
498
@item -q
499
@itemx --quiet
500
@cindex @code{-q}
501
@cindex @code{--quiet}
502
Suppress messages
503
 
504
@item -g=@var{file}
505
@itemx --generate=@var{file}
506
@cindex @code{-g}
507
@cindex @code{--generate}
508 82 jeremybenn
The data file to analyse.  If omitted, the default file,
509 19 jeremybenn
@file{sim.profile} is used.
510
 
511
@end table
512
 
513
@node Memory Profiling Utility
514
@section Memory Profiling Utility
515
@cindex memory profiling version of @value{OR1KSIM}
516
 
517
This utility analyses memory profile data generated by
518 82 jeremybenn
@value{OR1KSIM}.  It may be invoked as a standalone command, or from
519
the @value{OR1KSIM} CLI.  The general form the standalone command is:
520 19 jeremybenn
 
521
@example
522
or32-uclinux-mprofile  [-vh] [-m=@var{m}] [-g=@var{n}] [-f=@var{file}] @var{from} @var{to}
523
@end example
524
 
525 82 jeremybenn
Many of the options have both a short and a long form.  For example
526 19 jeremybenn
@code{-h} or @code{--help}.
527
 
528
@table @code
529
 
530
@item -v
531
@itemx --version
532
@cindex @code{-v} (memory profiling utility)
533
@cindex @code{--version} (memory profiling utility)
534
Print out the version and copyright notice for the @value{OR1KSIM}
535
memory profiling utility and exit.
536
 
537
@item -h
538
@itemx --help
539
@cindex @code{-h} (memory profiling utility)
540
@cindex @code{--help} (memory profiling utility)
541
Print out help about the command line options and what they mean.
542
 
543
@item -m=@var{m}
544
@itemx --mode=@var{m}
545
@cindex @code{-m}
546
@cindex @code{--mode}
547 82 jeremybenn
Specify the mode out output.  Permitted options are
548 19 jeremybenn
 
549
@table @code
550
 
551
@item detailed
552
@itemx d
553 82 jeremybenn
Detailed output.  This is the default if no mode is specified.
554 19 jeremybenn
 
555
@item pretty
556
@itemx p
557
Pretty printed output.
558
 
559
@item access
560
@itemx a
561
Memory accesses only.
562
 
563
@item width
564
@itemx w
565
Access width only.
566
 
567
@end table
568
 
569
@item -g=@var{n}
570
@itemx --group=@var{n}
571
@cindex @code{-g}
572
@cindex @code{--group}
573
Group @math{2^n} bits of successive addresses together.
574
 
575
@item -f=@var{file}
576
@itemx --filename=@var{file}
577
@cindex @code{-f}
578
@cindex @code{--filename}
579 82 jeremybenn
The data file to analyse.  If not specified, the default,
580 19 jeremybenn
@file{sim.profile} is used.
581
 
582
@item @var{from}
583
@itemx @var{to}
584
@cindex memory profiling start address
585
@cindex memory profiling end address
586
@var{from} and @var{to} are respectively the start and end address of
587
the region of memory to be analysed.
588
 
589
@end table
590
 
591
@node Simulator Library
592
@section Simulator Library
593
@cindex library version of @value{OR1KSIM}
594
 
595
@value{OR1KSIM} may be used as a static of dynamic library,
596 82 jeremybenn
@file{libsim.a} or @file{libsim.so}.  When compiling with the static
597 19 jeremybenn
library, the flag, @code{-lsim} should be added to the link command.
598
 
599
The header file @file{or1ksim.h} contains appropriate declarations of
600 82 jeremybenn
the functions exported by the @value{OR1KSIM} library.  These are:
601 19 jeremybenn
 
602
@deftypefn {@file{or1ksim.h}} int or1ksim_init (const char *@var{config_file}, const char *@var{image_file}, void *@var{class_ptr}, unsigned long int (*@var{upr})(void *@var{class_ptr}, unsigned long int @var{addr}, unsigned long int @var{mask}), void (*@var{upw})(void *@var{class_ptr}, unsigned long int @var{addr}, unsigned long int @var{mask}, unsigned long int @var{wdata}))
603
 
604
The initialization function is supplied with the name of a
605
configuration file, @var{config_file}, an executable image, @var{image_file}, a pointer to the calling
606
class, @var{class_ptr} (since the library may be used from C++) and
607
two up-call functions, one for reads, @var{upr}, and one for writes,
608
@var{upw}.
609
 
610
@xref{Configuration, , Configuration}, for detailed information on
611
configuring @value{OR1KSIM} and the format of the configuration file.
612
 
613
@var{upw} is called for any write to an address external to the model
614
(determined by a @code{generic} section in the configuration
615 82 jeremybenn
file).  @var{upr} is called for any reads to an external address.  The
616 19 jeremybenn
@var{class_ptr} is passed back with these upcalls, allowing the
617
function to associate the call with the class which originally
618
initialized the library.
619
 
620
@var{mask} indicates which bytes in the word are to be written or
621 82 jeremybenn
read.  Bytes to be read/written should have 0xff set in
622
@var{mask}.  Otherwise the byte should be zero.
623 19 jeremybenn
 
624
@var{addr}, @var{mask}, @var{wdata} and the result from @var{upr} all
625 82 jeremybenn
use host-endianess, @emph{not} model-endianess.  The internal
626 19 jeremybenn
@value{OR1KSIM} routines manage all the conversion.
627
 
628
@end deftypefn
629
 
630
@deftypefn {@file{or1ksim.h}} int or1ksim_run (double  @var{duration})
631
 
632
Run the simulator for the simulated duration specified (in seconds).
633
 
634
@end deftypefn
635
 
636
@deftypefn {@file{or1ksim.h}} void or1ksim_reset_duration (double @var{duration})
637
 
638
Change the duration of a run specified in an earlier call to
639 82 jeremybenn
@code{or1ksim_run}.  Typically this is called from an upcall, which
640 19 jeremybenn
realizes it needs to change the duration of the run specified in the
641
call to @code{or1ksim_run} that has been interrupted by the upcall.
642
 
643
The time specified is the amount of time that the run must continue
644
for (i.e the duration from @emph{now}, not the duration from the original
645
call to @code{or1ksim_run}).
646
 
647
@end deftypefn
648
 
649
@deftypefn {@file{or1ksim.h}} void  or1ksim_set_time_point ()
650
 
651 82 jeremybenn
Set a timing point.  For use with @code{or1ksim_get_time_period}.
652 19 jeremybenn
 
653
@end deftypefn
654
 
655
@deftypefn {@file{or1ksim.h}} double  or1ksim_get_time_period ()
656
 
657
Return the simulated time (in seconds) that has elapsed since the last
658
call to @code{or1ksim_set_time_point}.
659
 
660
@end deftypefn
661
 
662
@deftypefn {@file{or1ksim.h}} int  or1ksim_is_le ()
663
 
664
Return 1 (logical true) if the @value{OR1KSIM} simulation is
665
little-endian, 0 otherwise.
666
 
667
@end deftypefn
668
 
669
@deftypefn {@file{or1ksim.h}} unsigned long int  or1ksim_clock_rate ()
670
 
671 82 jeremybenn
Return the @value{OR1KSIM} clock rate (in Hz).  This is the value
672 19 jeremybenn
specified in the configuration file.
673
 
674
@end deftypefn
675
 
676
@deftypefn {@file{or1ksim.h}} void or1ksim_interrupt (int  @var{i})
677
 
678 82 jeremybenn
Generate an edge-triggered interrupt on interrupt line @var{i}.  The interrupt
679
is then immediately cleared automatically.  A warning will be generated and the
680 19 jeremybenn
interrupt request ignored if level sensitive interrupts have been configured
681
with the programmable interrupt controller (@pxref{Interrupt Configuration, ,
682
Interrupt Configuration}).
683
 
684
@end deftypefn
685
 
686
@deftypefn {@file{or1ksim.h}} void or1ksim_interrupt_set (int  @var{i})
687
 
688 82 jeremybenn
Assert a level-triggered interrupt on interrupt line @var{i}.  The interrupt
689 19 jeremybenn
must be cleared separately by an explicit call to
690 82 jeremybenn
@code{or1ksim_interrupt_clear}.  A warning will be generated, and the interrupt
691 19 jeremybenn
request ignored if edge sensitive interrupts have been configured with the
692
programmable interrupt controller (@pxref{Interrupt Configuration, , Interrupt
693
Configuration}).
694
 
695
@end deftypefn
696
 
697
@deftypefn {@file{or1ksim.h}} void or1ksim_interrupt_clear (int  @var{i})
698
 
699
Clear a level-triggered interrupt on interrupt line @var{i}, which was
700 82 jeremybenn
previously asserted by a call to @code{or1ksim_interrupt_set}.  A warning will
701 19 jeremybenn
be generated, and the interrupt request ignored if edge sensitive interrupts
702
have been configured with the programmable interrupt controller
703
(@pxref{Interrupt Configuration, , Interrupt Configuration}).
704
 
705
@end deftypefn
706
 
707
The libraries will be installed in the @file{lib} sub-directory of the
708
main installation directory (as specified with the @option{--prefix}
709
option to the @command{configure} script).
710
 
711
For example if the main installation directory is @file{/opt/or1ksim},
712 82 jeremybenn
the library will be found in the @file{/opt/or1ksim/lib} directory.  It
713 19 jeremybenn
is available as both a static library (@file{libsim.a}) and a shared
714
object (@file{libsim.so}).
715
 
716
To link against the library add the @option{-lsim} flag when linking
717
and do one of the following:
718
 
719
@itemize @bullet
720
 
721
@item
722
Add the library directory to the @code{LD_LIBRARY_PATH} environment
723 82 jeremybenn
variable during execution.  For example:
724 19 jeremybenn
 
725
@example
726
export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
727
@end example
728
 
729
@item
730
Add the library directory to the @code{LD_RUN_PATH} environment
731 82 jeremybenn
variable during linking.  For example:
732 19 jeremybenn
 
733
@example
734
export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
735
@end example
736
 
737
@item
738
Use the linker @option{--rpath} option and specify the library
739 82 jeremybenn
directory when linking your program.  For example
740 19 jeremybenn
 
741
@example
742 82 jeremybenn
gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
743 19 jeremybenn
@end example
744
 
745
@item
746
Add the library directory to @file{/etc/ld.so.conf}
747
 
748
@end itemize
749
 
750
@node Configuration
751
@chapter Configuration
752
@cindex configuring @value{OR1KSIM}
753
 
754 82 jeremybenn
@value{OR1KSIM} is configured through a configuration file.  This is specified
755 19 jeremybenn
through the @code{-f} parameter to the @value{OR1KSIM} command, or passed as a
756 82 jeremybenn
string when initializing the @value{OR1KSIM} library.  If no file is specified,
757
the default @file{sim.cfg} is used.  The file is looked for first in the
758 19 jeremybenn
current directory, then in the @file{$HOME/.or1k} directory of the user.
759
 
760
@menu
761
* Configuration File Format::
762
* Simulator Configuration::
763
* Core OpenRISC Configuration::
764
* Peripheral Configuration::
765
@end menu
766
 
767
@node Configuration File Format
768
@section Configuration File Format
769
@cindex configuration file structure
770
 
771
The configuration file is a plain text file.
772
 
773
@menu
774
* Configuration File Preprocessing::
775
* Configuration File Syntax::
776
@end menu
777
 
778
@node Configuration File Preprocessing
779
@subsection Configuration File Preprocessing
780
 
781 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
782 19 jeremybenn
@code{/*} and @code{*/}).
783
 
784
Configure files may be included, using
785
 
786
@example
787
include @var{filename_to_include}
788
@end example
789
 
790
@node Configuration File Syntax
791
@subsection Configuration File Syntax
792
 
793
The configuration file is divided into a series of sections, with the general
794
form:
795
 
796
@example
797
section @var{section_name}
798
 
799
  <contents>...
800
 
801
end
802
@end example
803
 
804
Sections may also have sub-sections within them (currently only the
805
ATA/ATAPI disc interface uses this).
806
 
807
Within a section, or sub-section are a series of parameter assignments, one
808
per line, withe the general form
809
 
810
@example
811
  @var{parameter} = @var{value}
812
@end example
813
 
814
Depending on the parameter, the value may be a named value (an enumeration),
815
an integer (specified in any format acceptable in C) or a string in doubple
816 82 jeremybenn
quotes.  For flag parameters, the value 1 is used to mean ``true'' or ``on''
817
and the value ``0'' to mean ``false'' or ``off''.  An example from a memory
818 19 jeremybenn
section shows each of these
819
 
820
@example
821
section memory
822
  type    = random
823
  pattern = 0x00
824
  name    = "FLASH"
825
  ...
826
end
827
@end example
828
 
829
Many parameters are optional and take reasonable default values if not
830 82 jeremybenn
specified.  However there are some parameters (for example the
831 19 jeremybenn
@code{ce} parameter in @code{@w{section memory}}) @emph{must} be
832
specified.
833
 
834
Subsections are introduced by a keyword, with a parameter value (no
835
@code{=} sign), and end with the same keyword prefixed by
836 82 jeremybenn
@code{end}.  Thus the ATA/ATAPI inteface (@code{@w{section ata}}) has a
837 19 jeremybenn
@code{device} subsection, thus:
838
 
839
@example
840
section ata
841
  ...
842
  device 0
843
    type    = 1
844
    file = "@var{filename}"
845
    ...
846
  enddevice
847
  ...
848
end
849
@end example
850
 
851
Some sections (for example @code{@w{section sim}}) should appear only
852 82 jeremybenn
once.  Others (for example @code{@w{section memory}} may appear
853 19 jeremybenn
multiple times.
854
 
855
Sections may be omitted, @emph{unless they contain parameters which
856 82 jeremybenn
are non-optional}.  If the section describes a part of the simulator
857 19 jeremybenn
which is optional (for example whether it has a UART), then that
858 82 jeremybenn
functionality will not be provided.  If the section describes a part of
859 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
860
parameters of that section will take their default values.
861
 
862
All optional parts of the functionality are always described by
863
sections including a @code{enabled} parameter, which can be set to 0
864
to ensure that functionality is explicitly omitted.
865
 
866
Even if a section is disabled, all its parameters will be read and
867 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
868 19 jeremybenn
the @value{OR1KSIM} command line (@pxref{Interactive Command Line, ,
869
Interactive Command Line}).
870
 
871
@quotation Tip
872
It generally clearer to have sections describing @emph{all}
873
components, with omitted functionality explicitly indicated by setting
874
the @code{enabled} parameter to 0
875
@end quotation
876
 
877
The following sections describe the various configuration sections and the
878
parameters which may be set in each.
879
 
880
@node Simulator Configuration
881
@section Simulator Configuration
882
 
883
@menu
884
* Simulator Behavior::
885
* Verification API Configuration::
886
* CUC Configuration::
887
@end menu
888
 
889
@node Simulator Behavior
890
@subsection Simulator Behavior
891
@cindex configuring the behavior of @value{OR1KSIM}
892
@cindex simulator configuration
893
@cindex @code{section sim}
894 82 jeremybenn
Simulator behavior is described in @code{section sim}.  This section
895
should appear only once.  The following parameters may be specified.
896 19 jeremybenn
 
897
@table @code
898
 
899
@item verbose = 0|1
900
@cindex @code{verbose} (simulator configuration)
901 82 jeremybenn
If 1 (true), print extra messages.  Default 0.
902 19 jeremybenn
 
903
@item debug = 0-9
904
@cindex @code{debug} (simulator configuration)
905 82 jeremybenn
 
906
value the greater the number of messages.  Default 0.  Negative values
907
will be treated as 0 (with a warning).  Values that are too large will
908 19 jeremybenn
be treated as 9 (with a warning).
909
 
910
@item profile = 0|1
911
@cindex @code{profile} (simulator configuration)
912
If 1 (true) generate a profiling file using the file specified in the
913 82 jeremybenn
@code{prof_file} parameter or otherwise @file{sim.profile}.  Default 0.
914 19 jeremybenn
 
915
@item prof_file = ``@var{filename}''
916
@cindex @code{prof_file} (simulator configuration)
917
@cindex @code{prof_fn} (simulator configuration - deprecated)
918 82 jeremybenn
Specifies the file to be used with the @code{profile} parameter.  Default
919
@file{sim.profile}.  For backwards compatibility, the alternative name
920 19 jeremybenn
@code{prof_fn} is supported for this parameter, but deprecated.
921
 
922
@item mprofile = 0|1
923
@cindex @code{mprofile} (simulator configuration)
924
If 1 (true) generate a memory profiling file using the file specified in the
925 82 jeremybenn
@code{mprof_file} parameter or otherwise @file{sim.mprofile}.  Default 0.
926 19 jeremybenn
 
927
@item mprof_fn = ``@var{filename}''
928
@cindex @code{mprof_file} (simulator configuration)
929
@cindex @code{mprof_fn} (simulator configuration - deprecated)
930 82 jeremybenn
Specifies the file to be used with the @code{mprofile} parameter.  Default
931
@file{sim.mprofile}.  For backwards compatibility, the alternative name
932 19 jeremybenn
@code{mprof_fn} is supported for this parameter, but deprecated.
933
 
934
@item history = 0|1
935
@cindex @code{history} (simulator configuration)
936 82 jeremybenn
If 1 (true) track execution flow.  Default 0.
937 19 jeremybenn
 
938
@quotation Note
939
Setting this parameter seriously degrades performance.
940
@end quotation
941
 
942
@quotation Note
943
If this execution flow tracking is enabled, then @code{dependstats}
944
must be enabled in the CPU configuration section (@pxref{CPU
945
Configuration, , CPU Configuration}).
946
@end quotation
947
 
948
@item exe_log = 0|1
949
@cindex @code{exe_log} (simulator configuration)
950 82 jeremybenn
If 1 (true), generate an execution log.  Log is written to the file specified
951
in parameter @code{exe_log_file}.  Default 0.
952 19 jeremybenn
 
953
@quotation Note
954
Setting this parameter seriously degrades performance.
955
@end quotation
956
 
957
@item exe_log_type = default|hardware|simple|software
958
@cindex @code{exe_log_type} (simulator configuration)
959
Type of execution log to produce.
960
 
961
@table @code
962
 
963
@item default
964
@cindex @code{exe_log_type=default} (simulator configuration)
965 82 jeremybenn
Produce default output for the execution log.  In the current implementation
966 19 jeremybenn
this is the equivalent of @code{hardware}.
967
 
968
@item hardware
969
@cindex @code{exe_log_type=hardware} (simulator configuration)
970
After each instruction execution, log the number of instructions executed so
971
far, the next instruction to execute (in hex), the general purpose registers
972
(GPRs), status register, exception program counter, exception, effective
973
address register and exception status register.
974
 
975
@item simple
976
@cindex @code{exe_log_type=simple} (simulator configuration)
977
After each instruction execution, log the number of instructions executed so
978
far and the next instruction to execute, symbolically disassembled.
979
 
980
@item software
981
@cindex @code{exe_log_type=software} (simulator configuration)
982
After each instruction execution, log the number of instructions executed so
983 82 jeremybenn
far and the next instruction to execute, symbolically disassembled.  Also show
984 19 jeremybenn
the value of each operand to the instruction.
985
 
986
@end table
987
 
988 82 jeremybenn
Default value @code{hardware}.  Any unrecognized keyword (case
989 19 jeremybenn
insensitive) will be treated as the default with a warning.
990
 
991
@quotation Note
992
Execution logs can be @emph{very} big.
993
@end quotation
994
 
995
@item exe_log_start = @var{value}
996
@cindex @code{exe_log_start} (simulator configuration)
997 82 jeremybenn
Address of the first instruction to start logging.  Default 0.
998 19 jeremybenn
 
999
@item exe_log_end = @var{value}
1000
@cindex @code{exe_log_end} (simulator configuration)
1001 82 jeremybenn
Address of the last instruction to log.  Default no limit (i.e once started
1002 19 jeremybenn
logging will continue until the simulator exits).
1003
 
1004
@item exe_log_marker = @var{value}
1005
@cindex @code{exe_log_marker} (simulator configuration)
1006
Specifies the number of instructions between printing horizontal
1007 82 jeremybenn
markers.  Default is to produce no markers.
1008 19 jeremybenn
 
1009
@item exe_log_file = @var{filename}
1010
@cindex @code{exe_log_file} (simulator configuration)
1011
@cindex @code{exe_log_fn} (simulator configuration - deprecated)
1012 82 jeremybenn
Filename for the execution log filename if @code{exe_log} is enabled.  Default
1013
@file{executed.log}.  For backwards compatibility, the alternative name
1014 19 jeremybenn
@code{exe_log_fn} is supported for this parameter, but deprecated.
1015
 
1016
@item clkcycle = @var{value}[ps|ns|us|ms]
1017
@cindex @code{clkcycle} (simulator configuration)
1018 82 jeremybenn
Specify the time taken by one clock cycle.  If no units are specified,
1019
@code{ps} is assumed.  Default 4000ps (250MHz).
1020 19 jeremybenn
 
1021
@end table
1022
 
1023
@node Verification API Configuration
1024
@subsection Verification API (VAPI) Configuration
1025
@cindex configuring the Verification API (VAPI)
1026
@cindex Verification API configuration
1027
@cindex VAPI configuration
1028
@cindex @code{section vapi}
1029
The Verification API (VAPI) provides a TCP/IP interface to allow
1030
components of the simulation to be controlled
1031 82 jeremybenn
externally.  @xref{Verification API, , Verification API}, for more
1032 19 jeremybenn
details.
1033
 
1034
Verification API configuration is described in @code{section
1035 82 jeremybenn
vapi}.  This section may appear at most once.  The following parameters
1036 19 jeremybenn
may be specified.
1037
 
1038
@table @code
1039
 
1040
@item enabled = 0|1
1041
@cindex @code{enabled} (verification API configuration)
1042 82 jeremybenn
If 1 (true), verification API is enabled and its server started.  If 0
1043 19 jeremybenn
(the default), it is disabled.
1044
 
1045
@item server_port = @var{value}
1046
@cindex @code{server_port} (verification API configuration)
1047
When VAPI is enabled, communication will be via TCP/IP on the port
1048 82 jeremybenn
specified by @var{value}.  The value must lie in the range 1 to 65535.
1049 19 jeremybenn
The default value is 50000.
1050
 
1051
@quotation Tip
1052
@cindex TCP/IP port range
1053
@cindex port range for TCP/IP
1054
@cindex dynamic ports, use of
1055
@cindex private ports, use of
1056 82 jeremybenn
There is no registered port for @value{OR1KSIM} VAPI.  Good practice
1057 19 jeremybenn
suggests users should adopt port values in the @dfn{Dynamic} or
1058 82 jeremybenn
@dfn{Private} port range, i.e.  49152-65535.
1059 19 jeremybenn
@end quotation
1060
 
1061
@item log_enabled = 0|1
1062
@cindex @code{log_enabled} (verification API configuration)
1063 82 jeremybenn
If 1 (true), all VAPI requests and sent commands will be logged.  If 0
1064
(the default), logging is diabled.  Logs are written to the file
1065 19 jeremybenn
specified by the @code{vapi_log_file} field (see below).
1066
 
1067
@quotation Caution
1068
This can generate a substantial amount of file I/O and seriously
1069
degrade simulator performance.
1070
@end quotation
1071
 
1072
@item hide_device_id = 0|1
1073
@cindex @code{hide_device_id} (verification API configuration)
1074 82 jeremybenn
If 1 (true) don't log the device ID.  If 0 (the default), log the
1075
device ID.  This feature (when set to 1) is provided for backwards
1076 19 jeremybenn
compatibility with an old version of VAPI.
1077
 
1078
@item vapi_log_file = "@var{filename}"
1079
@cindex @code{vapi_log_file} (verification API configuration)
1080
@cindex @code{vapi_log_fn} (verification API configuration - deprecated)
1081
Use @file{filename} as the file for logged data is logging is enabled
1082 82 jeremybenn
(see @code{log_enabled} above).  The default is @code{"vapi.log"}.  For
1083 19 jeremybenn
backwards compatibility, the alternative name @code{vapi_log_fn} is
1084
supported for this parameter, but deprecated.
1085
 
1086
@end table
1087
 
1088
@node CUC Configuration
1089
@subsection Custom Unit Compiler (CUC) Configuration
1090
@cindex configuring the Custom Unit Compiler (CUC)
1091
@cindex Custom Unit Compiler Configuration
1092
@cindex CUC configuration
1093
@cindex @code{section cuc}
1094
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1095 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1096
beyond the initial prototype phase.  The configuration parameters are
1097 19 jeremybenn
described here for the record.
1098
 
1099 82 jeremybenn
CUC configuration is described in @code{@w{section cuc}}.  This section
1100
may appear at most once.  The following parameters may be specified.
1101 19 jeremybenn
 
1102
@table @code
1103
 
1104
@item memory_order = none|weak|strong|exact
1105
@cindex @code{memory_order} (CUC configuration)
1106
This parameter specifies the memory ordering required:
1107
 
1108
@table @code
1109
 
1110
@item memory_order=none
1111
@cindex @code{memory_order=none} (CUC configuration)
1112 82 jeremybenn
Different memory ordering, even if there are dependencies.  Bursts can
1113 19 jeremybenn
be made, width can change.
1114
 
1115
@cindex @code{memory_order=weak} (CUC configuration)
1116 82 jeremybenn
Different memory ordering, even if there are dependencies.  If
1117 19 jeremybenn
dependencies cannot occur, then bursts can be made, width can change.
1118
 
1119
@cindex @code{memory_order=strong} (CUC configuration)
1120 82 jeremybenn
Same memory ordering.  Bursts can be made, width can change.
1121 19 jeremybenn
 
1122
@cindex @code{memory_order=exact} (CUC configuration)
1123
Exactly the same memory ordering and widths.
1124
 
1125
@end table
1126
 
1127 82 jeremybenn
The default value is @code{memory_order=exact}.  Invalid memory
1128 19 jeremybenn
orderings are ignored with a warning.
1129
 
1130
@item calling_convention = 0|1
1131
@cindex @code{calling_convention} (CUC configuration)
1132 82 jeremybenn
If 1 (true), programs follow OpenRISC calling conventions.  If 0 (the
1133 19 jeremybenn
default), they may use other convenitions.
1134
 
1135
@item enable_bursts = 0 | 1
1136
@cindex @code{enable_bursts} (CUC configuration)
1137 82 jeremybenn
If 1 (true), bursts are detected.  If 0 (the default), bursts are not
1138 19 jeremybenn
detected.
1139
 
1140
@item no_multicycle = 0 | 1
1141
@cindex @code{no_multicycle} (CUC configuration)
1142 82 jeremybenn
If 1 (true), no multicycle logic paths will be generated.  If 0 (the
1143 19 jeremybenn
default), multicycle logic paths will be generated.
1144
 
1145
@item timings_file = "@var{filename}"
1146
@cindex @code{timings_file} (CUC configuration)
1147
@cindex @code{timings_fn} (CUC configuration - deprecated)
1148 82 jeremybenn
@var{filename} specifies a file containing timing information.  The
1149
default value is @code{"virtex.tim"}.  For backwards compatibility, the
1150 19 jeremybenn
alternative name @code{timings_fn} is supported for this parameter,
1151
but deprecated.
1152
 
1153
@end table
1154
 
1155
@node Core OpenRISC Configuration
1156
@section Configuring the OpenRISC Architectural Components
1157
 
1158
@menu
1159
* CPU Configuration::
1160
* Memory Configuration::
1161
* Memory Management Configuration::
1162
* Cache Configuration::
1163
* Interrupt Configuration::
1164
* Power Management Configuration::
1165
* Branch Prediction Configuration::
1166
* Debug Interface Configuration::
1167
@end menu
1168
 
1169
@node CPU Configuration
1170
@subsection CPU Configuration
1171
@cindex configuring the CPU
1172
@cindex configuring the processor
1173
@cindex CPU configuration
1174
@cindex processor configuration
1175
@cindex @code{section cpu}
1176 82 jeremybenn
CPU configuration is described in @code{section cpu}.  This section
1177
should appear only once.  At present @value{OR1KSIM} does not model multi-CPU
1178
systems.  The following parameters may be specified.
1179 19 jeremybenn
 
1180
@table @code
1181
 
1182
@item ver = @var{value}
1183
@item cfg = @var{value}
1184
@item rev = @var{value}
1185
@cindex @code{ver} (CPU configuration)
1186
@cindex @code{rev} (CPU configuration)
1187
The values are used to form the corresponding fields in the @code{VR}
1188 82 jeremybenn
Special Purpose Register (SPR 0).  Default values 0.  A warning is given
1189 19 jeremybenn
and the value truncated if it is too large (8 bits for @code{ver} and
1190
@code{cfg}, 6 bits for @code{rev}).
1191
 
1192
@item upr = @var{value}
1193
@cindex @code{upr} (CPU configuration)
1194
Used as the value of the Unit Present Register (UPR) Special Purpose Register
1195 82 jeremybenn
(SPR 1) to @var{value}.  Default value is 0x0000075f, i.e.
1196 19 jeremybenn
@itemize @bullet
1197
@item
1198
UPR present (0x00000001)
1199
@item
1200
Data cache present (0x00000002)
1201
@item
1202
Instruction cache present (0x00000004)
1203
@item
1204
Data MMY present (0x00000008)
1205
@item
1206
Instruction MMU present (0x00000010)
1207
@item
1208
Debug unit present (0x00000040)
1209
@item
1210
Power management unit present (0x00000100)
1211
@item
1212
Programmable interrupt controller present (0x00000200)
1213
@item
1214
Tick timer present (0x00000400)
1215
@end itemize
1216
 
1217
However, with the exection of the UPR present (0x00000001) and tick
1218
timer present, the various
1219
fields will be modified with the values specified in their corresponding
1220
configuration sections.
1221
 
1222
@item cfgr = @var{value}
1223
@cindex @code{cfgr} (CPU configuration)
1224
Sets the CPU configuration register (Special Purpose Register 2) to
1225 82 jeremybenn
@var{value}.  Default value is 0x00000020, i.e.  support for the ORBIS32
1226
instruction set.  Attempts to set any other value are accepted, but
1227 19 jeremybenn
issue a warning that there is no support for the instruction set.
1228
 
1229
@item sr = @var{value}
1230
@cindex @code{sr} (CPU configuration)
1231
Sets the supervision register Special Purpose Register (SPR 0x11) to
1232 82 jeremybenn
@var{value}.  Default value is 0x00008001, i.e.  start in supervision
1233 19 jeremybenn
mode (0x00000001) and set the ``Fixed One'' bit (0x00008000).
1234
 
1235
@item superscalar = 0|1
1236
@cindex @code{superscalar} (CPU configuration)
1237 82 jeremybenn
If 1, the processor operates in superscalar mode.  Default value is
1238 19 jeremybenn
0.
1239
 
1240
In the current simulator, the only functional effect of superscalar
1241
mode is to affect the calculation of the number of cycles taken to
1242
execute an instruction.
1243
 
1244
@quotation Caution
1245
The code for this does not appear to be complete or well tested, so
1246
users are advised not to use this option.
1247
@end quotation
1248
 
1249
@item hazards = 0|1
1250
@cindex @code{hazards} (CPU configuration)
1251 82 jeremybenn
If 1, data hazards are tracked in a superscalar CPU.  Default value is
1252 19 jeremybenn
0.
1253
 
1254
In the current simulator, the only functional effect is to cause
1255
logging of hazard waiting information if the CPU is
1256 82 jeremybenn
superscalar.  However nowhere in the simulator is this data actually
1257 19 jeremybenn
computed, so the net result is probably to have no effect.
1258
 
1259
if harzards are tracked, current hazards can be displayed using the
1260
simulator's @command{r} command.
1261
 
1262
@quotation Caution
1263
The code for this does not appear to be complete or well tested, so
1264
users are advised not to use this option.
1265
@end quotation
1266
 
1267
@item dependstats = 0|1
1268
@cindex @code{dependstats} (CPU configuration)
1269 82 jeremybenn
If 1, inter-instruction dependencies are calculated.  Default value 0.
1270 19 jeremybenn
 
1271
If these values are calculated, the depencies can be displayed using
1272
the simulator's @command{stat} command.
1273
 
1274
@quotation Note
1275
This field must be enabled, if execution execution flow tracking
1276
(field @code{history}) has been requested in the simulator
1277
configuration section (@pxref{Simulator Behavior, , Simulator
1278
Behavior}).
1279
@end quotation
1280
 
1281
@item sbuf_len = @var{value}
1282
@cindex @code{sbuf_len} (CPU configuration)
1283
The length of the store buffer is set to @var{value}, which must be no
1284 82 jeremybenn
greater than 256.  Larger values will be truncated to 256 with a
1285
warning.  Negative values will be treated as 0 with a warning.  Use 0 to
1286 19 jeremybenn
disable the store buffer.
1287
 
1288
When the store buffer is active, stores are accumulated and committed
1289
when I/O is idle.
1290
 
1291
@end table
1292
 
1293
@node Memory Configuration
1294
@subsection Memory Configuration
1295
@cindex configuring memory
1296
@cindex memory configuration
1297
@cindex @code{section memory}
1298 82 jeremybenn
Memory configuration is described in @code{section memory}.  This
1299 19 jeremybenn
section may appear multiple times, specifying multiple blocks of
1300 82 jeremybenn
memory.  The following parameters may be specified.
1301 19 jeremybenn
 
1302
@table @code
1303
 
1304
@item type=random|pattern|unknown|zero
1305
@cindex @code{type} (memory configuration)
1306 82 jeremybenn
Specifies the values to which memory should be initialized.  The
1307 19 jeremybenn
default value is @code{unknown}.
1308
 
1309
@table @code
1310
 
1311
@item random
1312
@cindex @code{type=random} (memory configuration)
1313 82 jeremybenn
Set the memory values to be a random value.  A seed for the random
1314 19 jeremybenn
generator may be set using the @code{random_seed} field in this
1315
section (see below), thus ensuring the same ``random'' values are used
1316
each time.
1317
 
1318
@item pattern
1319
@cindex @code{type=pattern} (memory configuration)
1320
Set the memory values to be a pattern value, which is set using the
1321
@code{pattern} field in this section (see below).
1322
 
1323
@item unknown
1324
@cindex @code{type=unknown} (memory configuration)
1325 82 jeremybenn
The memory values are not initialized (i.e.  left ``unknown'').  This
1326 19 jeremybenn
option will yield faster initialization of the simulator.
1327
 
1328
@item zero
1329
@cindex @code{type=zero} (memory configuration)
1330 82 jeremybenn
Set the memory values to be 0.  This is the equivalent of
1331 19 jeremybenn
@code{type=pattern} and a @code{pattern} value of 0, and implemented
1332
as such.
1333
 
1334
@quotation Note
1335
As a consequence, if the @code{pattern} field is @emph{subsequently}
1336
specified in this section, the value in that field will be used
1337
instead of zero to initialize the memory.
1338
@end quotation
1339
 
1340
@end table
1341
 
1342
@item random_seed = @var{value}
1343
@cindex @code{random_seed} (memory configuration)
1344 82 jeremybenn
Set the seed for the random number generator to @var{value}.  This only
1345 19 jeremybenn
has any effect for memory type @code{random}.
1346
 
1347
The default value is -1,
1348
which means the seed will be set from a call to the @code{time}
1349
function, thus ensuring different random values are used on each
1350 82 jeremybenn
run.  The simulator prints out the seed used in this case, allowing
1351 19 jeremybenn
repeat runs to regenerate the same random values used in any
1352
particular run.
1353
 
1354
@item pattern = @var{value}
1355
@cindex @code{pattern} (memory configuration)
1356
Set the pattern to be used when initializing memory to
1357 82 jeremybenn
@var{value}.  The default value is 0.  This only has any effect for
1358
memory type @code{pattern}.  The least significant 8 bits of this value
1359
is used to initialize each byte.  More than 8 bits can be specified,
1360 19 jeremybenn
but will ignored with a warning.
1361
 
1362
@quotation Tip
1363
The default value, is equivalent to setting the memory @code{type} to
1364 82 jeremybenn
be @code{zero}.  If that is what is intended, then using
1365 19 jeremybenn
@code{type=zero} explicitly is better than using @code{type=pattern}
1366
and not specifying a value for @code{pattern}.
1367
@end quotation
1368
 
1369
@item baseaddr = @var{value}
1370
@cindex @code{baseaddr} (memory configuration)
1371 82 jeremybenn
Set the base address of the memory to @var{value}.  It should be
1372 19 jeremybenn
aligned to a multiple of the memory size rounded up to the nearest
1373 82 jeremybenn
@math{2^n}.  The default value is 0.
1374 19 jeremybenn
 
1375
@item size = @var{value}
1376
@cindex @code{size} (memory configuration)
1377 82 jeremybenn
Set the size of the memory block to be @var{value} bytes.  This should be a
1378
multiple of 4 (i.e.  word aligned).  The default value is 1024.
1379 19 jeremybenn
 
1380
@quotation Note
1381
When allocating memory, the simulator will allocate the nearest
1382
@math{2^n} bytes greater than or equal to @var{value}, and will not
1383
notice memory misses in any part of the memory between @var{value} and
1384
the amount allocated.
1385
 
1386
As a consequence users are strongly recommended to specify memory
1387 82 jeremybenn
sizes that are an exact power of 2.  If some other amount of memory is
1388 19 jeremybenn
required, it should be specified as separate, contiguous blocks, each
1389
of which is a power of 2 in size.
1390
@end quotation
1391
 
1392
@item name = "@var{text}"
1393
@cindex @code{name} (memory configuration)
1394 82 jeremybenn
Name the block.  Typically these describe the type of memory being
1395
modeled (thus @code{"SRAM"} or @code{"Flash"}.  The default is
1396 19 jeremybenn
@code{@w{"anonymous memory block"}}.
1397
 
1398
@quotation Note
1399
It is not clear that this information is currently ever used in normal
1400 82 jeremybenn
operation of the simulator.  Even the @command{info} command of the simulator
1401 19 jeremybenn
ignores it.
1402
@end quotation
1403
 
1404
@item ce = @var{value}
1405
@cindex @code{ce} (memory configuration)
1406 82 jeremybenn
Set the chip enable index of the memory instance.  Each memory instance
1407 19 jeremybenn
should have a unique chip enable index, which should be greater
1408 82 jeremybenn
than or equal to zero.  This is used by the memory controller when
1409 19 jeremybenn
identifying different memory instances.
1410
 
1411
The default value is -1 (invalid).
1412
 
1413
@item mc = @var{value}
1414
@cindex @code{mc} (memory configuration)
1415 82 jeremybenn
Specifies the memory controller this memory is connected to.  It should
1416 19 jeremybenn
correspond to the @code{index} field specified in a @code{@w{section
1417
mc}} for a memory controller (@pxref{Memory Controller Configuration,
1418
, Memory Controller Configuration}).
1419
 
1420
Default value is 0, which is also the default value of a memory
1421 82 jeremybenn
controller @code{index} field.  This is suitable therefore for designs
1422 19 jeremybenn
with just one memory controller.
1423
 
1424
@item delayr = @var{value}
1425
@cindex @code{delayr} (memory configuration)
1426 82 jeremybenn
The number of cycles required for a read access.  Set to -1 if the
1427
memory does not support reading.  Default value 1.  The simulator will
1428 19 jeremybenn
add this number of cycles to the total instruction cycle count when
1429
reading from main memory.
1430
 
1431
@item delayw = @var{value}
1432
@cindex @code{delayw} (memory configuration)
1433 82 jeremybenn
The number of cycles required for a write access.  Set to -1 if the
1434
memory does not support writing.  Default value 1.  The simulator will
1435 19 jeremybenn
add this number of cycles to the total instruction cycle count when
1436
writing to main memory.
1437
 
1438
@item log = "@var{file}"
1439
@cindex @code{log} (memory configuration)
1440
If specified, @file{file} names a file for all memory accesses to be
1441 82 jeremybenn
logged.  If not specified, the default value, NULL is used, meaning
1442 19 jeremybenn
that the memory is not logged.
1443
 
1444
@end table
1445
 
1446
@node Memory Management Configuration
1447
@subsection Memory Management Configuration
1448
@cindex configuring data & instruction MMUs
1449
@cindex MMU configuration
1450
@cindex DMMU configuration
1451
@cindex data MMU configuration
1452
@cindex IMMU configuration
1453
@cindex instruction MMU configuration
1454
@cindex @code{section dmmu}
1455
@cindex @code{section immu}
1456
Memory Management Unit (MMU) configuration is described in
1457
@code{section dmmu} (for the data MMU) and @code{section immu} (for
1458 82 jeremybenn
the instruction MMU).  Each section should appear at most once.  The
1459 19 jeremybenn
following parameters may be specified.
1460
 
1461
@table @code
1462
 
1463
@item enabled = 0|1
1464
@cindex @code{enabled} (MMU configuration)
1465
If 1 (true), the data or instruction (as appropriate) MMU is
1466 82 jeremybenn
enabled.  If 0 (the default), it is disabled.
1467 19 jeremybenn
 
1468
@item nsets = @var{value}
1469
@cindex @code{nsets} (MMU configuration)
1470
Sets the number of data or instruction (as appropriate) TLB sets to
1471 82 jeremybenn
@var{value}, which must be a power of two, not exceeding 128.  Values
1472
which do not fit these criteria are ignored with a warning.  The
1473
default value is 1.
1474 19 jeremybenn
 
1475
@item nways = @var{value}
1476
@cindex @code{nways} (MMU configuration)
1477
Sets the number of data or instruction (as appropriate) TLB ways to
1478 82 jeremybenn
@var{value}.  The value must be in the range 1 to 4.  Values outside
1479
this range are ignored with a warning.  The default value is 1.
1480 19 jeremybenn
 
1481
@item pagesize = @var{value}
1482
@cindex @code{pagesize} (MMU configuration)
1483
The data or instruction (as appropriate) MMU page size is set to
1484 82 jeremybenn
@var{value}, which must be a power of 2.  Values which are not a power
1485
of 2 are ignored with a warning.  The default is 8192 (0x2000).
1486 19 jeremybenn
 
1487
@item entrysize = @var{value}
1488
@cindex @code{entrysize} (MMU configuration)
1489
The data or instruction (as appropriate) MMU entry size is set to
1490 82 jeremybenn
@var{value}, which must be a power of 2.  Values which are not a power
1491
of 2 are ignored with a warning.  The default value is 1.
1492 19 jeremybenn
 
1493
@quotation Note
1494
@value{OR1KSIM} does not appear to use the @code{entrysize} parameter
1495 82 jeremybenn
in its simulation of the MMUs.  Thus setting this value does not seem
1496 19 jeremybenn
to matter.
1497
@end quotation
1498
 
1499
@item ustates = @var{value}
1500
@cindex @code{ustates} (MMU configuration)
1501
The number of instruction usage states for the data or instruction (as
1502
appropriate) MMU is set to @var{value}, which must be 2, 3 or
1503 82 jeremybenn
4.  Values outside this range are ignored with a warning.  The default
1504 19 jeremybenn
value is 2.
1505
 
1506
@quotation Note
1507
@value{OR1KSIM} does not appear to use the @code{ustates} parameter in
1508 82 jeremybenn
its simulation of the MMUs.  Thus setting this value does not seem to
1509 19 jeremybenn
matter.
1510
@end quotation
1511
 
1512
@item hitdelay = @var{value}
1513
@cindex @code{hitdelay} (MMU configuration)
1514
Set the number of cycles a data or instruction (as appropriate) MMU
1515 82 jeremybenn
hit costs.  Default value 1.
1516 19 jeremybenn
 
1517
@item missdelay = @var{value}
1518
@cindex @code{missdelay} (MMU configuration)
1519
Set the number of cycles a data or instruction (as appropriate) MMU
1520 82 jeremybenn
miss costs.  Default value 1.
1521 19 jeremybenn
 
1522
@end table
1523
 
1524
@node Cache Configuration
1525
@subsection Cache Configuration
1526
@cindex configuring data & instruction caches
1527
@cindex cache configuration
1528
@cindex data cache configuration
1529
@cindex instruction cache configuration
1530
@cindex @code{section dc}
1531
@cindex @code{section ic}
1532
Cache configuration is described in @code{section dc} (for the data
1533 82 jeremybenn
cache) and @code{seciton ic} (for the instruction cache).  Each section
1534
should appear at most once.  The following parameters may be specified.
1535 19 jeremybenn
 
1536
@table @code
1537
 
1538
@item enabled = 0|1
1539
@cindex @code{enabled} (cache configuration)
1540
If 1 (true), the data or instruction (as appropriate) cache is
1541 82 jeremybenn
enabled.  If 0 (the default), it is disabled.
1542 19 jeremybenn
 
1543
@item nsets = @var{value}
1544
@cindex @code{nsets} (cache configuration)
1545
Sets the number of data or instruction (as appropriate) cache sets to
1546
@var{value}, which must be a power of two, not exceeding
1547
@code{MAX_DC_SETS} (for the data cache) or @code{MAX_IC_SETS} (for the
1548 82 jeremybenn
instruction cache).  At the time of writing, these constants are
1549
both defined in the code to be 1024).  The default value is 1.
1550 19 jeremybenn
 
1551
@item nways = @var{value}
1552
@cindex @code{nways} (cache configuration)
1553
Sets the number of data or instruction (as appropriate) cache ways to
1554
@var{value}, which must be a power of two, not exceeding
1555
@code{MAX_DC_WAYS} (for the data cache) or @code{MAX_IC_WAYS} (for the
1556 82 jeremybenn
instruction cache).  At the time of writing, these constants are both
1557
defined in the code to be 32).  The default value is 1.
1558 19 jeremybenn
 
1559
@item blocksize = @var{value}
1560
@cindex @code{blocksize} (cache configuration)
1561
The data or instruction (as appropriate) cache block size is set to
1562 82 jeremybenn
@var{value} bytes, which must be either 16 or 32.  The default is 16.
1563 19 jeremybenn
 
1564
@item ustates = @var{value}
1565
@cindex @code{ustates} (cache configuration)
1566
The number of instruction usage states for the data or instruction (as
1567 82 jeremybenn
appropriate) cache is set to @var{value}, which must be 2, 3 or 4.  The
1568 19 jeremybenn
default value is 2.
1569
 
1570
@item hitdelay = @var{value}
1571
@cindex @code{hitdelay} (instruction cache configuration)
1572 82 jeremybenn
@emph{Instruction cache only}.  Set the number of cycles an instruction
1573
cache hit costs.  Default value 1.
1574 19 jeremybenn
 
1575
@item missdelay = @var{value}
1576
@cindex @code{missdelay} (instruction cache configuration)
1577 82 jeremybenn
@emph{Instruction cache only}.  Set the number of cycles an instruction
1578
cache miss costs.  Default value 1.
1579 19 jeremybenn
 
1580
@item load_hitdelay = @var{value}
1581
@cindex @code{load_hitdelay} (data cache configuration)
1582 82 jeremybenn
@emph{Data cache only}.  Set the number of cycles a data load cache hit
1583
costs.  Default value 2.
1584 19 jeremybenn
 
1585
@item load_missdelay = @var{value}
1586
@cindex @code{load_missdelay} (data cache configuration)
1587 82 jeremybenn
@emph{Data cache only}.  Set the number of cycles a data load cache
1588
miss costs.  Default value 2.
1589 19 jeremybenn
 
1590
@item store_hitdelay = @var{value}
1591
@cindex @code{store_hitdelay} (data cache configuration)
1592 82 jeremybenn
@emph{Data cache only}.  Set the number of cycles a data store cache hit
1593
costs.  Default value 0.
1594 19 jeremybenn
 
1595
@item store_missdelay = @var{value}
1596
@cindex @code{store_missdelay} (data cache configuration)
1597 82 jeremybenn
@emph{Data cache only}.  Set the number of cycles a data store cache
1598
miss costs.  Default value 0.
1599 19 jeremybenn
 
1600
@end table
1601
 
1602
@node Interrupt Configuration
1603
@subsection Interrupt Configuration
1604
@cindex configuring the interrupt controller
1605
@cindex interrupt controller configuration
1606
@cindex programmable interrupt controller configuration
1607
@cindex PIC configuration
1608
@cindex @code{section pic}
1609
Programmable Interrupt Controller (PIC) configuration is described in
1610 82 jeremybenn
@code{section pic}.  This section may appear at most
1611 19 jeremybenn
once---@value{OR1KSIM} has no mechanism for handling multiple
1612 82 jeremybenn
interrupt controllers.  The following parameters may be specified.
1613 19 jeremybenn
 
1614
@table @code
1615
 
1616
@item enabled = 0|1
1617
@cindex @code{enabled} (interrupt controller)
1618 82 jeremybenn
If 1 (true), the programmable interrupt controller is enabled.  If 0
1619 19 jeremybenn
(the default), it is disabled.
1620
 
1621
@item edge_trigger = 0|1
1622
@cindex @code{edge_trigger} (interrupt controller)
1623
If 1 (true, the default), the programmable interrupt controller is
1624 82 jeremybenn
edge triggered.  If 0 (false), it is level triggered.
1625 19 jeremybenn
 
1626
@end table
1627
 
1628
@node Power Management Configuration
1629
@subsection Power Management Configuration
1630
@cindex configuring power management
1631
@cindex power management configuration
1632
@cindex PMU configuration
1633
@cindex @code{section pmu}
1634 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1635 19 jeremybenn
(which only happens when the power management unit is enabled) of
1636
setting the different bits in the power management Special Purpose
1637
Register (PMR, SPR 0x4000) is
1638
 
1639
@table @code
1640
 
1641
@item SDF (bit mask 0x0000000f)
1642
@cindex SDF (power management register)
1643
@cindex slow down factor (power management register)
1644
@cindex power management register, SDF
1645
@cindex PMR - SDF
1646
No effect - these bits are ignored
1647
 
1648
@item DME (bit mask 0x00000010)
1649
@cindex DME (power management register)
1650
@cindex doze mode (power management register)
1651
@cindex power management register, DME
1652
@cindex PMR - DME
1653
@itemx SME (bit mask 0x00000020)
1654
@cindex SME (power management register)
1655
@cindex sleep mode (power management register)
1656
@cindex power management register, SME
1657
@cindex PMR - SME
1658
Both these bits cause the processor to stop executing
1659 82 jeremybenn
instructions.  However all other functions (debug interaction, CLI,
1660 19 jeremybenn
VAPI etc) carry on as normal.
1661
 
1662
@item DCGE (bit mask 0x00000004)
1663
@cindex DCGE (power management register)
1664
@cindex dynamic clock gating (power management register)
1665
@cindex power management register, DGCE
1666
@cindex PMR - DGCE
1667
No effect - this bit is ignored
1668
 
1669
@item SUME (bit mask 0x00000008)
1670
@cindex SUME (power management register)
1671
@cindex suspend mode (power management register)
1672
@cindex power management register, SUME
1673
@cindex PMR - SUME
1674
Enabling this bit causes a message to be printed, advising that the
1675
processor is suspending and the simulator exits.
1676
 
1677
@end table
1678
 
1679
On reset all bits are cleared.
1680
 
1681 82 jeremybenn
Power management configuration is described in @code{section pm}.  This
1682
section may appear at most once.  The following parameter may be specified.
1683 19 jeremybenn
 
1684
@table @code
1685
 
1686
@item enabled = 0|1
1687
@cindex @code{enabled} (power management configuration)
1688 82 jeremybenn
If 1 (true), power management is enabled.  If 0 (the default), it is
1689 19 jeremybenn
disabled.
1690
 
1691
@end table
1692
 
1693
@node Branch Prediction Configuration
1694
@subsection Branch Prediction Configuration
1695
@cindex configuring branch prediction
1696
@cindex branch prediction configuration
1697
@cindex BPB configuration
1698
@cindex @code{section bpb}
1699
From examining the code base, it seems the branch prediction function
1700 82 jeremybenn
is not fully implemented.  At present the functionality seems
1701 19 jeremybenn
restricted to collection of statistics.
1702
 
1703 82 jeremybenn
Branch prediction configuration is described in @code{section bpb}.  This
1704
section may appear at most once.  The following parameters may be specified.
1705 19 jeremybenn
 
1706
@table @code
1707
 
1708
@item enabled = 0|1
1709
@cindex @code{enabled} (branch prediction configuration)
1710 82 jeremybenn
If 1 (true), branch prediction is enabled.  If 0 (the default), it is
1711 19 jeremybenn
disabled.
1712
 
1713
@item btic = 0|1
1714
@cindex @code{btic} (branch prediction configuration)
1715 82 jeremybenn
If 1 (true), the branch target instruction cache model is enabled.  If
1716 19 jeremybenn
 
1717
 
1718
@item sbp_bf_fwd = 0|1
1719
@cindex @code{sbp_bf_fwd} (branch prediction configuration)
1720 82 jeremybenn
If 1 (true), use forward prediction for the @code{l.bf} instruction.  If
1721 19 jeremybenn
 
1722
 
1723
@item sbp_bnf_fwd = 0|1
1724
@cindex @code{sbp_bnf_fwd} (branch prediction configuration)
1725 82 jeremybenn
If 1 (true), use forward prediction for the @code{l.bnf} instruction.  If
1726 19 jeremybenn
 
1727
 
1728
@item hitdelay = @var{value}
1729
@cindex @code{hitdelay} (branch prediction configuration)
1730 82 jeremybenn
Set the number of cycles a branch prediction hit costs.  Default value
1731 19 jeremybenn
0.
1732
 
1733
@item missdelay = @var{value}
1734
@cindex @code{missdelay} (branch prediction configuration)
1735 82 jeremybenn
Set the number of cycles a branch prediction miss costs.  Default value
1736 19 jeremybenn
0.
1737
 
1738
@end table
1739
 
1740
@node Debug Interface Configuration
1741
@subsection Debug Interface Configuration
1742
@cindex configuring the debug unit and interface to external debuggers
1743
@cindex debug unit configuration
1744
@cindex debug interface configuration
1745
@cindex @code{section debug}
1746
The debug unit and debug interface configuration is described in
1747 82 jeremybenn
@code{@w{section debug}}.  This section may appear at most once.  The
1748 19 jeremybenn
following parameters may be specified.
1749
 
1750
@table @code
1751
 
1752
@item enabled = 0|1
1753
@cindex @code{enabled} (debug interface configuration)
1754 82 jeremybenn
If 1 (true), the debug unit is enabled.  If 0 (the default), it is disabled.
1755 19 jeremybenn
 
1756
@quotation Note
1757
This enables the functionality of the debug unit (its registers etc) within
1758 82 jeremybenn
the mode.  It does not provide any external interface to the debug unit.
1759
For
1760 19 jeremybenn
that, see @code{gdb_enabled} and @code{rsp_enabled} below.
1761
@end quotation
1762
 
1763
@item rsp_enabled = 0|1
1764
@cindex @code{rsp_enabled} (debug interface configuration)
1765
@cindex Remote Serial Protocol
1766
If 1 (true), the GDB @dfn{Remote Serial Protocol} server is started, provding
1767
an interface to an external GNU debugger, using the port specified in the
1768
@code{rsp_port} field (see below), or the @code{or1ksim-rsp} TCP/IP
1769 82 jeremybenn
service.  If 0 (the default), the server is not started, and no external
1770 19 jeremybenn
interface is provided.
1771
 
1772
For more detailed information on the interface to the GNU Debugger see
1773
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger Practical
1774
Experience with the OpenRISC 1000 Architecture}, by Jeremy Bennett, published
1775
by Embecosm Limited (@url{www.embecosm.com}).
1776
 
1777
@quotation Note
1778 82 jeremybenn
@code{rsp_enabled} may not be enabled with @code{gdb_enabled} (see
1779
below).  If
1780 19 jeremybenn
both are enabled, a warning is issued and only the @dfn{Remote Serial
1781
Protocol} interface is enabled.
1782
@end quotation
1783
 
1784
@item rsp_port = @var{value}
1785
@cindex @code{rsp_port} (debug interface configuration)
1786
@var{value} specifies the port to be used for the GDB @dfn{Remote Serial
1787 82 jeremybenn
Protocol} interface to the GNU Debugger (GDB).  Default value 51000.  If
1788 19 jeremybenn
the value 0 is specified, @value{OR1KSIM} will instead look for a TCP/IP
1789
service named @code{or1ksim-rsp}.
1790
 
1791
@quotation Tip
1792
@cindex TCP/IP port range for @code{or1ksim-rsp} service
1793
There is no registered port for @value{OR1KSIM} @dfn{Remote Serial Protocol}
1794 82 jeremybenn
service @code{or1ksim-rsp}.  Good practice suggests users should adopt port
1795
values in the @dfn{Dynamic} or @dfn{Private} port range, i.e.  49152-65535.
1796 19 jeremybenn
@end quotation
1797
 
1798
@item gdb_enabled = 0|1
1799
@cindex @code{gdb_enabled} (debug interface configuration)
1800
If 1 (true), the OpenRISC Remote JTAG protocol server is started, provding an
1801
interface to an external GNU debugger, using the port specified in the
1802 82 jeremybenn
@code{server_port} field (see below), or the @code{or1ksim} TCP/IP
1803
service.  If
1804 19 jeremybenn
 
1805
provided.
1806
 
1807
For more detailed information on the interface to the GNU Debugger see
1808
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger Practical
1809
Experience with the OpenRISC 1000 Architecture}, by Jeremy Bennett, published
1810
by Embecosm Limited (@url{www.embecosm.com}).
1811
 
1812
@quotation Note
1813
The OpenRISC Remote JTAG protocol is unique to OpenRISC, and remains only for
1814 82 jeremybenn
backward compatibility.  New users should adopt the standard GDB @dfn{Remote
1815 19 jeremybenn
Serial Protocol} interface (see @code{rsp_enabled} above) providing access to
1816
a wider range of GDB functionality.
1817
@end quotation
1818
 
1819
@quotation Note
1820 82 jeremybenn
@code{gdb_enabled} may not be enabled with @code{rsp_enabled}.  If both are
1821 19 jeremybenn
enabled, a warning is issued and only the @dfn{Remote Serial Protocol}
1822
interface is enabled.
1823
@end quotation
1824
 
1825
@item server_port = @var{value}
1826
@cindex @code{server_port} (debug interface configuration)
1827
@var{value} specifies the port to be used for the OpenRISC Rmote JTAG
1828 82 jeremybenn
protocol interface to the GNU Debugger (GDB).  Default value 51000.  If
1829 19 jeremybenn
the value 0 is specified, @value{OR1KSIM} will instead look for a TCP/IP
1830
service named @code{or1ksim}.
1831
 
1832
@quotation Tip
1833
@cindex TCP/IP port range for @code{or1ksim} service
1834
There is no registered port for @value{OR1KSIM} Remote JTAG Interface
1835 82 jeremybenn
or service @code{or1ksim}.  Good practice suggests users should adopt
1836 19 jeremybenn
port values in the @dfn{Dynamic} or @dfn{Private} port range,
1837 82 jeremybenn
i.e.  49152-65535.
1838 19 jeremybenn
@end quotation
1839
 
1840
@item vapi_id = @var{value}
1841
@cindex @code{vapi_id} (debug interface configuration)
1842
@var{value} specifies the value of the Verification API (VAPI) base
1843 82 jeremybenn
address to be used with the debug unit.  @xref{Verification API, ,
1844 19 jeremybenn
Verification API}, for more details.
1845
 
1846
If this is specified and @var{value} is non-zero, all OpenRISC Remote
1847
JTAG protocol transactions will be logged to the VAPI log file, if
1848 82 jeremybenn
enabled.  This is the only functionality associated with VAPI for the
1849
debug unit.  No VAPI commands are sent, nor requests handled.
1850 19 jeremybenn
 
1851
@end table
1852
 
1853
@node Peripheral Configuration
1854
@section Configuring Memory Mapped Peripherals
1855
 
1856 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1857 19 jeremybenn
(unlike other components) by default they are enabled.
1858
 
1859
@menu
1860
* Memory Controller Configuration::
1861
* UART Configuration::
1862
* DMA Configuration::
1863
* Ethernet Configuration::
1864
* GPIO Configuration::
1865
* Display Interface Configuration::
1866
* Frame Buffer Configuration::
1867
* Keyboard Configuration::
1868
* Disc Interface Configuration::
1869
* Generic Peripheral Configuration::
1870
@end menu
1871
 
1872
@node Memory Controller Configuration
1873
@subsection Memory Controller Configuration
1874
@cindex configuring the memory controller
1875
@cindex memory controller configuration
1876
@cindex @code{section mc}
1877
The memory controller used in @value{OR1KSIM} is the component
1878
implemented at OpenCores, and found in the top level CVS directory,
1879 82 jeremybenn
@file{mem_ctrl}.  It is described in the document @cite{Memory
1880 19 jeremybenn
Controller IP Core} by Rudolf Usselmann, which can be found in the
1881 82 jeremybenn
@file{doc} subdirectory.  It is a memory mapped component, which
1882 19 jeremybenn
resides on the main OpenRISC Wishbone data bus.
1883
 
1884
The memory controller configuration is described in @code{@w{section
1885 82 jeremybenn
mc}}.  This section may appear multiple times, specifying multiple
1886
memory controllers.  The following parameters may be specified.
1887 19 jeremybenn
 
1888
@table @code
1889
 
1890
@item enabled = 0|1
1891
@cindex @code{enabled} (memory controller configuration)
1892 82 jeremybenn
If 1 (true, the default), this memory controller is enabled.  If 0, it is
1893 19 jeremybenn
disabled.
1894
 
1895
@quotation Note
1896
The memory controller can effectively also be disabled by setting an
1897 82 jeremybenn
appropriate power on control register value (see below).  However this
1898 19 jeremybenn
should only be used if it is desired to specifically model this
1899
behavior of the memory controller, not as a way of disabling the
1900
memory controller in general.
1901
@end quotation
1902
 
1903
@item baseaddr = @var{value}
1904
@cindex @code{baseaddr} (memory controller configuration)
1905
Set the base address of the memory controller's memory mapped
1906 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
1907 19 jeremybenn
sensible value.
1908
 
1909
The memory controller has a 7 bit address bus, with a total of 19
1910
32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1911
addresses 0x50 through 0x7c are not used).
1912
 
1913
@item poc = @var{value}
1914
@cindex @code{poc} (memory controller configuration)
1915
Specifies the value of the power on control register, The least
1916
signficant two bits specify the bus width (use 0 for an 8-bit bus, 1
1917
for a 16-bit bus and 2 for a 32-bit bus) and the next two bits the
1918
type of memory connected (use 0 for a disabled interface, 1 for SSRAM,
1919
2 for asyncrhonous devices and 3 for synchronous devices).
1920
 
1921
If other bits are specified, they are ignored with a warning.
1922
 
1923
@quotation Caution
1924
The default value, 0, corresponds to a disabled 8-bit bus, and
1925
is likely not the most suitable value
1926
@end quotation
1927
 
1928
@item index = @var{value}
1929
@cindex @code{index} (memory controller configuration)
1930
Specify the index of this memory controller amongst all the memory
1931 82 jeremybenn
controllers.  This value should be unique for each memory controller,
1932 19 jeremybenn
and is used to associate specific memories with the controller,
1933
through the @code{mc} field in the @code{@w{section memory}}
1934
configuration (@pxref{Memory Configuration, , Memory Configuration}).
1935
 
1936
The default value, 0, is suitable when there is only one memory controller.
1937
 
1938
@end table
1939
 
1940
@node UART Configuration
1941
@subsection UART Configuration
1942
@cindex configuring the UART
1943
@cindex UART configuration
1944
@cindex @code{section uart}
1945
The UART implemented in @value{OR1KSIM} follows the specification of the
1946 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1947 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1948
 
1949
The component provides a number of interfaces to emulate the behavior
1950
of an external terminal connected to the UART.
1951
 
1952 82 jeremybenn
UART configuration is described in @code{section uart}.  This section
1953
may appear multiple times, specifying multiple UARTs.  The following
1954 19 jeremybenn
parameters may be specified.
1955
 
1956
@table @code
1957
 
1958
@item enabled = 0|1
1959
@cindex @code{enabled} (UART configuration)
1960 82 jeremybenn
If 1 (true, the default), this UART is enabled.  If 0, it is disabled.
1961 19 jeremybenn
 
1962
@item baseaddr = @var{value}
1963
@cindex @code{baseaddr} (UART configuration)
1964
Set the base address of the UART's memory mapped
1965 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
1966 19 jeremybenn
sensible value.
1967
 
1968
The UART has a 3 bit address bus, with a total of 8 8-bit registers,
1969
at addresses 0x0 through 0x7.
1970
 
1971
@item channel = "@var{type}:@var{args}"
1972
@cindex @code{channel} (UART configuration)
1973
Specify the channel representing the terminal connected to the UART
1974
Rx & Tx pins.
1975
 
1976
@table @code
1977
 
1978
@item channel="file:@file{rxfile},@file{txfile}"
1979
@cindex UART I/O from/to files
1980
Read input characters from the file @file{rxfile} and write output
1981
characters to the file @file{txfile} (which will be created if
1982
required).
1983
 
1984
@item channel="xterm:@var{args}"
1985
@cindex UART I/O from/to an @command{xterm}
1986
Create an xterm on startup, write UART Tx traffic to the xterm and
1987
take Rx traffic from the keyboard when the xterm window is
1988 82 jeremybenn
selected.  Additional arguments to the xterm command (for example
1989 19 jeremybenn
specifying window size may be specified in @var{args}, or this may be
1990
left blank.
1991
 
1992
@item channel="tcp:@var{value}"
1993
@cindex UART I/O from/to TCP/IP
1994
Open the TCP/IP port specified by @var{value} and read and write UART
1995
traffic from and to it.
1996
 
1997
Typically a telnet session is connected to the other end of this port.
1998
 
1999
@quotation Tip
2000
There is no registered port for @value{OR1KSIM} telnet UART
2001 82 jeremybenn
connection.  Priviledged access is required to read traffic on the
2002
registered ``well-known'' telnet port (23).  Instead users should use
2003 19 jeremybenn
port values in the @dfn{Dynamic} or @dfn{Private} port range,
2004 82 jeremybenn
i.e.  49152-65535.
2005 19 jeremybenn
@end quotation
2006
 
2007
@item channel="fd:@code{rxfd},@code{txfd}"
2008
@cindex UART I/O from/to open file descriptors
2009
Read and write characters from and to the existing open numerical file
2010
descriptors, file @code{rxfd} and @code{txfd}.
2011
 
2012
@item channel="tty:device=/dev/ttyS0,baud=9600"
2013
@cindex UART I/O from/to a physical serial port
2014 82 jeremybenn
Read and write characters from and to a physical serial port.  The
2015 19 jeremybenn
precise device (shown here as @code{/dev/ttyS0}) may vary from machine
2016
to machine.
2017
 
2018
@end table
2019
 
2020
The default value for this field is @code{"xterm:"}.
2021
 
2022
@item irq = @var{value}
2023
@cindex @code{irq} (UART configuration)
2024 82 jeremybenn
Use @var{value} as the IRQ number of this UART.  Default value 0.
2025 19 jeremybenn
 
2026
@item 16550 = 0|1
2027
@cindex @code{16550} (UART configuration)
2028 82 jeremybenn
If 1 (true), the UART has the functionality of a 16550.  If 0 (the
2029
default), it has the functionality of a 16450.  The principal
2030 19 jeremybenn
difference is that the 16550 can buffer multiple characters.
2031
 
2032
@item jitter = @var{value}
2033
@cindex @code{jitter} (UART configuration)
2034
Set the jitter, modeled as a time to block, to @var{value}
2035 82 jeremybenn
milliseconds.  Set to -1 to disable jitter modeling.  Default value 0.
2036 19 jeremybenn
 
2037
@quotation Note
2038
This functionality has yet to be implemented, so this parameter has no
2039
effect.
2040
@end quotation
2041
 
2042
@item vapi_id = @var{value}
2043
@cindex @code{vapi_id} (UART configuration)
2044
@var{value} specifies the value of the Verification API (VAPI) base
2045 82 jeremybenn
address to be used with the UART.  @xref{Verification API, ,
2046 19 jeremybenn
Verification API}, for more details, which details the use of the VAPI
2047
with the UART.
2048
 
2049
@end table
2050
 
2051
@node DMA Configuration
2052
@subsection DMA Configuration
2053
@cindex configuring DMA
2054
@cindex DMA configuration
2055
@cindex @code{section dma}
2056
The DMA controller used in @value{OR1KSIM} is the component
2057
implemented at OpenCores, and found in the top level CVS directory,
2058 82 jeremybenn
@file{wb_dma}.  It is described in the document @cite{Wishbone
2059 19 jeremybenn
DMA/Bridge IP Core} by Rudolf Usselmann, which can be found in the
2060 82 jeremybenn
@file{doc} subdirectory.  It is a memory mapped component, which
2061
resides on the main OpenRISC Wishbone data bus.  The present
2062 19 jeremybenn
implementation is incomplete, intended only to support the Ethernet
2063
interface (@pxref{Ethernet Configuration}), although the Ethernet
2064
interface is not yet completed.
2065
 
2066 82 jeremybenn
DMA configuration is described in @code{@w{section dma}}.  This section
2067
may appear multiple times, specifying multiple DMA controllers.  The
2068 19 jeremybenn
following parameters may be specified.
2069
 
2070
@table @code
2071
 
2072
@item enabled = 0|1
2073
@cindex @code{enabled} (DMA configuration)
2074 82 jeremybenn
If 1 (true, the default), this DMA controller is enabled.  If 0, it is disabled.
2075 19 jeremybenn
 
2076
@item baseaddr = @var{value}
2077
@cindex @code{baseaddr} (DMA configuration)
2078
Set the base address of the DMA's memory mapped
2079 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
2080 19 jeremybenn
sensible value.
2081
 
2082
The DMA controller has a 10 bit address bus, with a total of 253
2083 82 jeremybenn
32-bit registers.  The first 5 registers at addresses 0x000 through
2084
0x010 control the overall behavior of the DMA controller.  There are
2085 19 jeremybenn
then 31 blocks of 8 registers, controlling each of the 31 DMA channels
2086 82 jeremybenn
available.  Addresses 0x014 through 0x01c are not used.
2087 19 jeremybenn
 
2088
@item irq = @var{value}
2089
@cindex @code{irq} (DMA configuration)
2090 82 jeremybenn
Use @var{value} as the IRQ number of this DMA controller.  Default value 0.
2091 19 jeremybenn
 
2092
@item vapi_id = @var{value}
2093
@cindex @code{vapi_id} (DMA configuration)
2094
@var{value} specifies the value of the Verification API (VAPI) base
2095 82 jeremybenn
address to be used with the DMA controller.  @xref{Verification API, ,
2096 19 jeremybenn
Verification API}, for more details, which details the use of the VAPI
2097
with the DMA controller.
2098
 
2099
@end table
2100
 
2101
@node Ethernet Configuration
2102
@subsection Ethernet Configuration
2103
@cindex configuring the Ethernet interface
2104
@cindex Ethernet configuration
2105
@cindex @code{section ethernet}
2106
The Ethernet MAC used in @value{OR1KSIM} is the component implemented
2107
at OpenCores, and found in the top level CVS directory,
2108 82 jeremybenn
@file{ethernet}.  It also forms part of the OpenRISC SoC, ORPSoC.  It is
2109 19 jeremybenn
described in the document @cite{Ethernet IP Core Specification} by
2110 82 jeremybenn
Igor Mohor, which can be found in the @file{doc} subdirectory.  It is a
2111 19 jeremybenn
memory mapped component, which resides on the main OpenRISC Wishbone
2112
data bus.
2113
 
2114 82 jeremybenn
Ethernet configuration is described in @code{section ethernet}.  This
2115 19 jeremybenn
section may appear multiple times, specifying multiple Ethernet
2116 82 jeremybenn
interfaces.  The following parameters may be specified.
2117 19 jeremybenn
 
2118
@table @code
2119
 
2120
@item enabled = 0|1
2121
@cindex @code{enabled} (Ethernet configuration)
2122 82 jeremybenn
If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it is
2123 19 jeremybenn
disabled.
2124
 
2125
@item baseaddr = @var{value}
2126
@cindex @code{baseaddr} (Ethernet configuration)
2127
Set the base address of the MAC's memory mapped registers to
2128 82 jeremybenn
@var{value}.  The default is 0, which is probably not a sensible value.
2129 19 jeremybenn
 
2130
The Ethernet MAC has a 7-bit address bus, with a total of 21
2131 82 jeremybenn
32-bit registers.  Addresses 0x54 through 0x7c are not used.
2132 19 jeremybenn
 
2133
@quotation Note
2134
The Ethernet specification describes a Tx control register,
2135 82 jeremybenn
@code{TXCTRL}, at address 0x50.  However this register is not
2136 19 jeremybenn
implemented in the @value{OR1KSIM} model.
2137
@end quotation
2138
 
2139
@item dma = @var{value}
2140
@cindex @code{dma} (Ethernet configuration)
2141
@var{value} specifies the DMA controller with which this Ethernet is
2142 82 jeremybenn
associated.  The default value is 0.
2143 19 jeremybenn
 
2144
@quotation Note
2145
Support for external DMA is not provided in the current
2146 82 jeremybenn
implementation, and this value is ignored.  In any case there is no
2147 19 jeremybenn
equivalent field to which this can be matched in the current DMA
2148
component implementation (@pxref{DMA Configuration, , DMA
2149
Configuration}).
2150
@end quotation
2151
 
2152
@item irq = @var{value}
2153
@cindex @code{dma} (Ethernet configuration)
2154 82 jeremybenn
Use @var{value} as the IRQ number of this Ethernet MAC.  Default value 0.
2155 19 jeremybenn
 
2156
@item rtx_type = 0|1
2157
@cindex @code{rtx_type} (Ethernet configuration)
2158
If 1 (true) use a socket interface to the Ethernet (see parameter
2159 82 jeremybenn
@code{sockif} below).  If 0 (the default), use a file interface,
2160 19 jeremybenn
reading and writing from and to the files specified in the
2161
@code{rxfile} and @code{txfile} parameters (see below).
2162
 
2163
@quotation Note
2164 82 jeremybenn
By default the socket interface is not provided in @value{OR1KSIM}.  If
2165 19 jeremybenn
it is required, this must be requested when configuring, by use of the
2166
@code{--enable-ethphy} option to @command{configure}.
2167
 
2168
@example
2169
configure --target=or32-uclinux --enable-ethphy ...
2170
@end example
2171
@end quotation
2172
 
2173
@item rx_channel = @var{rxvalue}
2174
@cindex @code{rx_channel} (Ethernet configuration)
2175
@itemx tx_channel = @var{txvalue}
2176
@cindex @code{tx_channel} (Ethernet configuration)
2177
@var{rxvalue} specifies the DMA channel to use for receive and
2178 82 jeremybenn
@var{txvalue} the DMA channel to use for transmit.  Both default to 0.
2179 19 jeremybenn
 
2180
@quotation Note
2181
As noted above, support for external DMA is not provided in the
2182
current implementation, and so these values are ignored.
2183
@end quotation
2184
 
2185
@item rxfile = "@var{rxfile}"
2186
@cindex @code{rxfile} (Ethernet configuration)
2187
@itemx txfile = "@var{txfile}"
2188
@cindex @code{txfile} (Ethernet configuration)
2189
When @code{rtx_type} is 0 (see above), @var{rxfile} specifies the file
2190
to use as input and @var{txfile} specifies the fie to use as
2191
output.
2192
 
2193 82 jeremybenn
The file contains a sequence of packets.  Each packet consists of a
2194
packet length (32 bits), followed by that many bytes of data.  Once the
2195 19 jeremybenn
input file is empty, the Ethernet MAC behaves as though there were no
2196 82 jeremybenn
data on the Ethernet.  The default values of these parameters are
2197 19 jeremybenn
@code{"eth_rx"} and @code{"eth_tx"} respectively.
2198
 
2199 82 jeremybenn
The input file must exist and be readable.  The output file must be
2200
writable and will be created if necessary.  If either of these
2201 19 jeremybenn
conditions is not met, a warning will be given.
2202
 
2203
@item sockif = "@var{service}"
2204
@cindex @code{sockif} (Ethernet configuration)
2205
When @code{rtx_type} is 1 (see above), @var{service} specifies the
2206 82 jeremybenn
service to use for communication.  This may be TCP/IP or UDP/IP.  The
2207 19 jeremybenn
default value of this parameter is @code{"or1ksim_eth"}.
2208
 
2209
@item vapi_id = @var{value}
2210
@cindex @code{vapi_id} (DMA configuration)
2211
@var{value} specifies the value of the Verification API (VAPI) base
2212 82 jeremybenn
address to be used with the Ethernet PHY.  @xref{Verification API, ,
2213 19 jeremybenn
Verification API}, for more details, which details the use of the VAPI
2214
with the DMA controller.
2215
 
2216
@end table
2217
 
2218
@node GPIO Configuration
2219
@subsection GPIO Configuration
2220
@cindex configuring the GPIO
2221
@cindex GPIO configuration
2222
@cindex @code{section cpio}
2223
The GPIO used in @value{OR1KSIM} is the component implemented at
2224 82 jeremybenn
OpenCores, and found in the top level CVS directory, @file{gpio}.  It
2225 19 jeremybenn
is described in the document @cite{GPIO IP Core Specification} by
2226
Damjan Lampret and Goran Djakovic, which can be found in the
2227 82 jeremybenn
@file{doc} subdirectory.  It is a memory mapped component, which
2228 19 jeremybenn
resides on the main OpenRISC Wishbone data bus.
2229
 
2230 82 jeremybenn
GPIO configuration is described in @code{@w{section gpio}}.  This section
2231
may appear multiple times, specifying multiple GPIO devices.  The
2232 19 jeremybenn
following parameters may be specified.
2233
 
2234
@table @code
2235
 
2236
@item enabled = 0|1
2237
@cindex @code{enabled} (GPIO configuration)
2238 82 jeremybenn
If 1 (true, the default), this GPIO is enabled.  If 0, it is disabled.
2239 19 jeremybenn
 
2240
@item baseaddr = @var{value}
2241
@cindex @code{baseaddr} (GPIO configuration)
2242
Set the base address of the GPIO's memory mapped
2243 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
2244 19 jeremybenn
sensible value.
2245
 
2246
The GPIO has a 6 bit address bus, with a total of 10 32-bit registers,
2247 82 jeremybenn
although the number of bits that are actively used varies.  Addresses
2248 19 jeremybenn
0x28 through 0x3c are not used.
2249
 
2250
@item irq = @var{value}
2251
@cindex @code{irq} (GPIO configuration)
2252 82 jeremybenn
Use @var{value} as the IRQ number of this GPIO.  Default value 0.
2253 19 jeremybenn
 
2254
@item vapi_id = @var{value}
2255
@cindex @code{vapi_id} (GPIO configuration)
2256
@cindex @code{base_vapi_id} (GPIO configuration - deprecated)
2257
@var{value} specifies the value of the Verification API (VAPI) base
2258 82 jeremybenn
address to be used with the GPIO.  @xref{Verification API, ,
2259 19 jeremybenn
Verification API}, for more details, which details the use of the VAPI
2260 82 jeremybenn
with the GPIO controller.  For backwards compatibility, the
2261 19 jeremybenn
alternative name @code{base_vapi_id} is supported for this parameter,
2262
but deprecated.
2263
 
2264
@end table
2265
 
2266
@node Display Interface Configuration
2267
@subsection Display Interface Configuration
2268
@cindex configuring the VGA interface
2269
@cindex display interface configuration
2270
@cindex VGA configuration
2271
@cindex @code{section vga}
2272
@value{OR1KSIM} models a VGA interface to an external monitor.  The
2273
VGA controller used in @value{OR1KSIM} is the component implemented at
2274
OpenCores, and found in the top level CVS directory, @file{vga_lcd},
2275 82 jeremybenn
with no support for the optional hardware cursors.  It is described in
2276 19 jeremybenn
the document @cite{VGA/LCD Core v2.0 Specifications} by Richard
2277 82 jeremybenn
Herveille, which can be found in the @file{doc} subdirectory.  It is a
2278 19 jeremybenn
memory mapped component, which resides on the main OpenRISC Wishbone
2279
data bus.
2280
 
2281
The current implementation provides only functionality to dump the
2282
screen to a file at intervals.
2283
 
2284
VGA controller configuration is described in @code{@w{section
2285 82 jeremybenn
vga}}.  This section may appear multiple times, specifying multiple
2286
VGA controllers.  The following parameters may be specified.
2287 19 jeremybenn
 
2288
@table @code
2289
 
2290
@item enabled = 0|1
2291
@cindex @code{enabled} (VGA configuration)
2292 82 jeremybenn
If 1 (true, the default), this VGA is enabled.  If 0, it is disabled.
2293 19 jeremybenn
 
2294
@item baseaddr = @var{value}
2295
@cindex @code{baseaddr} (VGA configuration)
2296
Set the base address of the VGA controller's memory mapped
2297 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
2298 19 jeremybenn
sensible value.
2299
 
2300
The VGA controller has a 12-bit address bus, with 7 32-bit registers, at
2301
addresses 0x000 through 0x018, and two color lookup tables at
2302 82 jeremybenn
addresses 0x800 through 0xfff.  The hardware cursor registers are not
2303 19 jeremybenn
implemented, so addresses 0x01c through 0x7fc are not used.
2304
 
2305
@item irq = @var{value}
2306
@cindex @code{irq} (VGA configuration)
2307 82 jeremybenn
Use @var{value} as the IRQ number of this VGA controller.  Default
2308 19 jeremybenn
value 0.
2309
 
2310
@item refresh_rate = @var{value}
2311
@cindex @code{refresh_rate} (VGA configuration)
2312 82 jeremybenn
@var{value} specifies number of cycles between screen dumps.  Default
2313 19 jeremybenn
value is derived from the simulation clock cycle time
2314
(@pxref{Simulator Behavior, , Simulator Behavior}), to correspond
2315
to dumping 50 times per simulated second.
2316
 
2317
@item txfile = "@var{file}"
2318
@cindex @code{txfile} (VGA configuration)
2319
@cindex @code{filename} (VGA configuration - deprecated)
2320
@var{file} specifies the base of the filename for screen
2321 82 jeremybenn
dumps.  Successive screen dumps will be in BMP format, in files with
2322 19 jeremybenn
the name @file{@var{file}@var{nnnn}.bmp}, where @var{nnnn} is a
2323 82 jeremybenn
sequential count of the screen dumps starting at zero.  The default
2324
value is @code{"vga_out"}.  For backwards compatibility, the
2325 19 jeremybenn
alternative name @code{filename} is supported for this parameter,
2326
but deprecated.
2327
 
2328
@end table
2329
 
2330
@node Frame Buffer Configuration
2331
@subsection Frame Buffer Configuration
2332
@cindex configuring the frame buffer
2333
@cindex frame buffer configuration
2334
@cindex @code{section fb}
2335
@quotation Caution
2336 82 jeremybenn
The frame buffer is only partially implemented.  Its configuration
2337 19 jeremybenn
fields are described here, but the component should not be used at
2338 82 jeremybenn
this time.  Like the VGA controller, it is designed to make screen
2339 19 jeremybenn
dumps to file.
2340
@end quotation
2341
 
2342 82 jeremybenn
Frame buffer configuration is described in @code{section fb}.  This
2343 19 jeremybenn
section may appear multiple times, specifying multiple frame
2344 82 jeremybenn
buffers.  The following parameters may be specified.
2345 19 jeremybenn
 
2346
@table @code
2347
 
2348
@item enabled = 0|1
2349
@cindex @code{enabled} (frame buffer configuration)
2350 82 jeremybenn
If 1 (true, the default), this frame buffer is enabled.  If 0, it is disabled.
2351 19 jeremybenn
 
2352
@item baseaddr = @var{value}
2353
@cindex @code{baseaddr} (frame buffer configuration)
2354
Set the base address of the frame buffer's memory mapped registers to
2355 82 jeremybenn
@var{value}.  The default is 0, which is probably not a sensible value.
2356 19 jeremybenn
 
2357
The frame buffer has an 121-bit address bus, with 4 32-bit registers,
2358
at addresses 0x000 through 0x00c, and a PAL lookup table at addresses
2359 82 jeremybenn
0x400 through 0x4ff.  Addresses 0x010 through 0x3fc and addresses 0x500
2360 19 jeremybenn
through 0x7ff are not used.
2361
 
2362
@item refresh_rate = @var{value}
2363
@cindex @code{refresh_rate} (frame buffer configuration)
2364 82 jeremybenn
@var{value} specifies number of cycles between screen dumps.  Default
2365 19 jeremybenn
value is derived from the simulation clock cycle time
2366
(@pxref{Simulator Behavior, , Simulator Behavior}), to correspond to
2367
dumping 50 times per simulated second.
2368
 
2369
@item txfile = "@var{file}"
2370
@cindex @code{txfile} (frame buffer configuration)
2371
@cindex @code{filename} (frame buffer configuration - deprecated)
2372
@var{file} specifies the base of the filename for screen
2373 82 jeremybenn
dumps.  Successive screen dumps will be in BMP format, in files with
2374 19 jeremybenn
the name @file{@var{file}@var{nnnn}.bmp}, where @var{nnnn} is a
2375 82 jeremybenn
sequential count of the screen dumps starting at zero.  The default
2376
value is @code{"fb_out"}.  For backwards compatibility, the
2377 19 jeremybenn
alternative name @code{filename} is supported for this parameter,
2378
but deprecated.
2379
 
2380
@end table
2381
 
2382
@node Keyboard Configuration
2383
@subsection Keyboard Configuration (PS2)
2384
@cindex configuring the keyboard interface
2385
@cindex configuring the PS2 interface
2386
@cindex keyboard configuration
2387
@cindex PS2 configuration
2388
@cindex @code{section kb}
2389 82 jeremybenn
The PS2 interface provided by @value{OR1KSIM} is not documented.  It
2390 19 jeremybenn
may be based on the PS2 project at OpenCores, and found in
2391 82 jeremybenn
the top level CVS directory, @file{ps2}.  However this project lacks
2392
any documentation beyond its project webpage.  Since most PS2
2393 19 jeremybenn
interfaces follow the Intel i8042 standard, this is presumably what is
2394
expected with this device.
2395
 
2396
The implementation only provides for keyboard support, which is
2397 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2398 19 jeremybenn
 
2399
@quotation Caution
2400
A standard i8042 device has two registers at addresses 0x60 (command)
2401 82 jeremybenn
and 0x64 (status).  Inspection of the code, suggests that the
2402 19 jeremybenn
@value{OR1KSIM} component places these registers at addresses 0x00 and
2403
0x04.
2404
 
2405
The port of Linux for the OpenRISC 1000, which runs on @value{OR1KSIM}
2406
implements the i8042 device driver, anticipating these registers
2407 82 jeremybenn
reside at their conventional address.  It seems unlikel that this code
2408 19 jeremybenn
will work.
2409
 
2410
This component should be used with caution.
2411
@end quotation
2412
 
2413 82 jeremybenn
Keyboard configuration is described in @code{section kbd}.  This
2414 19 jeremybenn
section may appear multiple times, specifying multiple keyboard
2415 82 jeremybenn
interfaces.  The following parameters may be specified.
2416 19 jeremybenn
 
2417
@table @code
2418
 
2419
@item enabled = 0|1
2420
@cindex @code{enabled} (keyboard configuration)
2421 82 jeremybenn
If 1 (true, the default), this keyboard is enabled.  If 0, it is disabled.
2422 19 jeremybenn
 
2423
@item baseaddr = @var{value}
2424
@cindex @code{baseaddr} (keyboard configuration)
2425
Set the base address of the keyboard's memory mapped registers to
2426 82 jeremybenn
@var{value}.  The default is 0, which is probably not a sensible value.
2427 19 jeremybenn
 
2428
The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit registers,
2429
at addresses 0x000 and 0x004.
2430
 
2431
@quotation Caution
2432
As noted above, a standard Intel 8042 interface would expect to find
2433
these registers at locations 0x60 and 0x64, thus requiring at least a
2434
7-bit bus.
2435
@end quotation
2436
 
2437
@item irq = @var{value}
2438
@cindex @code{irq} (keyboard configuration)
2439 82 jeremybenn
Use @var{value} as the IRQ number of this Keyboard interface.  Default
2440 19 jeremybenn
value 0.
2441
 
2442
@item rxfile = "@var{file}"
2443
@cindex @code{file} (keyboard configuration)
2444
@file{file} specifies a file containing raw key stroke data, which
2445 82 jeremybenn
models the input from a physical keyboard.  The default value is
2446 19 jeremybenn
@code{"kbd_in"}.
2447
 
2448
@end table
2449
 
2450
@node Disc Interface Configuration
2451
@subsection Disc Interface Configuration
2452
@cindex configuring the ATA/ATAPI interfaces
2453
@cindex disc interface configuration
2454
@cindex ATA/ATAPI configuration
2455
@cindex @code{section ata}
2456
The ATA/ATAPI disc controller used in @value{OR1KSIM} is the OCIDEC
2457
(OpenCores IDE Controller) component implemented at OpenCores, and
2458 82 jeremybenn
found in the top level CVS directory, @file{ata}.  It is described in
2459 19 jeremybenn
the document @cite{ATA/ATAPI-5 Core Specification} by Richard
2460 82 jeremybenn
Herveille, which can be found in the @file{doc} subdirectory.  It is a
2461 19 jeremybenn
memory mapped component, which resides on the main OpenRISC Wishbone
2462
data bus.
2463
 
2464 82 jeremybenn
ATA/ATAPI configuration is described in @code{@w{section ata}}.  This section
2465
may appear multiple times, specifying multiple disc controllers.  The
2466 19 jeremybenn
following parameters may be specified.
2467
 
2468
@table @code
2469
 
2470
@item enabled = 0|1
2471
@cindex @code{enabled} (ATA/ATAPI configuration)
2472 82 jeremybenn
If 1 (true, the default), this ATA/ATAPI interface is enabled.  If 0,
2473 19 jeremybenn
it is disabled.
2474
 
2475
@item baseaddr = @var{value}
2476
@cindex @code{baseaddr} (ATA/ATAPI configuration)
2477
Set the base address of the ATA/ATAPI interface's memory mapped
2478 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
2479 19 jeremybenn
sensible value.
2480
 
2481
The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8 32-bit
2482 82 jeremybenn
registers.  Depending on the version of the OCIDEC ATA/ATAPI interface
2483 19 jeremybenn
selected (see @code{dev_id} below), not all registers will be available.
2484
 
2485
@item irq = @var{value}
2486
@cindex @code{irq} (ATA/ATAPI configuration)
2487 82 jeremybenn
Use @var{value} as the IRQ number of this ATA/ATAPI interface.  Default
2488 19 jeremybenn
value 0.
2489
 
2490
@item dev_id = 1|2|3
2491
@cindex @code{dev_id} (ATA/ATAPI configuration)
2492
This parameter specifies which version of the OCIDEC ATA/ATAPI
2493 82 jeremybenn
interface to model.  The default value is 1.
2494 19 jeremybenn
 
2495
Version 1 supports only the @code{CTRL}, @code{STAT} and @code{PCTR}
2496 82 jeremybenn
registers.  Versions 2 & 3 add the @code{FCTR} registers, Version 3
2497 19 jeremybenn
adds the @code{DTR} registers and the @code{RXD}/@code{TXD} registers.
2498
 
2499
@item rev = @var{value}
2500
@cindex @code{rev} (ATA/ATAPI configuration)
2501
Set the @var{value} as the revision of the OCIDEC ATA/ATAPI
2502 82 jeremybenn
interface.  The default value is 1.  The default value is 0.  Its value
2503
should be in the range 0-15.  Larger values are truncated with a
2504
warning.  This only affects the reset value of the @code{STAT}
2505 19 jeremybenn
register, where it forms bits 24-27.
2506
 
2507
@item pio_mode0_t1 = @var{value}
2508
@cindex @code{pio_mode0_t1} (ATA/ATAPI configuration)
2509
@itemx pio_mode0_t2 = @var{value}
2510
@cindex @code{pio_mode0_t2} (ATA/ATAPI configuration)
2511
@itemx pio_mode0_t4 = @var{value}
2512
@cindex @code{pio_mode0_t4} (ATA/ATAPI configuration)
2513
@itemx pio_mode0_teoc = @var{value}
2514
@cindex @code{pio_mode0_teoc} (ATA/ATAPI configuration)
2515
These parameters specify the timings for use with Programmed
2516 82 jeremybenn
Input/Output (PIO) transfers.  They are specified as the number of
2517 19 jeremybenn
clock cycles - 2, rounded up to the next highest integer, or zero if
2518 82 jeremybenn
that would be negative.  The values should not exceed 255.  If they do,
2519 19 jeremybenn
they will be ignored with a warning.
2520
 
2521
See the ATA/ATAPI-5 specification for explanations of each of these
2522 82 jeremybenn
timing parameters.  The default values are:
2523 19 jeremybenn
 
2524
@example
2525
pio_mode0_t1   =  6
2526
pio_mode0_t2   = 28
2527
pio_mode0_t4   =  2
2528
pio_mode0_teoc = 23
2529
@end example
2530
 
2531
@item dma_mode0_tm = @var{value}
2532
@cindex @code{dma_mode0_tm} (ATA/ATAPI configuration)
2533
@itemx dma_mode0_td = @var{value}
2534
@cindex @code{dma_mode0_td} (ATA/ATAPI configuration)
2535
@itemx dma_mode0_teoc = @var{value}
2536
@cindex @code{dma_mode0_teoc} (ATA/ATAPI configuration)
2537 82 jeremybenn
These parameters specify the timings for use with DMA transfers.  They
2538 19 jeremybenn
are specified as the number of clock cycles - 2, rounded up to the
2539 82 jeremybenn
next highest integer, or zero if that would be negative.  The values
2540
should not exceed 255.  If they do, they will be ignored with a
2541 19 jeremybenn
warning.
2542
 
2543
See the ATA/ATAPI-5 specification for explanations of each of these
2544 82 jeremybenn
timing parameters.  The default values are:
2545 19 jeremybenn
 
2546
@example
2547
dma_mode0_tm   =  4
2548
dma_mode0_td   = 21
2549
dma_mode0_teoc = 21
2550
@end example
2551
 
2552
@end table
2553
 
2554
@subsubsection ATA/ATAPI Device Configuration
2555
@cindex disc interface device configuration
2556
@cindex ATA/ATAPI device configuration
2557
Within the @code{@w{section ata}}, each device is specified
2558 82 jeremybenn
separately.  The device subsection is introduced by
2559 19 jeremybenn
 
2560
@example
2561
device @var{value}
2562
@end example
2563
 
2564 82 jeremybenn
@var{value} is the device number, which should be 0 or 1.  The
2565
subsection ends with @code{enddevice}.  Note that if the same device
2566 19 jeremybenn
number is specified more than once, the previous values will be
2567 82 jeremybenn
overwritten.  Within the @code{device} subsection, the following
2568 19 jeremybenn
parameters may appear:
2569
 
2570
@table @code
2571
 
2572
@item type = @var{value}
2573
@cindex @code{type} (ATA/ATAPI device configuration)
2574
@var{value}specifies the type of device: 0 (the default) for ``not
2575
connected'', 1 for hard disk simulated in a file and 2 for local system
2576
hard disk.
2577
 
2578
@item file = "@var{filename}"
2579
@cindex @code{file} (ATA/ATAPI device configuration)
2580
@file{filename} specifies the file to be used for a simulated ATA
2581 82 jeremybenn
device if the file type (see @code{type} above) is 1.  Default value
2582 19 jeremybenn
@code{"ata-File@var{n}"}, where @var{n} is the device number.
2583
 
2584
@item size = @var{value}
2585
@cindex @code{size} (ATA/ATAPI device configuration)
2586
@var{value} specifies the size of a simulated ATA device if the file
2587 82 jeremybenn
type (see @code{type} above) is 1.  The default value is zero.
2588 19 jeremybenn
 
2589
@item packet = 0|1
2590
@cindex @code{packet} (ATA/ATAPI device configuration)
2591 82 jeremybenn
If 1 (true), implement the PACKET command feature set.  If 0 (the
2592 19 jeremybenn
default), do not implement the PACKET command feature set.
2593
 
2594
@item firmware = "@var{str}"
2595
@cindex @code{firmware} (ATA/ATAPI device configuration)
2596
Firmware to report in response to the ``Identify Device''
2597 82 jeremybenn
command.  Default @code{"02207031"}.
2598 19 jeremybenn
 
2599
@item heads = @var{value}
2600
@cindex @code{heads} (ATA/ATAPI device configuration)
2601 82 jeremybenn
Number of heads in the device.  Default 7, use -1 to disable all heads.
2602 19 jeremybenn
 
2603
@item sectors = @var{value}
2604
@cindex @code{sectors} (ATA/ATAPI device configuration)
2605 82 jeremybenn
Number of sectors per track in the device.  Default 32.
2606 19 jeremybenn
 
2607
@item mwdma = 0|1|2|-1
2608
@cindex @code{mwdma} (ATA/ATAPI device configuration)
2609 82 jeremybenn
Highest multi-word DMA mode supported.  Default 2, use -1 to disable.
2610 19 jeremybenn
 
2611
@item pio = 0|1|2|3|4
2612
@cindex @code{pio} (ATA/ATAPI device configuration)
2613 82 jeremybenn
Highest PIO mode supported.  Default 4.
2614 19 jeremybenn
 
2615
@end table
2616
 
2617
@node Generic Peripheral Configuration
2618
@subsection Generic Peripheral Configuration
2619
@cindex generic peripheral configuration
2620
@cindex configuration of generic peripherals
2621
@cindex @code{section generic}
2622
When used as a library (@pxref{Simulator Library, , Simulator
2623
Library}), @value{OR1KSIM} makes provision for any additional peripheral to be
2624 82 jeremybenn
implemented externally.  Any read or write access to this peripheral's
2625
memory map generates @dfn{upcall}s to an external handler.  This
2626 19 jeremybenn
interface can support either C or C++, and was particularly designed
2627
to facilitate support for OSCI SystemC (see @url{http://www.systemc.org}).
2628
 
2629
Generic peripheral configuration is described in @code{@w{section
2630 82 jeremybenn
generic}}.  This section may appear multiple times, specifying multiple
2631
external peripherals.  The following parameters may be specified.
2632 19 jeremybenn
 
2633
@table @code
2634
 
2635
@item enabled = 0|1
2636
@cindex @code{enabled} (generic peripheral configuration)
2637 82 jeremybenn
If 1 (true, the default), this ATA/ATAPI interface is enabled.  If 0,
2638 19 jeremybenn
it is disabled.
2639
 
2640
@item baseaddr = @var{value}
2641
@cindex @code{baseaddr} (generic peripheral configuration)
2642
Set the base address of the generic peripheral's memory mapped
2643 82 jeremybenn
registers to @var{value}.  The default is 0, which is probably not a
2644 19 jeremybenn
sensible value.
2645
 
2646
The size of the memory mapped register space is controlled by the
2647
@code{size} paramter, described below.
2648
 
2649
@item size = @var{value}
2650
@cindex @code{size} (generic peripheral configuration)
2651
Set the size of the generic peripheral's memory mapped register space
2652 82 jeremybenn
to @var{value} bytes.  Any read or write accesses to addresses with
2653 19 jeremybenn
offsets of 0 to @var{value}-1 bytes from the base address specified in
2654
parameter @code{baseaddr} (see above) will be directed to the external
2655
interface.
2656
 
2657 82 jeremybenn
@var{value} will be rounded up the nearest power of 2.  It's default
2658
value is zero.  If @var{value} is not an exact power of two, accesses
2659 19 jeremybenn
to address offsets of @var{value} or above up to the next power of 2
2660
will generate a warning, and have no effect (reads will return zero).
2661
 
2662
@item name = "@var{str}"
2663
@cindex @code{name} (generic peripheral configuration)
2664 82 jeremybenn
This gives the peripheral the name @code{"@var{str}"}.  This is used to
2665 19 jeremybenn
identify the peripheral in error messages and warnings, and when
2666 82 jeremybenn
reporting its status.  The default value is @code{@w{"anonymous
2667 19 jeremybenn
external peripheral"}}.
2668
 
2669
@item byte_enabled = 0|1
2670
@cindex @code{byte_enabled} (generic peripheral configuration)
2671
@itemx hw_enabled = 0|1
2672
@cindex @code{hw_enabled} (generic peripheral configuration)
2673
@itemx word_enabled = 0|1
2674
@cindex @code{word_enabled} (generic peripheral configuration)
2675
If 1 (true, the default), these parameters respectively enable the
2676 82 jeremybenn
device for byte wide, half-word wide and word wide accesses.  If 0,
2677 19 jeremybenn
accesses of that width will fail.
2678
 
2679
@end table
2680
 
2681
@node Interactive Command Line
2682
@chapter Interactive Command Line
2683
 
2684
If started with the @code{-f} flag, or if interrupted with
2685
@kbd{ctrl-C}, @value{OR1KSIM} provides the user with an interactive
2686 82 jeremybenn
command line.  The commands available, which may not be abbreviated, are:
2687 19 jeremybenn
 
2688
@table @code
2689
 
2690
@item q
2691
@cindex @code{q} (Interactive CLI)
2692
@cindex quitting (Interactive CLI)
2693
Exit the simulator
2694
 
2695
@item r
2696
@cindex @code{r} (Interactive CLI)
2697
@cindex displaying registers (Interactive CLI)
2698
@cindex register display (Interactive CLI)
2699 82 jeremybenn
Display all the General Purpose Registers (GPRs).  Also shows the just
2700 19 jeremybenn
executed and next to be executed instructions symbolically and the
2701
state of the flag in the Supervision Register.
2702
 
2703
@item t
2704
@cindex @code{t} (Interactive CLI)
2705
@cindex stepping code (Interactive CLI)
2706
Execute the next instruction and then display register/instruction
2707
information as with the @code{r} command (see above).
2708
 
2709
@item run @var{num} [ hush ]
2710
@cindex @code{run} (Interactive CLI)
2711
@cindex running code (Interactive CLI)
2712
@cindex executing code (Interactive CLI)
2713 82 jeremybenn
Execute @var{num} instructions.  The register/instruction information
2714 19 jeremybenn
is displayed after each instruction, as with the @code{r} command (see
2715
above) @emph{unless} @code{hush} is specified.
2716
 
2717
@item pr @var{reg} @var{value}
2718
@cindex @code{pr} (Interactive CLI)
2719
@cindex patching registers (Interactive CLI)
2720
@cindex register patching (Interactive CLI)
2721
Patch register @var{reg} with @var{value}.
2722
 
2723
@item dm @var{fromaddr} [ @var{toaddr} ]
2724
@cindex @code{dm} (Interactive CLI)
2725
@cindex displaying memory (Interactive CLI)
2726
@cindex memory display (Interactive CLI)
2727 82 jeremybenn
Display memory bytes between @var{fromaddr} and @var{toaddr}.  If
2728 19 jeremybenn
@var{toaddr} is not given, 64 bytes are displayed, starting at
2729
@var{fromaddr}.
2730
 
2731
@quotation Caution
2732 82 jeremybenn
The output from this command is broken (a bug).  @value{OR1KSIM}
2733
attempts to print out 16 bytes per row.  However, instead of printing
2734 19 jeremybenn
out the address at the start of each row, it prints the address (of
2735
the first of the 16 bytes) before @emph{each} byte.
2736
@end quotation
2737
 
2738
@item de @var{fromaddr} [ @var{toaddr} ]
2739
@cindex @code{dm} (Interactive CLI)
2740
@cindex disassemble (Interactive CLI)
2741 82 jeremybenn
Disassemble code between @var{fromaddr} and @var{toaddr}.  If
2742 19 jeremybenn
@var{toaddr} is not given, 16 instructions are disassembled.
2743
 
2744
The disassembly is entirely numerical, and gives no symbolic
2745
information.
2746
 
2747
@item pm @var{addr} @var{value}
2748
@cindex @code{pm} (Interactive CLI)
2749
@cindex patching memory (Interactive CLI)
2750
@cindex memory patching (Interactive CLI)
2751
Patch the 4 bytes in memory starting at @var{addr} with the 32-bit
2752
@var{value}.
2753
 
2754
@item pc @var{value}
2755
@cindex @code{pc} (Interactive CLI)
2756
@cindex patching the program counter (Interactive CLI)
2757
@cindex program counter patching (Interactive CLI)
2758
Patch the program counter with @var{value}.
2759
 
2760
@item cm @var{fromaddr} @var{toaddr} @var{size}
2761
@cindex @code{cm} (Interactive CLI)
2762
@cindex copying memory (Interactive CLI)
2763
@cindex memory copying (Interactive CLI)
2764
Copy @var{size} bytes in memory from @var{fromaddr} to @var{toaddr}.
2765
 
2766
@item break @var{addr}
2767
@cindex @code{break} (Interactive CLI)
2768
@cindex breakpoint set/clear (Interactive CLI)
2769
@cindex set breakpoint (Interactive CLI)
2770
@cindex clear breakpoint (Interactive CLI)
2771
@cindex toggle breakpoint (Interactive CLI)
2772
Toggle the breakpoint set at @var{addr}.
2773
 
2774
@item breaks
2775
@cindex @code{breaks} (Interactive CLI)
2776
@cindex breakpoint list (Interactive CLI)
2777
@cindex list breakpoints (Interactive CLI)
2778
List all set breakpoints
2779
 
2780
@item reset
2781
@cindex @code{reset} (Interactive CLI)
2782
@cindex simulator reset (Interactive CLI)
2783
@cindex reset the simulator (Interactive CLI)
2784 82 jeremybenn
Reset the simulator.  Includes modeling a reset of the processor, so
2785 19 jeremybenn
execution will restart from the reset vector location, 0x100.
2786
 
2787
@item hist
2788
@cindex @code{hist} (Interactive CLI)
2789
@cindex execution history (Interactive CLI)
2790
@cindex history of execution (Interactive CLI)
2791
If saving the execution history has been configured (@pxref{Simulator
2792
Behavior, , Simulator Behavior}), display the execution history.
2793
 
2794
@item stall
2795
@cindex @code{stall} (Interactive CLI)
2796
@cindex processor stall (Interactive CLI)
2797
@cindex stall the processor (Interactive CLI)
2798 82 jeremybenn
Stall the processor, so that control is passed to the debug unit.  When
2799
stalled, the processor can execute no instructions.  This command is
2800 19 jeremybenn
useful when debugging the JTAG interface, used by debuggers such as
2801
GDB.
2802
 
2803
@item unstall
2804
@cindex @code{unstall} (Interactive CLI)
2805
@cindex processor unstall (Interactive CLI)
2806
@cindex unstall the processor (Interactive CLI)
2807 82 jeremybenn
Unstall the processor, so that normal execution can continue.  This command is
2808 19 jeremybenn
useful when debugging the JTAG interface, used by debuggers such as GDB.
2809
 
2810
@item stats @var{category} | clear
2811
@cindex @code{stats} (Interactive CLI)
2812
@cindex simulator statistics (Interactive CLI)
2813
@cindex statistics, simulation (Interactive CLI)
2814
Print the statistics for the given @var{category}, if available, or
2815 82 jeremybenn
clear if @code{clear} is specified.  The categories are:
2816 19 jeremybenn
 
2817
@table @asis
2818
 
2819
@item 1
2820
Miscellaneous statistics: branch predictions (if branch predictions
2821
are enabled), branch target cache model (if enabled), cache (if
2822
enbaled), MMU (if enabled) and number of addtional load & store
2823
cycles.
2824
 
2825
@xref{Core OpenRISC Configuration, , Configuring the OpenRisc
2826
Achitectural Components}, for details of how to enable these various
2827
features.
2828
 
2829
@item 2
2830 82 jeremybenn
Instruction usage statistics.  Requires hazard analysis to be enabled
2831 19 jeremybenn
(@pxref{CPU Configuration, ,CPU Configuration}).
2832
 
2833
@item 3
2834 82 jeremybenn
Instruction dependency statistics.  Requires hazard analysis to be enabled
2835 19 jeremybenn
(@pxref{CPU Configuration, ,CPU Configuration}).
2836
 
2837
@item 4
2838 82 jeremybenn
Functional unit dependency statistics.  Requires hazard analysis to be enabled
2839 19 jeremybenn
(@pxref{CPU Configuration, ,CPU Configuration}).
2840
 
2841
@item 5
2842 82 jeremybenn
Raw register usage over time.  Requires hazard analysis to be enabled
2843 19 jeremybenn
(@pxref{CPU Configuration, ,CPU Configuration}).
2844
 
2845
@item 6
2846 82 jeremybenn
Store buffer statistics.  Requires the store buffer to be enabled
2847 19 jeremybenn
(@pxref{CPU Configuration, ,CPU Configuration}).
2848
 
2849
@end table
2850
 
2851
@item info
2852
@cindex @code{info} (Interactive CLI)
2853
@cindex simulator configuration info (Interactive CLI)
2854
@cindex configuration info (Interactive CLI)
2855 82 jeremybenn
Display detailed information about the simulator configuration.  This
2856 19 jeremybenn
is quite a lengthy about, because all MMU TLB information is displayed.
2857
 
2858
@item dv @var{fromaddr} [ @var{toaddr} ] [ @var{module} ]
2859
@cindex @code{dv} (Interactive CLI)
2860
@cindex Verilog memory dump (Interactive CLI)
2861
@cindex memory dump, Verilog (Interactive CLI)
2862
Dump the area of memory between @var{fromaddr} and @var{toaddr} as
2863
Verilog code for a synchronous, 23-bit wide SRAM module, named
2864 82 jeremybenn
@var{module}.  If @var{toaddr} is not specified, then 64 bytes are
2865
dumped (as 16 32-bit words).  If @var{module} is not specified,
2866 19 jeremybenn
@code{or1k_mem} is used.
2867
 
2868
To save to a file, use the redirection function (described after this
2869
table, below).
2870
 
2871
@item dh @var{fromaddr} [ @var{toaddr} ]
2872
@cindex @code{dv} (Interactive CLI)
2873
@cindex hexadecimal memory dump (Interactive CLI)
2874
@cindex memory dump, hexadecimal (Interactive CLI)
2875
Dump the area of memory between @var{fromaddr} and @var{toaddr} as
2876 82 jeremybenn
32-bit hex numbers (no @code{0x}, or @code{32'h} prefix).  If
2877 19 jeremybenn
@var{toaddr} is not specified, then 64 bytes are dumped (as 16 32-bit
2878
words).
2879
 
2880
To save to a file, use the redirection function (described after this
2881
table, below).
2882
 
2883
@item setdbch
2884
@cindex @code{setdbch} (Interactive CLI)
2885
@cindex debug channel toggle (Interactive CLI)
2886
@cindex toggle debug channels (Interactive CLI)
2887 82 jeremybenn
Toggle debug channels on/off.  @xref{Standalone Simulator, , Standalone
2888 19 jeremybenn
Simulator}, for a description of specifying debug channels on the
2889
command line.
2890
 
2891
@item set @var{section} @var{param} = @var{value}
2892
@cindex @code{set} (Interactive CLI)
2893
@cindex configuration parameter setting (Interactive CLI)
2894
Set the configuration parameter @var{para} in section @var{section} to
2895 82 jeremybenn
@var{value}.  @xref{Configuration, , Configuration}, for details of
2896 19 jeremybenn
configuration parameters and their settings.
2897
 
2898
@item debug
2899
@cindex @code{debug} (Interactive CLI)
2900
@cindex debug mode toggle (Interactive CLI)
2901
@cindex toggle debug mode (Interactive CLI)
2902 82 jeremybenn
Toggle the simulator debug mode.  @xref{Debug Interface Configuration,
2903 19 jeremybenn
, Debug Interface Configuration}, for information on this parameter.
2904
 
2905
@quotation Caution
2906 82 jeremybenn
This is effectively enabling or disabling the debug unit.  It does not
2907
effect the remote GDB debug interface.  However using the remote debug
2908 19 jeremybenn
interface while the debug unit is disabled will lead to undefined
2909
behavior and likely crash @value{OR1KSIM}
2910
@end quotation
2911
 
2912
@item cuc
2913
@cindex @code{debug} (Interactive CLI)
2914
@cindex Custom Unit Compiler (Interactive CLI)
2915
Enter the the Custom Unit Compiler command prompt (@pxref{CUC
2916
Configuration, , CUC Configuration}).
2917
 
2918
@quotation Caution
2919 82 jeremybenn
The CUC must be properly configured, for this to succeed.  In
2920
particular a timing file must be available and readable.  Otherwise
2921 19 jeremybenn
@value{OR1KSIM} will crash.
2922
@end quotation
2923
 
2924
@item help
2925
@cindex @code{help} (Interactive CLI)
2926
@cindex Custom Unit Compiler (Interactive CLI)
2927
Print out brief information about each command available.
2928
 
2929
@item mprofile [-vh] [-m @var{m}] [-g @var{n}] [-f @var{file}] @var{from} @var{to}
2930
@cindex @code{mprofile} (Interactive CLI)
2931
@cindex memory profiling utility (Interactive CLI)
2932 82 jeremybenn
Run the memory profiling utility.  This follows the same usage as the
2933 19 jeremybenn
standalone command (@pxref{Memory Profiling Utility, , Memory
2934
Profiling Utility}).
2935
 
2936
@item profile [-vhcq] [-g @var{file}]
2937
@cindex @code{mprofile} (Interactive CLI)
2938
@cindex profiling utility (Interactive CLI)
2939
@cindex instruction profiling utility (Interactive CLI)
2940 82 jeremybenn
Run the instruction profiling utility.  This follows the same usage as the
2941 19 jeremybenn
standalone command (@pxref{Profiling Utility, , Profiling Utility}).
2942
 
2943
@end table
2944
 
2945
For all commands, it is possible to redirect the output to a file, by
2946
using the redirection operator, @code{>}.
2947
 
2948
@example
2949
@var{command} > @var{filename}
2950
@end example
2951
 
2952
This is particularly useful for commands dumping a large amount of
2953
output, such as @code{dv}.
2954
 
2955
@quotation Caution
2956 82 jeremybenn
Unfortunately there is a serious bug with the redirection operator.  It
2957 19 jeremybenn
does not return output to standard output after the command
2958 82 jeremybenn
completes.  Until this bug is fixed, file redirection should not be
2959 19 jeremybenn
used.
2960
@end quotation
2961
 
2962
@node Verification API
2963
@chapter Verification API (VAPI)
2964
 
2965
The Verification API (VAPI) provides a TCP/IP interface to allow
2966 82 jeremybenn
components of the simulation to be controlled externally.  The
2967 19 jeremybenn
interface is polled for new requests on each simulated clock
2968 82 jeremybenn
cycle.  Components within the simulator may send responses to such
2969 19 jeremybenn
requests.
2970
 
2971 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2972 19 jeremybenn
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2973 82 jeremybenn
with a single piece of data (also a 32 bit integer).  On the send side,
2974
it provides for sending a single VAPI ID and data.  However there is no
2975
explicit command-response structure.  Some components just accept
2976
requests (e.g.  to set values), some just generate sends (to report
2977 19 jeremybenn
values), and some do both.
2978
 
2979
Each component has a base ID (32 bit) and its commands will start from
2980 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2981
amongst components.  Request commands will be directed to the component with
2982 19 jeremybenn
the closest base ID lower than the VAPI ID of the command.
2983
 
2984
Thus if there are two components with base IDs of 0x200 and 0x300, and
2985
a request with VAPI ID of 0x203 is received, it will be directed to
2986
the first component as its command #3.
2987
 
2988
The results of VAPI interactions are logged (by default in
2989
@file{vapi.log} unless an alternative is specified in @code{@w{section
2990
vapi}}).
2991
 
2992
Currently the following components support VAPI:
2993
 
2994
@table @asis
2995
 
2996
@item Debug Unit
2997
@cindex Debug Unit verification (VAPI)
2998
@cindex VAPI for Debug Unit
2999
Although the Debug Unit can specify a base VAPI ID, it is not used to
3000
send commands or receive requests.
3001
 
3002
Instead, if the base VAPI ID is set, all remote JTAG protocol exchanges are
3003
logged in the VAPI log file.
3004
 
3005
@item UART
3006
@cindex UART verification (VAPI)
3007
@cindex VAPI for UART
3008
If a base VAPI ID is specified, the UART sends details of any chars or
3009
break characters sent, with dteails of the line control register etc
3010
encoded in the data packet sent.
3011
 
3012
This supports a single VAPI command request, but encodes a sub-command in the
3013
top 8 bits of the associated data.
3014
 
3015
@table @code
3016
 
3017
@item 0x00
3018
@cindex 0x00 UART VAPI sub-command (UART verification)
3019
This stuffs the least significant 8 bits of the data into the serial
3020
register of the UART and the next 8 bits into the line control
3021
register, effectively providing control of the next character to be
3022
sent or received.
3023
 
3024
@item 0x01
3025
@cindex 0x01 UART VAPI sub-command (UART verification)
3026
The divisor latch bytes are set from the least significant 16 bits of
3027
the data.
3028
 
3029
@item 0x02
3030
@cindex 0x02 UART VAPI sub-command (UART verification)
3031
The line control register is set from bits 15-8 of the data.
3032
 
3033
@item 0x03
3034
@cindex 0x03 UART VAPI sub-command (UART verification)
3035
The UART skew is set from the least significant 16 bits of the data
3036
 
3037
@item 0x04
3038
@cindex 0x04 UART VAPI sub-command (UART verification)
3039
If the 16th most significant bit of the data is 1, start sending
3040 82 jeremybenn
breaks, otherwise stop sending breaks.  The breaks are sent or cleared
3041 19 jeremybenn
after the number of UART clock divider ticks specified by the data
3042
(immediately if the data is zero).
3043
 
3044
@end table
3045
 
3046
@item DMA
3047
@cindex DMA verification (VAPI)
3048
@cindex VAPI for DMA
3049
Although the DMA unit supports a base VAPI ID in its configuration
3050
(@code{@w{section dma}}), no VAPI data is sent, nor VAPI requests
3051
currently implemented.
3052
 
3053
@item Ethernet
3054
@cindex Ethernet verification (VAPI)
3055
@cindex VAPI for Ethernet
3056 82 jeremybenn
The following requests are handled by the Ethernet.  Specified
3057 19 jeremybenn
symbolically, these are the increments from the base VAPI ID of the
3058 82 jeremybenn
Ethernet.  At present no implementation is provided behind these VAPI
3059 19 jeremybenn
requests.
3060
 
3061
@table @code
3062
 
3063
@item ETH_VAPI_DATA (0)
3064
@cindex @code{ETH_VAPI_DATA} (Ethernet verification)
3065
 
3066
@item ETH_VAPI_CTRL (0)
3067
@cindex @code{ETH_VAPI_CTRL} (Ethernet verification)
3068
 
3069
@end table
3070
 
3071
@item GPIO
3072
@cindex GPIO verification (VAPI)
3073
@cindex VAPI for GPIO
3074
If a base VAPI ID is specified, the GPIO sends out on its base VAPI ID
3075
(symbolically, GPIO_VAPI_DATA (0) offset from the base VAPI ID) any
3076
changes in outputs.
3077
 
3078 82 jeremybenn
The following requests are handled by the GPIO.  Specified
3079 19 jeremybenn
symbolically, these are the increments from the VAPI base ID of the
3080
GPIO.
3081
 
3082
@table @code
3083
 
3084
@item GPIO_VAPI_DATA (0)
3085
@cindex @code{GPIO_VAPI_DATA} (GPIO verification)
3086
Set the next input to the commands data field
3087
 
3088
@item GPIO_VAPI_AUX (1)
3089
@cindex @code{GPIO_VAPI_AUX} (GPIO verification)
3090
Set the GPIO auxiliary inputs to the data field
3091
 
3092
@item GPIO_VAPI_CLOCK (2)
3093
@cindex @code{GPIO_VAPI_CLOCK} (GPIO verification)
3094
Add an external GPIO clock trigger of period specified in the data field.
3095
 
3096
@item GPIO_VAPI_RGPIO_OE (3)
3097
@cindex @code{GPIO_VAPI_RGPIO} (GPIO verification)
3098
Set the GPIO output enable to the data field
3099
 
3100
@item GPIO_VAPI_RGPIO_INTE (4)
3101
@cindex @code{GPIO_VAPI_INTE} (GPIO verification)
3102
Set the next interrupt to the data field
3103
 
3104
@item GPIO_VAPI_RGPIO_PTRIG (5)
3105
@cindex @code{GPIO_VAPI_PTRIG} (GPIO verification)
3106
Set the next trigger to the data field
3107
 
3108
@item GPIO_VAPI_RGPIO_AUX (6)
3109
@cindex @code{GPIO_VAPI_AUX} (GPIO verification)
3110
Set the next auxiliary input to the data field
3111
 
3112
@item GPIO_VAPI_RGPIO_CTRL (7)
3113
@cindex @code{GPIO_VAPI_CTRL} (GPIO verification)
3114
Set th next control input to the data field
3115
 
3116
@end table
3117
 
3118
@end table
3119
 
3120
@node Code Internals
3121
@chapter A Guide to @value{OR1KSIM} Internals
3122
 
3123 82 jeremybenn
These are notes to help those wanting to extend @value{OR1KSIM}.  This
3124 19 jeremybenn
section assumes the use of a tag file, so file locations of entities'
3125 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
3126
Linux manual page for @command{etags}.  A tag file can be created
3127 19 jeremybenn
with:
3128
 
3129
@example
3130
make tags
3131
@end example
3132
 
3133
@menu
3134
* Coding Conventions::
3135
* Global Data Structures::
3136
* Concepts::
3137
* Internal Debugging::
3138
@end menu
3139
 
3140
@node Coding Conventions
3141
@section Coding Conventions for @value{OR1KSIM}
3142
 
3143
This chapter provides some guidelines for coding, to facilitate
3144
extensions to @value{OR1KSIM}
3145
 
3146
@table @emph
3147
 
3148
@item GNU Coding Standard
3149
Code should follow the GNU coding standard for C
3150 82 jeremybenn
(@url{http://www.gnu.org/prep/standards/}.  If in doubt, put your code
3151 19 jeremybenn
through the @command{indent} program.
3152
 
3153
@item @code{#include} headers
3154
All C source code files should include @file{config.h} before any
3155
other file.
3156
 
3157
This should be followed by inclusion of any system headers (but see
3158
the comments about portability and @file{port.h} below) and then by
3159
any @value{OR1KSIM} package headers.
3160
 
3161
If @file{port.h} is required, it should be the first package header to
3162
be included after the system headers.
3163
 
3164
All C source code and header files should directly include any system
3165 82 jeremybenn
or package header they depend on, i.e.  not rely on any other header
3166
having already included it.  The two exceptions are
3167 19 jeremybenn
 
3168
@enumerate
3169
@item
3170
All header files may assume that @file{config.h} has already been
3171
included.
3172
 
3173
@item
3174
System headers which impose portability problems should be included by
3175
using the package header @file{port.h}, rather than the system headers
3176 82 jeremybenn
themselves.  This is the case for code requiring
3177 19 jeremybenn
 
3178
@itemize @bullet
3179
 
3180
@item
3181
@code{strndup} (from @file{string.h})
3182
 
3183
@item
3184
Integer types (@code{int@var{n}_t}, @code{uint@var{n}_t}) (from
3185
@file{inttypes.h}).
3186
 
3187
@item
3188
@code{isblank} (from @file{ctype.h})
3189
 
3190
@end itemize
3191
 
3192
@end enumerate
3193
 
3194
@item @code{#include} files once only
3195
All include files should be protected by @code{#ifndef} to ensure
3196 82 jeremybenn
their definitions are only included once.  For instance a header file
3197 19 jeremybenn
@file{@var{x-y.h}} should surround its contents with:
3198
 
3199
@example
3200
#ifndef X_Y__H
3201
#define X_Y__H
3202
 
3203
<body of the include file>
3204
 
3205
#endif  /* X_Y__H */
3206
@end example
3207
 
3208
@item Avoid @code{typedef}
3209
The GNU coding style for C does not have a clear way to distinguish
3210 82 jeremybenn
between user type name and user variables.  For this reason
3211 19 jeremybenn
@code{typedef} should be avoided except for the most ubiquitous user
3212 82 jeremybenn
defined types.  This makes the code much easier to read.
3213 19 jeremybenn
 
3214
There are some @code{typedef} declarations in the @command{argtable2}
3215
library and the @acronym{ELF} and @acronym{COFF} headers, because this
3216
code is taken from other places.
3217
 
3218
Within @value{OR1KSIM} legacy uses of @code{typedef} have largely been
3219
purged, except in the Custom Unit Compiler (@pxref{CUC Configuration,
3220
, Custom Unit Compiler (CUC) Configuration}).
3221
 
3222
The remaining uses of @code{typedef} occur in two places:
3223
 
3224
@itemize @bullet
3225
 
3226
@item
3227
@file{port/port.h} defines types to replace those in header files that
3228
are not available (character functions, string duplication, integer
3229
types).
3230
 
3231
@file{cpu/or1k/arch.h} defines types for the key @value{OR1KSIM}
3232
entities: addresses (@code{oraddr_t}), unsigned register values
3233
(@code{uorreg_t}) and signed register (@code{orreg_t}) values.
3234
 
3235
@end itemize
3236
 
3237
Where new types are defined, they should appear in one of these two
3238 82 jeremybenn
files as appropriate.  @value{OR1KSIM} specific types appearing in
3239 19 jeremybenn
@file{arch.h} should always have the suffix @file{_h}.
3240
 
3241
@item Don't begin names with underscore
3242
Names beginning with @code{_} are intended to be part of the C
3243 82 jeremybenn
infrastructure.  They should not be used in the simulator code.
3244 19 jeremybenn
 
3245
@item Keep Non-global top level entities static
3246
All top level entities (functions, variables), which are not
3247 82 jeremybenn
explicitly part of a global interface should be declared static.  This
3248 19 jeremybenn
ensures that unwanted connections are not inadvertently built across
3249
the program.
3250
 
3251
@item Use of @code{inline}
3252 82 jeremybenn
Code should not be declared @code{inline}.  Modern compilers can work
3253 19 jeremybenn
out for themselves what is best in this respect.
3254
 
3255
@item Initialization
3256 82 jeremybenn
All data structures should be explicitly initialized.  In particular
3257 19 jeremybenn
code should not rely on static data structures being initialized to
3258
zero.
3259
 
3260
The rationale is that in future static data structures may become
3261 82 jeremybenn
dynamic.  This has been a particular source of bugs in @value{OR1KSIM}
3262 19 jeremybenn
historically.
3263
 
3264
A specific case is with new peripherals, which should always include a
3265
@code{start} function to pre-initialize all configuration parameters
3266
to sensible defaults
3267
 
3268
@item Configuration Validation
3269
All configuration values should be validated, preferably when
3270
encountered, if not when the @code{section} is closed, or otherwise
3271
at run time when the parameter is first used.
3272
 
3273
@end table
3274
 
3275
@node Global Data Structures
3276
@section Global Data Structures
3277
 
3278
@table @code
3279
 
3280
@item config
3281
@cindex configuration global structure
3282
@vindex config
3283
The global variable @code{config} of type @code{struct config} holds
3284
the configuration data for some of the @value{OR1KSIM} components which
3285 82 jeremybenn
are always present.  At present the components are:
3286 19 jeremybenn
 
3287
@itemize @bullet
3288
 
3289
@item
3290
@vindex config.sim
3291
The simulator defined in @code{@w{section sim}} (@pxref{Simulator
3292
Configuration, , Simulator Configuration}).
3293
 
3294
@item
3295
@vindex config.vapi
3296
The Verification API (VAPI) defined  in @code{@w{section vapi}}
3297
(@pxref{Verification API Configuration, , Verification API (VAPI)
3298
Configuration}).
3299
 
3300
@item
3301
@vindex config.cuc
3302
The Custom Unit Compiler (CUC), defined in @code{@w{section cuc}}
3303
(@pxref{CUC Configuration, , Custom Unit Compiler (CUC)
3304
Configuration}).
3305
 
3306
@item
3307
@vindex config.cpu
3308
The CPU, defined in @code{@w{section cpu}} (@pxref{CPU Configuration,
3309
, CPU Configuration}).
3310
 
3311
@item
3312
@vindex config.dc
3313
The data cache (but not the instruction cache), defined in
3314
@code{@w{section dc}} (@pxref{Cache Configuration, , Cache
3315
Configuration}).
3316
 
3317
@item
3318
@vindex config.pm
3319
The power management unit, defined in @code{@w{section pm}}
3320
(@pxref{Power Management Configuration, , Power Management
3321
Configuration}).
3322
 
3323
@item
3324
@vindex config.pic
3325
The programmable interrupt controller, defined in @code{@w{section pic}}
3326
(@pxref{Interrupt Configuration, , Interrupt Configuration}).
3327
 
3328
@item
3329
@vindex config.bpb
3330
Branch prediciton, defined in @code{@w{section bpb}} (@pxref{Branch
3331
Prediction Configuration, , Branch Prediction Configuration}).
3332
 
3333
@item
3334
@vindex config.debug
3335
The debug unit, defined in @code{@w{section debug}} (@pxref{Debug
3336
Interface Configuration, , Debug Interface Configuration}).
3337
 
3338
@end itemize
3339
 
3340
This struct is made of a collection of structs, one for each
3341 82 jeremybenn
component.  For example the simulator configuration is held in
3342 19 jeremybenn
@code{config.sim}.
3343
 
3344
@item config
3345
@cindex configuration dynamic structure
3346
@vindex sections
3347
This is a linked list of data structures holding configuration data
3348
for all sections which are not held in the main @code{config} data
3349 82 jeremybenn
structure.  In general these are components (such as peripherals and
3350
memory) which may occur multiple times.  However it also handles some
3351 19 jeremybenn
architectural components which may occur only once, such as the memory
3352
management units, the instruction cache, the interrupt controller and
3353
branch prediction.
3354
 
3355
@item runtime
3356
@cindex runtime global structure
3357
@vindex runtime
3358
The global variable @code{runtime} of type @code{struct runtime} holds
3359 82 jeremybenn
all the runtime information about the simulation.  To access this
3360 19 jeremybenn
variable, @file{sim-config.h} must be included.
3361
 
3362
@vindex runtime.cpu
3363
@vindex runtime.vapi
3364
@vindex runtime.cuc
3365
This struct is itself made of 3 other structs, @code{cpu} (for CPU run
3366
time state), @code{vapi} (for Verification API state) and @code{cuc}
3367
(for Custom Unit Compiler state).
3368
 
3369
@end table
3370
 
3371
@node Concepts
3372
@section Concepts
3373
 
3374
@table @emph
3375
 
3376
@anchor{Output Redirection}
3377
@item Output Redirection
3378
@cindex output rediretion
3379
@vindex runtime.cpu.fout
3380 82 jeremybenn
The current output stream is held in @code{runtime.cpu.fout}.  Output
3381 19 jeremybenn
should be explicitly written to this stream, or may use the
3382
@code{PRINTF} macro, which will write its arguments to this output stream.
3383
 
3384
@item Reset Hooks
3385
@cindex reset hooks
3386
@findex reg_sim_reset
3387
Any peripheral may register a routine to be called when the the
3388
processor is reset by calling @code{reg_sim_reset}, providing a
3389 82 jeremybenn
function and pointer to a data structure as arguments.  On reset that
3390 19 jeremybenn
function will be called with the data stucture pointer as argument.
3391
 
3392
@end table
3393
 
3394
@node Internal Debugging
3395
@section Internal Debugging
3396
@cindex internal debugging
3397
 
3398
The function @code{debug} is like @code{printf}, but with an extra
3399 82 jeremybenn
first argument, which is the debug level.  If the debug level specified
3400 19 jeremybenn
in the simulator configuration (@pxref{Simulator Behavior, , Simulator
3401
Behavior}) is greater than or equal to this value, the remaining
3402
arguments are printed to the current output stream (@pxref{Output
3403
Redirection, , Output Redirection}).
3404
 
3405
@node  GNU Free Documentation License
3406
@chapter GNU Free Documentation License
3407
@cindex license for @value{OR1KSIM}
3408
 
3409
@include fdl-1.2.texi
3410
 
3411
@node Index
3412
 
3413
@unnumbered Index
3414
 
3415
@printindex cp
3416
 
3417
@bye

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