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1 19 jeremybenn
/* libtoplevel.c -- Top level simulator library source file
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
/* Autoconf and/or portability configuration */
28
#include "config.h"
29
 
30
/* System includes */
31
#include <stdlib.h>
32
#include <unistd.h>
33
#include <signal.h>
34
 
35
/* Package includes */
36
#include "or1ksim.h"
37
#include "sim-config.h"
38
#include "toplevel-support.h"
39 224 jeremybenn
#include "debug-unit.h"
40 19 jeremybenn
#include "sched.h"
41
#include "execute.h"
42
#include "pic.h"
43 82 jeremybenn
#include "jtag.h"
44 224 jeremybenn
#include "spr-defs.h"
45
#include "sprs.h"
46 19 jeremybenn
 
47 224 jeremybenn
 
48 143 jeremybenn
/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
49
#define MAX_GPRS    32                  /*!< Maximum GPRs */
50
#define PPC_REGNUM  (MAX_GPRS + 0)      /*!< Previous PC */
51
#define NPC_REGNUM  (MAX_GPRS + 1)      /*!< Next PC */
52
#define SR_REGNUM   (MAX_GPRS + 2)      /*!< Supervision Register */
53 19 jeremybenn
 
54 143 jeremybenn
 
55 19 jeremybenn
/*---------------------------------------------------------------------------*/
56
/*!Initialize the simulator.
57
 
58 220 jeremybenn
   The user can pass in any arguments acceptable to the standalone
59
   simulator. Not all make any sense in a library environment.
60 19 jeremybenn
 
61 220 jeremybenn
   @param[in] argc         Size of argument vector
62
   @param[in] argv         Argument vector
63 19 jeremybenn
   @param[in] class_ptr    Pointer to a C++ class instance (for use when
64
                           called by C++)
65
   @param[in] upr          Upcall routine for reads
66
   @param[in] upw          Upcall routine for writes
67
 
68
   @return  0 on success and an error code on failure                        */
69
/*---------------------------------------------------------------------------*/
70
int
71 220 jeremybenn
or1ksim_init (int         argc,
72
              char       *argv[],
73 19 jeremybenn
              void       *class_ptr,
74 93 jeremybenn
              int       (*upr) (void              *class_ptr,
75
                                unsigned long int  addr,
76
                                unsigned char      mask[],
77
                                unsigned char      rdata[],
78
                                int                data_len),
79
              int       (*upw) (void              *class_ptr,
80
                                unsigned long int  addr,
81
                                unsigned char      mask[],
82
                                unsigned char      wdata[],
83
                                int                data_len))
84 19 jeremybenn
{
85
  /* Initialization copied from existing main() */
86
  srand (getpid ());
87
  init_defconfig ();
88
  reg_config_secs ();
89
 
90 220 jeremybenn
  if (parse_args (argc, argv))
91 19 jeremybenn
    {
92
      return OR1KSIM_RC_BADINIT;
93
    }
94
 
95 143 jeremybenn
  config.sim.is_library = 1;    /* Library operation */
96
  config.sim.profile    = 0;     /* No profiling */
97
  config.sim.mprofile   = 0;
98 19 jeremybenn
 
99 143 jeremybenn
  config.ext.class_ptr  = class_ptr;    /* SystemC linkage */
100
  config.ext.read_up    = upr;
101
  config.ext.write_up   = upw;
102 19 jeremybenn
 
103
  print_config ();              /* Will go eventually */
104
  signal (SIGINT, ctrl_c);      /* Not sure we want this really */
105
 
106
  runtime.sim.hush = 1;         /* Not sure if this is needed */
107
  do_stats = config.cpu.superscalar ||
108
             config.cpu.dependstats ||
109
             config.sim.history     ||
110
             config.sim.exe_log;
111
 
112
  sim_init ();
113
 
114
  runtime.sim.ext_int_set = 0;   /* No interrupts pending to be set */
115
  runtime.sim.ext_int_clr = 0;   /* No interrupts pending to be cleared */
116
 
117
  return OR1KSIM_RC_OK;
118
 
119 143 jeremybenn
}       /* or1ksim_init () */
120 19 jeremybenn
 
121
 
122
/*---------------------------------------------------------------------------*/
123
/*!Run the simulator
124
 
125
   The argument is a time in seconds, which is converted to a number of
126
   cycles, if positive. A negative value means "run for ever".
127
 
128 97 jeremybenn
   With the JTAG interface, it is possible to stall the processor between
129
   calls of this function (but not during upcalls). In which case we return
130
   immediately.
131
 
132
   @todo Is it possible (or desirable) to permit JTAG activity during upcalls,
133
         in which case we could stall mid-run.
134
 
135
   @todo Should the JTAG functionality require enabling?
136
 
137 19 jeremybenn
   The semantics are that the duration for which the run may occur may be
138
   changed mid-run by a call to or1ksim_reset_duration(). This is to allow for
139
   the upcalls to generic components adding time, and reducing the time
140
   permitted for ISS execution before synchronization of the parent SystemC
141
   wrapper.
142
 
143
   This is over-ridden if the call was for a negative duration, which means
144
   run forever!
145
 
146
   Uses a simplified version of the old main program loop. Returns success if
147
   the requested number of cycles were run and an error code otherwise.
148
 
149
   @param[in] duration  Time to execute for (seconds)
150
 
151
   @return  OR1KSIM_RC_OK if we run to completion, OR1KSIM_RC_BRKPT if we hit
152
            a breakpoint (not clear how this can be set without CLI access)  */
153
/*---------------------------------------------------------------------------*/
154
int
155
or1ksim_run (double duration)
156
{
157
  const int  num_ints = sizeof (runtime.sim.ext_int_set) * 8;
158
 
159 97 jeremybenn
  /* If we are stalled we can't do anything. We treat this as hitting a
160 143 jeremybenn
     breakpoint or halting. */
161 97 jeremybenn
  if(runtime.cpu.stalled)
162
    {
163 143 jeremybenn
      return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
164 97 jeremybenn
    }
165
 
166
  /* Reset the duration */
167 19 jeremybenn
  or1ksim_reset_duration (duration);
168
 
169
  /* Loop until we have done enough cycles (or forever if we had a negative
170
     duration) */
171
  while (duration < 0.0 || (runtime.sim.cycles < runtime.sim.end_cycles))
172
    {
173
      long long int time_start = runtime.sim.cycles;
174
      int i;                    /* Interrupt # */
175
 
176
      /* Each cycle has counter of mem_cycles; this value is joined with cycles
177
       * at the end of the cycle; no sim originated memory accesses should be
178 82 jeremybenn
       * performed in between. */
179 19 jeremybenn
      runtime.sim.mem_cycles = 0;
180
 
181
      if (cpu_clock ())
182
        {
183 143 jeremybenn
          /* This is probably wrong. This is an Or1ksim breakpoint, not a GNU
184
             one. */
185
          return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
186 19 jeremybenn
        }
187
 
188 236 jeremybenn
      /* If we were single stepping, stall immediately. */
189
      if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST)
190
        {
191
          set_stall_state (1);
192
        }
193
 
194 143 jeremybenn
      /* If we are stalled we can't do anything. We treat this as hitting a
195
         breakpoint or halting. */
196
      if(runtime.cpu.stalled)
197
        {
198
          return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
199
        }
200
 
201 19 jeremybenn
      runtime.sim.cycles += runtime.sim.mem_cycles;
202
 
203
      /* Take any external interrupts. Outer test is for the common case for
204
         efficiency. */
205
      if (0 != runtime.sim.ext_int_set)
206
        {
207
          for (i = 0; i < num_ints; i++)
208
            {
209
              if (0x1 == ((runtime.sim.ext_int_set >> i) & 0x1))
210
                {
211
                  report_interrupt (i);
212
                  runtime.sim.ext_int_set &= ~(1 << i); /* Clear req flag */
213
                }
214
            }
215
        }
216
 
217
      /* Clear any interrupts as requested. For edge triggered interrupts this
218
         will happen in the same cycle. For level triggered, it must be an
219
         explicit call. */
220
      if (0 != runtime.sim.ext_int_clr)
221
        {
222
          for (i = 0; i < num_ints; i++)
223
            {
224
              /* Only clear interrupts that have been explicitly cleared */
225
              if(0x1 == ((runtime.sim.ext_int_clr >> i) & 0x1))
226
                {
227
                  clear_interrupt(i);
228
                  runtime.sim.ext_int_clr &= ~(1 << i); /* Clear clr flag */
229
                }
230
            }
231
        }
232
 
233
      /* Update the scheduler queue */
234
      scheduler.job_queue->time -= (runtime.sim.cycles - time_start);
235
 
236
      if (scheduler.job_queue->time <= 0)
237
        {
238
          do_scheduler ();
239
        }
240
    }
241
 
242
  return  OR1KSIM_RC_OK;
243
 
244 143 jeremybenn
}       /* or1ksim_run () */
245 19 jeremybenn
 
246
 
247
/*---------------------------------------------------------------------------*/
248
/*!Reset the run-time simulation end point
249
 
250
  Reset the time for which the simulation should run to the specified duration
251
  from NOW (i.e. NOT from when the run started).
252
 
253
  @param[in] duration  Time to run for in seconds                            */
254
/*---------------------------------------------------------------------------*/
255
void
256
or1ksim_reset_duration (double duration)
257
{
258
  runtime.sim.end_cycles =
259
    runtime.sim.cycles +
260
    (long long int) (duration * 1.0e12 / (double) config.sim.clkcycle_ps);
261
 
262 143 jeremybenn
}       /* or1ksim_reset_duration () */
263 19 jeremybenn
 
264
 
265
/*---------------------------------------------------------------------------*/
266
/*!Return time executed so far
267
 
268
   Internal utility to return the time executed so far. Note that this is a
269
   re-entrant routine.
270
 
271
   @return  Time executed so far in seconds                                  */
272
/*---------------------------------------------------------------------------*/
273
static double
274
internal_or1ksim_time ()
275
{
276
  return (double) runtime.sim.cycles * (double) config.sim.clkcycle_ps /
277
    1.0e12;
278
 
279
}       // or1ksim_cycle_count()
280
 
281
 
282
/*---------------------------------------------------------------------------*/
283
/*!Mark a time point in the simulation
284
 
285
   Sets the internal parameter recording this point in the simulation        */
286
/*---------------------------------------------------------------------------*/
287
void
288
or1ksim_set_time_point ()
289
{
290
  runtime.sim.time_point = internal_or1ksim_time ();
291
 
292 143 jeremybenn
}       /* or1ksim_set_time_point () */
293 19 jeremybenn
 
294
 
295
/*---------------------------------------------------------------------------*/
296
/*!Return the time since the time point was set
297
 
298
  Get the value from the internal parameter                                  */
299
/*---------------------------------------------------------------------------*/
300
double
301
or1ksim_get_time_period ()
302
{
303
  return internal_or1ksim_time () - runtime.sim.time_point;
304
 
305 143 jeremybenn
}       /* or1ksim_get_time_period () */
306 19 jeremybenn
 
307
 
308
/*---------------------------------------------------------------------------*/
309
/*!Return the endianism of the model
310
 
311
   Note that this is a re-entrant routine.
312
 
313
   @return 1 if the model is little endian, 0 otherwise.                     */
314
/*---------------------------------------------------------------------------*/
315
int
316
or1ksim_is_le ()
317
{
318
#ifdef OR32_BIG_ENDIAN
319
  return 0;
320
#else
321
  return 1;
322
#endif
323
 
324 143 jeremybenn
}       /* or1ksim_is_le () */
325 19 jeremybenn
 
326
 
327
/*---------------------------------------------------------------------------*/
328
/*!Return the clock rate
329
 
330
   Value is part of the configuration
331
 
332
   @return  Clock rate in Hz.                                                */
333
/*---------------------------------------------------------------------------*/
334
unsigned long int
335
or1ksim_clock_rate ()
336
{
337
  return (unsigned long int) (1000000000000ULL /
338
                              (unsigned long long int) (config.sim.
339
                                                        clkcycle_ps));
340 143 jeremybenn
}       /* or1ksim_clock_rate () */
341 19 jeremybenn
 
342
 
343
/*---------------------------------------------------------------------------*/
344
/*!Trigger an edge triggered interrupt
345
 
346
   This function is appropriate for edge triggered interrupts, which are taken
347
   and then immediately cleared.
348
 
349
   @note There is no check that the specified interrupt number is reasonable
350
   (i.e. <= 31).
351
 
352
   @param[in] i  The interrupt number                                        */
353
/*---------------------------------------------------------------------------*/
354
void
355
or1ksim_interrupt (int i)
356
{
357
  if (!config.pic.edge_trigger)
358
    {
359
      fprintf (stderr, "Warning: or1ksim_interrupt should not be used for "
360 93 jeremybenn
               "level triggered interrupts. Ignored\n");
361 19 jeremybenn
    }
362
  else
363
    {
364
      runtime.sim.ext_int_set |= 1 << i;        // Better not be > 31!
365
      runtime.sim.ext_int_clr |= 1 << i;        // Better not be > 31!
366
    }
367 143 jeremybenn
}       /* or1ksim_interrupt () */
368 19 jeremybenn
 
369
 
370
/*---------------------------------------------------------------------------*/
371
/*!Set a level triggered interrupt
372
 
373
   This function is appropriate for level triggered interrupts, which must be
374
   explicitly cleared in a separate call.
375
 
376
   @note There is no check that the specified interrupt number is reasonable
377
   (i.e. <= 31).
378
 
379
   @param[in] i  The interrupt number to set                                 */
380
/*---------------------------------------------------------------------------*/
381
void
382
or1ksim_interrupt_set (int i)
383
{
384
  if (config.pic.edge_trigger)
385
    {
386
      fprintf (stderr, "Warning: or1ksim_interrupt_set should not be used for "
387 93 jeremybenn
               "edge triggered interrupts. Ignored\n");
388 19 jeremybenn
    }
389
  else
390
    {
391
      runtime.sim.ext_int_set |= 1 << i;        // Better not be > 31!
392
    }
393 143 jeremybenn
}       /* or1ksim_interrupt () */
394 19 jeremybenn
 
395
 
396
/*---------------------------------------------------------------------------*/
397
/*!Clear a level triggered interrupt
398
 
399
   This function is appropriate for level triggered interrupts, which must be
400
   explicitly set first in a separate call.
401
 
402
   @note There is no check that the specified interrupt number is reasonable
403
   (i.e. <= 31).
404
 
405
   @param[in] i  The interrupt number to clear                               */
406
/*---------------------------------------------------------------------------*/
407
void
408
or1ksim_interrupt_clear (int i)
409
{
410
  if (config.pic.edge_trigger)
411
    {
412
      fprintf (stderr, "Warning: or1ksim_interrupt_clear should not be used "
413 93 jeremybenn
               "for edge triggered interrupts. Ignored\n");
414 19 jeremybenn
    }
415
  else
416
    {
417
      runtime.sim.ext_int_clr |= 1 << i;        // Better not be > 31!
418
    }
419 143 jeremybenn
}       /* or1ksim_interrupt () */
420 82 jeremybenn
 
421
 
422
/*---------------------------------------------------------------------------*/
423
/*!Reset the JTAG interface
424
 
425
   @note Like all the JTAG interface functions, this must not be called
426
         re-entrantly while a call to any other function (e.g. or1kim_run ())
427
         is in progress. It is the responsibility of the caller to ensure this
428
         constraint is met, for example by use of a SystemC mutex.
429
 
430
   @return  The time in seconds which the reset took.                        */
431
/*---------------------------------------------------------------------------*/
432
double
433
or1ksim_jtag_reset ()
434
{
435 98 jeremybenn
  /* Number of JTAG clock cycles a reset sequence takes */
436
  const double  JTAG_RESET_CYCLES = 5.0;
437 82 jeremybenn
 
438 98 jeremybenn
  jtag_reset ();
439
 
440
  return  JTAG_RESET_CYCLES  * (double) config.debug.jtagcycle_ps / 1.0e12;
441
 
442 82 jeremybenn
}       /* or1ksim_jtag_reset () */
443
 
444
 
445
/*---------------------------------------------------------------------------*/
446
/*!Shift a JTAG instruction register
447
 
448
   @note Like all the JTAG interface functions, this must not be called
449
         re-entrantly while a call to any other function (e.g. or1kim_run ())
450
         is in progress. It is the responsibility of the caller to ensure this
451
         constraint is met, for example by use of a SystemC mutex.
452
 
453
   The register is represented as a vector of bytes, with the byte at offset
454
   zero being shifted first, and the least significant bit in each byte being
455
   shifted first. Where the register will not fit in an exact number of bytes,
456
   the odd bits are in the highest numbered byte, shifted to the low end.
457
 
458
   The only JTAG instruction for which we have any significant behavior in
459
   this model is DEBUG. For completeness the register is parsed and a warning
460
   given if any register other than DEBUG is shifted.
461
 
462 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
463
                            back out.
464
   @param[in]     num_bits  The number of bits in the register. Just for
465
                            sanity check (it should always be 4).
466 82 jeremybenn
 
467
   @return  The time in seconds which the shift took.                        */
468
/*---------------------------------------------------------------------------*/
469
double
470 98 jeremybenn
or1ksim_jtag_shift_ir (unsigned char *jreg,
471
                       int            num_bits)
472 82 jeremybenn
{
473 98 jeremybenn
  jtag_shift_ir (jreg, num_bits);
474 82 jeremybenn
 
475 98 jeremybenn
  return  (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
476
 
477 82 jeremybenn
}       /* or1ksim_jtag_shift_ir () */
478
 
479
 
480
/*---------------------------------------------------------------------------*/
481
/*!Shift a JTAG data register
482
 
483
   @note Like all the JTAG interface functions, this must not be called
484
         re-entrantly while a call to any other function (e.g. or1kim_run ())
485
         is in progress. It is the responsibility of the caller to ensure this
486
         constraint is met, for example by use of a SystemC mutex.
487
 
488
   The register is represented as a vector of bytes, with the byte at offset
489
   zero being shifted first, and the least significant bit in each byte being
490
   shifted first. Where the register will not fit in an exact number of bytes,
491
   the odd bits are in the highest numbered byte, shifted to the low end.
492
 
493
   The register is parsed to determine which of the six possible register
494
   types it could be.
495
   - MODULE_SELECT
496
   - WRITE_COMMNAND
497
   - READ_COMMAND
498
   - GO_COMMAND
499
   - WRITE_CONTROL
500
   - READ_CONTROL
501
 
502
   @note In practice READ_COMMAND is not used. However the functionality is
503
         provided for future compatibility.
504
 
505 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
506
                            back out.
507
   @param[in]     num_bits  The number of bits in the register. This is
508
                            essential to prevent bugs where the size of
509
                            register supplied is incorrect.
510 82 jeremybenn
 
511
   @return  The time in seconds which the shift took.                        */
512
/*---------------------------------------------------------------------------*/
513
double
514 98 jeremybenn
or1ksim_jtag_shift_dr (unsigned char *jreg,
515
                       int            num_bits)
516 82 jeremybenn
{
517 98 jeremybenn
  jtag_shift_dr (jreg, num_bits);
518 82 jeremybenn
 
519 98 jeremybenn
  return  (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
520
 
521 82 jeremybenn
}       /* or1ksim_jtag_shift_dr () */
522 143 jeremybenn
 
523
 
524
/*---------------------------------------------------------------------------*/
525
/*!Read a block of memory.
526
 
527 224 jeremybenn
   @param[in]  addr  The address to read from.
528 143 jeremybenn
   @param[out] buf   Where to put the data.
529
   @param[in]  len   The number of bytes to read.
530
 
531
   @return  Number of bytes read, or zero if error.                          */
532
/*---------------------------------------------------------------------------*/
533
int
534 230 jeremybenn
or1ksim_read_mem (unsigned long int  addr,
535
                  unsigned char     *buf,
536
                  int                len)
537 143 jeremybenn
{
538
  int             off;                  /* Offset into the memory */
539
 
540
  /* Fill the buffer with data */
541
  for (off = 0; off < len; off++)
542
    {
543
      /* Check memory area is valid */
544
      if (NULL == verify_memoryarea (addr + off))
545
        {
546
          /* Fail silently - others can raise any error message. */
547
          return  0;
548
        }
549
      else
550
        {
551
          /* Get the memory direct - no translation. */
552
          buf[off] = eval_direct8 (addr + off, 0, 0);
553
        }
554
    }
555
 
556
  return  len;
557
 
558
}       /* or1ksim_read_mem () */
559
 
560
 
561
/*---------------------------------------------------------------------------*/
562
/*!Write a block of memory.
563
 
564 224 jeremybenn
   @param[in] addr  The address to write to.
565 143 jeremybenn
   @param[in] buf   Where to get the data from.
566
   @param[in] len   The number of bytes to write.
567
 
568
   @return  Number of bytes written, or zero if error.                       */
569
/*---------------------------------------------------------------------------*/
570
int
571 230 jeremybenn
or1ksim_write_mem (unsigned long int  addr,
572
                   unsigned char     *buf,
573
                   int                len)
574 143 jeremybenn
{
575
  int             off;                  /* Offset into the memory */
576
 
577
  /* Write the bytes to memory */
578
  for (off = 0; off < len; off++)
579
    {
580
      if (NULL == verify_memoryarea (addr + off))
581
        {
582
          /* Fail silently - others can raise any error message. */
583
          return  0;
584
        }
585
      else
586
        {
587
          /* circumvent the read-only check usually done for mem accesses data
588
             is in host order, because that's what set_direct32 needs */
589
          set_program8 (addr + off, buf[off]);
590
        }
591
    }
592
 
593
  return  len;
594
 
595
}       /* or1ksim_write_mem () */
596
 
597
 
598
/*---------------------------------------------------------------------------*/
599 224 jeremybenn
/*!Read a SPR
600 143 jeremybenn
 
601 224 jeremybenn
   @param[in]  sprnum      The SPR to read.
602
   @param[out] sprval_ptr  Where to put the data.
603 143 jeremybenn
 
604 224 jeremybenn
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
605 143 jeremybenn
/*---------------------------------------------------------------------------*/
606
int
607 230 jeremybenn
or1ksim_read_spr (int                sprnum,
608
                  unsigned long int *sprval_ptr)
609 143 jeremybenn
{
610 224 jeremybenn
  /* SPR numbers are up to 16 bits long */
611
  if ((unsigned int) sprnum <= 0xffff)
612 143 jeremybenn
    {
613 224 jeremybenn
      *sprval_ptr = (unsigned int) mfspr ((uint16_t) sprnum);
614
      return  1;
615 143 jeremybenn
    }
616 224 jeremybenn
  else
617 143 jeremybenn
    {
618 224 jeremybenn
      return  0;                 /* Silent failure */
619 143 jeremybenn
    }
620 224 jeremybenn
}       /* or1skim_read_spr () */
621
 
622
 
623
/*---------------------------------------------------------------------------*/
624
/*!Write a SPR
625
 
626
   @param[in] sprnum  The SPR to write.
627
   @param[in] sprval  The data to write.
628
 
629
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
630
/*---------------------------------------------------------------------------*/
631
int
632 230 jeremybenn
or1ksim_write_spr (int                sprnum,
633
                   unsigned long int  sprval)
634 224 jeremybenn
{
635
  /* SPR numbers are up to 16 bits long */
636
  if ((unsigned int) sprnum <= 0xffff)
637 143 jeremybenn
    {
638 224 jeremybenn
      mtspr ((uint16_t) sprnum, sprval);
639
      return  1;
640 143 jeremybenn
    }
641 224 jeremybenn
  else
642 143 jeremybenn
    {
643 224 jeremybenn
      return  0;                 /* Silent failure */
644 143 jeremybenn
    }
645 224 jeremybenn
}       /* or1ksim_write_spr () */
646
 
647
 
648
/*---------------------------------------------------------------------------*/
649
/*!Read a single register
650
 
651
   The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
652
   (i.e. SPR NPC) and SR (i.e. SPR SR).
653
 
654
   Map to the corresponding SPR.
655
 
656
   @param[in]  regnum      The register to read.
657
   @param[out] regval_ptr  Where to put the data.
658
 
659
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
660
/*---------------------------------------------------------------------------*/
661
int
662 230 jeremybenn
or1ksim_read_reg (int                 regnum,
663
                  unsigned long int  *regval_ptr)
664 224 jeremybenn
{
665
  /* GPR's */
666
  if (regnum < MAX_GPRS)
667 143 jeremybenn
    {
668 224 jeremybenn
      return or1ksim_read_spr (regnum + SPR_GPR_BASE, regval_ptr);
669 143 jeremybenn
    }
670 224 jeremybenn
 
671
  /* SPR's or unknown */
672
  switch (regnum)
673 143 jeremybenn
    {
674 224 jeremybenn
    case PPC_REGNUM: return or1ksim_read_spr (SPR_PPC, regval_ptr);
675
    case NPC_REGNUM: return or1ksim_read_spr (SPR_NPC, regval_ptr);
676
    case SR_REGNUM:  return or1ksim_read_spr (SPR_SR, regval_ptr);
677
    default:
678 143 jeremybenn
      /* Silent error response if we don't know the register */
679
      return  0;
680
    }
681
}       /* or1ksim_read_reg () */
682
 
683
 
684
/*---------------------------------------------------------------------------*/
685
/*!Write a single register
686
 
687
   The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
688 224 jeremybenn
   (i.e. SPR NPC) and SR (i.e. SPR SR).
689 143 jeremybenn
 
690 224 jeremybenn
   Map to the corresponding SPR
691 143 jeremybenn
 
692 224 jeremybenn
   @param[in] regval  The register to write.
693 143 jeremybenn
   @param[in] regnum  The register to write.
694
 
695 224 jeremybenn
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
696 143 jeremybenn
/*---------------------------------------------------------------------------*/
697
int
698 230 jeremybenn
or1ksim_write_reg (int                regnum,
699
                   unsigned long int  regval)
700 143 jeremybenn
{
701 224 jeremybenn
  /* GPR's */
702
  if (regnum < MAX_GPRS)
703 143 jeremybenn
    {
704 224 jeremybenn
      return or1ksim_write_spr (regnum + SPR_GPR_BASE, regval);
705 143 jeremybenn
    }
706
 
707 224 jeremybenn
  /* SPR's or unknown */
708
  switch (regnum)
709 143 jeremybenn
    {
710 224 jeremybenn
    case PPC_REGNUM: return or1ksim_write_spr (SPR_PPC, regval);
711
    case NPC_REGNUM: return or1ksim_write_spr (SPR_NPC, regval);
712
    case SR_REGNUM:  return or1ksim_write_spr (SPR_SR,  regval);
713
    default:
714 143 jeremybenn
      /* Silent error response if we don't know the register */
715
      return  0;
716
    }
717 224 jeremybenn
}       /* or1ksim_write_reg () */
718 143 jeremybenn
 
719 224 jeremybenn
 
720
/*---------------------------------------------------------------------------*/
721
/*!Set the simulator stall state.
722 143 jeremybenn
 
723 224 jeremybenn
   @param[in] state  The stall state to set.                                 */
724
/*---------------------------------------------------------------------------*/
725
void
726
or1ksim_set_stall_state (int  state)
727
{
728
  set_stall_state (state ? 1 : 0);
729 143 jeremybenn
 
730 224 jeremybenn
}       /* or1ksim_set_stall_state () */

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