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[/] [openrisc/] [trunk/] [or1ksim/] [libtoplevel.c] - Blame information for rev 734

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1 19 jeremybenn
/* libtoplevel.c -- Top level simulator library source file
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
/* Autoconf and/or portability configuration */
28
#include "config.h"
29
 
30
/* System includes */
31
#include <stdlib.h>
32
#include <unistd.h>
33
#include <signal.h>
34
 
35
/* Package includes */
36
#include "or1ksim.h"
37
#include "sim-config.h"
38
#include "toplevel-support.h"
39 224 jeremybenn
#include "debug-unit.h"
40 19 jeremybenn
#include "sched.h"
41
#include "execute.h"
42
#include "pic.h"
43 82 jeremybenn
#include "jtag.h"
44 224 jeremybenn
#include "spr-defs.h"
45
#include "sprs.h"
46 19 jeremybenn
 
47 224 jeremybenn
 
48 143 jeremybenn
/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
49
#define MAX_GPRS    32                  /*!< Maximum GPRs */
50
#define PPC_REGNUM  (MAX_GPRS + 0)      /*!< Previous PC */
51
#define NPC_REGNUM  (MAX_GPRS + 1)      /*!< Next PC */
52
#define SR_REGNUM   (MAX_GPRS + 2)      /*!< Supervision Register */
53 19 jeremybenn
 
54 143 jeremybenn
 
55 19 jeremybenn
/*---------------------------------------------------------------------------*/
56
/*!Initialize the simulator.
57
 
58 220 jeremybenn
   The user can pass in any arguments acceptable to the standalone
59
   simulator. Not all make any sense in a library environment.
60 19 jeremybenn
 
61 220 jeremybenn
   @param[in] argc         Size of argument vector
62
   @param[in] argv         Argument vector
63 19 jeremybenn
   @param[in] class_ptr    Pointer to a C++ class instance (for use when
64
                           called by C++)
65
   @param[in] upr          Upcall routine for reads
66
   @param[in] upw          Upcall routine for writes
67
 
68
   @return  0 on success and an error code on failure                        */
69
/*---------------------------------------------------------------------------*/
70
int
71 220 jeremybenn
or1ksim_init (int         argc,
72
              char       *argv[],
73 19 jeremybenn
              void       *class_ptr,
74 93 jeremybenn
              int       (*upr) (void              *class_ptr,
75
                                unsigned long int  addr,
76
                                unsigned char      mask[],
77
                                unsigned char      rdata[],
78
                                int                data_len),
79
              int       (*upw) (void              *class_ptr,
80
                                unsigned long int  addr,
81
                                unsigned char      mask[],
82
                                unsigned char      wdata[],
83
                                int                data_len))
84 19 jeremybenn
{
85
  /* Initialization copied from existing main() */
86 483 jeremybenn
  init_randomness ();
87 19 jeremybenn
  init_defconfig ();
88
  reg_config_secs ();
89
 
90 220 jeremybenn
  if (parse_args (argc, argv))
91 19 jeremybenn
    {
92
      return OR1KSIM_RC_BADINIT;
93
    }
94
 
95 143 jeremybenn
  config.sim.is_library = 1;    /* Library operation */
96
  config.sim.profile    = 0;     /* No profiling */
97
  config.sim.mprofile   = 0;
98 19 jeremybenn
 
99 143 jeremybenn
  config.ext.class_ptr  = class_ptr;    /* SystemC linkage */
100
  config.ext.read_up    = upr;
101
  config.ext.write_up   = upw;
102 19 jeremybenn
 
103
  print_config ();              /* Will go eventually */
104
  signal (SIGINT, ctrl_c);      /* Not sure we want this really */
105
 
106
  do_stats = config.cpu.superscalar ||
107
             config.cpu.dependstats ||
108
             config.sim.history     ||
109
             config.sim.exe_log;
110
 
111
  sim_init ();
112
 
113
  runtime.sim.ext_int_set = 0;   /* No interrupts pending to be set */
114
  runtime.sim.ext_int_clr = 0;   /* No interrupts pending to be cleared */
115
 
116
  return OR1KSIM_RC_OK;
117
 
118 143 jeremybenn
}       /* or1ksim_init () */
119 19 jeremybenn
 
120
 
121
/*---------------------------------------------------------------------------*/
122
/*!Run the simulator
123
 
124
   The argument is a time in seconds, which is converted to a number of
125
   cycles, if positive. A negative value means "run for ever".
126
 
127 97 jeremybenn
   With the JTAG interface, it is possible to stall the processor between
128
   calls of this function (but not during upcalls). In which case we return
129
   immediately.
130
 
131
   @todo Is it possible (or desirable) to permit JTAG activity during upcalls,
132
         in which case we could stall mid-run.
133
 
134
   @todo Should the JTAG functionality require enabling?
135
 
136 19 jeremybenn
   The semantics are that the duration for which the run may occur may be
137
   changed mid-run by a call to or1ksim_reset_duration(). This is to allow for
138
   the upcalls to generic components adding time, and reducing the time
139
   permitted for ISS execution before synchronization of the parent SystemC
140
   wrapper.
141
 
142
   This is over-ridden if the call was for a negative duration, which means
143
   run forever!
144
 
145
   Uses a simplified version of the old main program loop. Returns success if
146
   the requested number of cycles were run and an error code otherwise.
147
 
148
   @param[in] duration  Time to execute for (seconds)
149
 
150
   @return  OR1KSIM_RC_OK if we run to completion, OR1KSIM_RC_BRKPT if we hit
151
            a breakpoint (not clear how this can be set without CLI access)  */
152
/*---------------------------------------------------------------------------*/
153
int
154
or1ksim_run (double duration)
155
{
156
  const int  num_ints = sizeof (runtime.sim.ext_int_set) * 8;
157
 
158 97 jeremybenn
  /* If we are stalled we can't do anything. We treat this as hitting a
159 143 jeremybenn
     breakpoint or halting. */
160 97 jeremybenn
  if(runtime.cpu.stalled)
161
    {
162 143 jeremybenn
      return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
163 97 jeremybenn
    }
164
 
165
  /* Reset the duration */
166 19 jeremybenn
  or1ksim_reset_duration (duration);
167
 
168
  /* Loop until we have done enough cycles (or forever if we had a negative
169
     duration) */
170
  while (duration < 0.0 || (runtime.sim.cycles < runtime.sim.end_cycles))
171
    {
172
      long long int time_start = runtime.sim.cycles;
173
      int i;                    /* Interrupt # */
174
 
175
      /* Each cycle has counter of mem_cycles; this value is joined with cycles
176
       * at the end of the cycle; no sim originated memory accesses should be
177 82 jeremybenn
       * performed in between. */
178 19 jeremybenn
      runtime.sim.mem_cycles = 0;
179
 
180
      if (cpu_clock ())
181
        {
182 143 jeremybenn
          /* This is probably wrong. This is an Or1ksim breakpoint, not a GNU
183
             one. */
184
          return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
185 19 jeremybenn
        }
186
 
187 385 jeremybenn
      /* If we are tracing, dump after each instruction. */
188
      if (!runtime.sim.hush)
189
        {
190 420 jeremybenn
          trace_instr ();
191 385 jeremybenn
        }
192
 
193 236 jeremybenn
      /* If we were single stepping, stall immediately. */
194
      if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST)
195
        {
196
          set_stall_state (1);
197
        }
198
 
199 143 jeremybenn
      /* If we are stalled we can't do anything. We treat this as hitting a
200
         breakpoint or halting. */
201
      if(runtime.cpu.stalled)
202
        {
203
          return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
204
        }
205
 
206 19 jeremybenn
      runtime.sim.cycles += runtime.sim.mem_cycles;
207
 
208
      /* Take any external interrupts. Outer test is for the common case for
209
         efficiency. */
210
      if (0 != runtime.sim.ext_int_set)
211
        {
212
          for (i = 0; i < num_ints; i++)
213
            {
214
              if (0x1 == ((runtime.sim.ext_int_set >> i) & 0x1))
215
                {
216
                  report_interrupt (i);
217
                  runtime.sim.ext_int_set &= ~(1 << i); /* Clear req flag */
218
                }
219
            }
220
        }
221
 
222 432 jeremybenn
      /* Clear any interrupts as requested. This only applies to level
223
         sensitive interrupts. Edge triggered are cleared by writing to
224
         PICSR. */
225 19 jeremybenn
      if (0 != runtime.sim.ext_int_clr)
226
        {
227
          for (i = 0; i < num_ints; i++)
228
            {
229
              /* Only clear interrupts that have been explicitly cleared */
230
              if(0x1 == ((runtime.sim.ext_int_clr >> i) & 0x1))
231
                {
232
                  clear_interrupt(i);
233
                  runtime.sim.ext_int_clr &= ~(1 << i); /* Clear clr flag */
234
                }
235
            }
236
        }
237
 
238
      /* Update the scheduler queue */
239
      scheduler.job_queue->time -= (runtime.sim.cycles - time_start);
240
 
241
      if (scheduler.job_queue->time <= 0)
242
        {
243
          do_scheduler ();
244
        }
245
    }
246
 
247
  return  OR1KSIM_RC_OK;
248
 
249 143 jeremybenn
}       /* or1ksim_run () */
250 19 jeremybenn
 
251
 
252
/*---------------------------------------------------------------------------*/
253
/*!Reset the run-time simulation end point
254
 
255
  Reset the time for which the simulation should run to the specified duration
256
  from NOW (i.e. NOT from when the run started).
257
 
258
  @param[in] duration  Time to run for in seconds                            */
259
/*---------------------------------------------------------------------------*/
260
void
261
or1ksim_reset_duration (double duration)
262
{
263
  runtime.sim.end_cycles =
264
    runtime.sim.cycles +
265
    (long long int) (duration * 1.0e12 / (double) config.sim.clkcycle_ps);
266
 
267 143 jeremybenn
}       /* or1ksim_reset_duration () */
268 19 jeremybenn
 
269
 
270
/*---------------------------------------------------------------------------*/
271
/*!Return time executed so far
272
 
273
   Internal utility to return the time executed so far. Note that this is a
274
   re-entrant routine.
275
 
276
   @return  Time executed so far in seconds                                  */
277
/*---------------------------------------------------------------------------*/
278
static double
279
internal_or1ksim_time ()
280
{
281
  return (double) runtime.sim.cycles * (double) config.sim.clkcycle_ps /
282
    1.0e12;
283
 
284
}       // or1ksim_cycle_count()
285
 
286
 
287
/*---------------------------------------------------------------------------*/
288
/*!Mark a time point in the simulation
289
 
290
   Sets the internal parameter recording this point in the simulation        */
291
/*---------------------------------------------------------------------------*/
292
void
293
or1ksim_set_time_point ()
294
{
295
  runtime.sim.time_point = internal_or1ksim_time ();
296
 
297 143 jeremybenn
}       /* or1ksim_set_time_point () */
298 19 jeremybenn
 
299
 
300
/*---------------------------------------------------------------------------*/
301
/*!Return the time since the time point was set
302
 
303
  Get the value from the internal parameter                                  */
304
/*---------------------------------------------------------------------------*/
305
double
306
or1ksim_get_time_period ()
307
{
308
  return internal_or1ksim_time () - runtime.sim.time_point;
309
 
310 143 jeremybenn
}       /* or1ksim_get_time_period () */
311 19 jeremybenn
 
312
 
313
/*---------------------------------------------------------------------------*/
314
/*!Return the endianism of the model
315
 
316
   Note that this is a re-entrant routine.
317
 
318
   @return 1 if the model is little endian, 0 otherwise.                     */
319
/*---------------------------------------------------------------------------*/
320
int
321
or1ksim_is_le ()
322
{
323
#ifdef OR32_BIG_ENDIAN
324
  return 0;
325
#else
326
  return 1;
327
#endif
328
 
329 143 jeremybenn
}       /* or1ksim_is_le () */
330 19 jeremybenn
 
331
 
332
/*---------------------------------------------------------------------------*/
333
/*!Return the clock rate
334
 
335
   Value is part of the configuration
336
 
337
   @return  Clock rate in Hz.                                                */
338
/*---------------------------------------------------------------------------*/
339
unsigned long int
340
or1ksim_clock_rate ()
341
{
342
  return (unsigned long int) (1000000000000ULL /
343
                              (unsigned long long int) (config.sim.
344
                                                        clkcycle_ps));
345 143 jeremybenn
}       /* or1ksim_clock_rate () */
346 19 jeremybenn
 
347
 
348
/*---------------------------------------------------------------------------*/
349
/*!Trigger an edge triggered interrupt
350
 
351 432 jeremybenn
   This function is appropriate for edge triggered interrupts. These are
352
   cleared by writing to the PICSR SPR.
353 19 jeremybenn
 
354
   @note There is no check that the specified interrupt number is reasonable
355
   (i.e. <= 31).
356
 
357
   @param[in] i  The interrupt number                                        */
358
/*---------------------------------------------------------------------------*/
359
void
360
or1ksim_interrupt (int i)
361
{
362
  if (!config.pic.edge_trigger)
363
    {
364
      fprintf (stderr, "Warning: or1ksim_interrupt should not be used for "
365 93 jeremybenn
               "level triggered interrupts. Ignored\n");
366 19 jeremybenn
    }
367
  else
368
    {
369
      runtime.sim.ext_int_set |= 1 << i;        // Better not be > 31!
370
    }
371 143 jeremybenn
}       /* or1ksim_interrupt () */
372 19 jeremybenn
 
373
 
374
/*---------------------------------------------------------------------------*/
375
/*!Set a level triggered interrupt
376
 
377
   This function is appropriate for level triggered interrupts, which must be
378
   explicitly cleared in a separate call.
379
 
380
   @note There is no check that the specified interrupt number is reasonable
381
   (i.e. <= 31).
382
 
383
   @param[in] i  The interrupt number to set                                 */
384
/*---------------------------------------------------------------------------*/
385
void
386
or1ksim_interrupt_set (int i)
387
{
388
  if (config.pic.edge_trigger)
389
    {
390
      fprintf (stderr, "Warning: or1ksim_interrupt_set should not be used for "
391 93 jeremybenn
               "edge triggered interrupts. Ignored\n");
392 19 jeremybenn
    }
393
  else
394
    {
395
      runtime.sim.ext_int_set |= 1 << i;        // Better not be > 31!
396
    }
397 143 jeremybenn
}       /* or1ksim_interrupt () */
398 19 jeremybenn
 
399
 
400
/*---------------------------------------------------------------------------*/
401
/*!Clear a level triggered interrupt
402
 
403
   This function is appropriate for level triggered interrupts, which must be
404
   explicitly set first in a separate call.
405
 
406
   @note There is no check that the specified interrupt number is reasonable
407
   (i.e. <= 31).
408
 
409
   @param[in] i  The interrupt number to clear                               */
410
/*---------------------------------------------------------------------------*/
411
void
412
or1ksim_interrupt_clear (int i)
413
{
414
  if (config.pic.edge_trigger)
415
    {
416
      fprintf (stderr, "Warning: or1ksim_interrupt_clear should not be used "
417 93 jeremybenn
               "for edge triggered interrupts. Ignored\n");
418 19 jeremybenn
    }
419
  else
420
    {
421
      runtime.sim.ext_int_clr |= 1 << i;        // Better not be > 31!
422
    }
423 143 jeremybenn
}       /* or1ksim_interrupt () */
424 82 jeremybenn
 
425
 
426
/*---------------------------------------------------------------------------*/
427
/*!Reset the JTAG interface
428
 
429
   @note Like all the JTAG interface functions, this must not be called
430
         re-entrantly while a call to any other function (e.g. or1kim_run ())
431
         is in progress. It is the responsibility of the caller to ensure this
432
         constraint is met, for example by use of a SystemC mutex.
433
 
434
   @return  The time in seconds which the reset took.                        */
435
/*---------------------------------------------------------------------------*/
436
double
437
or1ksim_jtag_reset ()
438
{
439 98 jeremybenn
  /* Number of JTAG clock cycles a reset sequence takes */
440
  const double  JTAG_RESET_CYCLES = 5.0;
441 82 jeremybenn
 
442 98 jeremybenn
  jtag_reset ();
443
 
444
  return  JTAG_RESET_CYCLES  * (double) config.debug.jtagcycle_ps / 1.0e12;
445
 
446 82 jeremybenn
}       /* or1ksim_jtag_reset () */
447
 
448
 
449
/*---------------------------------------------------------------------------*/
450
/*!Shift a JTAG instruction register
451
 
452
   @note Like all the JTAG interface functions, this must not be called
453
         re-entrantly while a call to any other function (e.g. or1kim_run ())
454
         is in progress. It is the responsibility of the caller to ensure this
455
         constraint is met, for example by use of a SystemC mutex.
456
 
457
   The register is represented as a vector of bytes, with the byte at offset
458
   zero being shifted first, and the least significant bit in each byte being
459
   shifted first. Where the register will not fit in an exact number of bytes,
460
   the odd bits are in the highest numbered byte, shifted to the low end.
461
 
462
   The only JTAG instruction for which we have any significant behavior in
463
   this model is DEBUG. For completeness the register is parsed and a warning
464
   given if any register other than DEBUG is shifted.
465
 
466 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
467
                            back out.
468
   @param[in]     num_bits  The number of bits in the register. Just for
469
                            sanity check (it should always be 4).
470 82 jeremybenn
 
471
   @return  The time in seconds which the shift took.                        */
472
/*---------------------------------------------------------------------------*/
473
double
474 98 jeremybenn
or1ksim_jtag_shift_ir (unsigned char *jreg,
475
                       int            num_bits)
476 82 jeremybenn
{
477 98 jeremybenn
  jtag_shift_ir (jreg, num_bits);
478 82 jeremybenn
 
479 98 jeremybenn
  return  (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
480
 
481 82 jeremybenn
}       /* or1ksim_jtag_shift_ir () */
482
 
483
 
484
/*---------------------------------------------------------------------------*/
485
/*!Shift a JTAG data register
486
 
487
   @note Like all the JTAG interface functions, this must not be called
488
         re-entrantly while a call to any other function (e.g. or1kim_run ())
489
         is in progress. It is the responsibility of the caller to ensure this
490
         constraint is met, for example by use of a SystemC mutex.
491
 
492
   The register is represented as a vector of bytes, with the byte at offset
493
   zero being shifted first, and the least significant bit in each byte being
494
   shifted first. Where the register will not fit in an exact number of bytes,
495
   the odd bits are in the highest numbered byte, shifted to the low end.
496
 
497
   The register is parsed to determine which of the six possible register
498
   types it could be.
499
   - MODULE_SELECT
500
   - WRITE_COMMNAND
501
   - READ_COMMAND
502
   - GO_COMMAND
503
   - WRITE_CONTROL
504
   - READ_CONTROL
505
 
506
   @note In practice READ_COMMAND is not used. However the functionality is
507
         provided for future compatibility.
508
 
509 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
510
                            back out.
511
   @param[in]     num_bits  The number of bits in the register. This is
512
                            essential to prevent bugs where the size of
513
                            register supplied is incorrect.
514 82 jeremybenn
 
515
   @return  The time in seconds which the shift took.                        */
516
/*---------------------------------------------------------------------------*/
517
double
518 98 jeremybenn
or1ksim_jtag_shift_dr (unsigned char *jreg,
519
                       int            num_bits)
520 82 jeremybenn
{
521 98 jeremybenn
  jtag_shift_dr (jreg, num_bits);
522 82 jeremybenn
 
523 98 jeremybenn
  return  (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
524
 
525 82 jeremybenn
}       /* or1ksim_jtag_shift_dr () */
526 143 jeremybenn
 
527
 
528
/*---------------------------------------------------------------------------*/
529
/*!Read a block of memory.
530
 
531 224 jeremybenn
   @param[in]  addr  The address to read from.
532 143 jeremybenn
   @param[out] buf   Where to put the data.
533
   @param[in]  len   The number of bytes to read.
534
 
535
   @return  Number of bytes read, or zero if error.                          */
536
/*---------------------------------------------------------------------------*/
537
int
538 230 jeremybenn
or1ksim_read_mem (unsigned long int  addr,
539
                  unsigned char     *buf,
540
                  int                len)
541 143 jeremybenn
{
542
  int             off;                  /* Offset into the memory */
543
 
544
  /* Fill the buffer with data */
545
  for (off = 0; off < len; off++)
546
    {
547
      /* Check memory area is valid */
548
      if (NULL == verify_memoryarea (addr + off))
549
        {
550
          /* Fail silently - others can raise any error message. */
551
          return  0;
552
        }
553
      else
554
        {
555
          /* Get the memory direct - no translation. */
556
          buf[off] = eval_direct8 (addr + off, 0, 0);
557
        }
558
    }
559
 
560
  return  len;
561
 
562
}       /* or1ksim_read_mem () */
563
 
564
 
565
/*---------------------------------------------------------------------------*/
566
/*!Write a block of memory.
567
 
568 224 jeremybenn
   @param[in] addr  The address to write to.
569 143 jeremybenn
   @param[in] buf   Where to get the data from.
570
   @param[in] len   The number of bytes to write.
571
 
572
   @return  Number of bytes written, or zero if error.                       */
573
/*---------------------------------------------------------------------------*/
574
int
575 385 jeremybenn
or1ksim_write_mem (unsigned long int    addr,
576
                   const unsigned char *buf,
577
                   int                  len)
578 143 jeremybenn
{
579
  int             off;                  /* Offset into the memory */
580
 
581
  /* Write the bytes to memory */
582
  for (off = 0; off < len; off++)
583
    {
584
      if (NULL == verify_memoryarea (addr + off))
585
        {
586
          /* Fail silently - others can raise any error message. */
587
          return  0;
588
        }
589
      else
590
        {
591
          /* circumvent the read-only check usually done for mem accesses data
592
             is in host order, because that's what set_direct32 needs */
593
          set_program8 (addr + off, buf[off]);
594
        }
595
    }
596
 
597
  return  len;
598
 
599
}       /* or1ksim_write_mem () */
600
 
601
 
602
/*---------------------------------------------------------------------------*/
603 224 jeremybenn
/*!Read a SPR
604 143 jeremybenn
 
605 224 jeremybenn
   @param[in]  sprnum      The SPR to read.
606
   @param[out] sprval_ptr  Where to put the data.
607 143 jeremybenn
 
608 224 jeremybenn
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
609 143 jeremybenn
/*---------------------------------------------------------------------------*/
610
int
611 230 jeremybenn
or1ksim_read_spr (int                sprnum,
612
                  unsigned long int *sprval_ptr)
613 143 jeremybenn
{
614 224 jeremybenn
  /* SPR numbers are up to 16 bits long */
615
  if ((unsigned int) sprnum <= 0xffff)
616 143 jeremybenn
    {
617 224 jeremybenn
      *sprval_ptr = (unsigned int) mfspr ((uint16_t) sprnum);
618
      return  1;
619 143 jeremybenn
    }
620 224 jeremybenn
  else
621 143 jeremybenn
    {
622 224 jeremybenn
      return  0;                 /* Silent failure */
623 143 jeremybenn
    }
624 224 jeremybenn
}       /* or1skim_read_spr () */
625
 
626
 
627
/*---------------------------------------------------------------------------*/
628
/*!Write a SPR
629
 
630
   @param[in] sprnum  The SPR to write.
631
   @param[in] sprval  The data to write.
632
 
633
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
634
/*---------------------------------------------------------------------------*/
635
int
636 230 jeremybenn
or1ksim_write_spr (int                sprnum,
637
                   unsigned long int  sprval)
638 224 jeremybenn
{
639
  /* SPR numbers are up to 16 bits long */
640
  if ((unsigned int) sprnum <= 0xffff)
641 143 jeremybenn
    {
642 224 jeremybenn
      mtspr ((uint16_t) sprnum, sprval);
643
      return  1;
644 143 jeremybenn
    }
645 224 jeremybenn
  else
646 143 jeremybenn
    {
647 224 jeremybenn
      return  0;                 /* Silent failure */
648 143 jeremybenn
    }
649 224 jeremybenn
}       /* or1ksim_write_spr () */
650
 
651
 
652
/*---------------------------------------------------------------------------*/
653
/*!Read a single register
654
 
655
   The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
656
   (i.e. SPR NPC) and SR (i.e. SPR SR).
657
 
658
   Map to the corresponding SPR.
659
 
660
   @param[in]  regnum      The register to read.
661
   @param[out] regval_ptr  Where to put the data.
662
 
663
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
664
/*---------------------------------------------------------------------------*/
665
int
666 230 jeremybenn
or1ksim_read_reg (int                 regnum,
667
                  unsigned long int  *regval_ptr)
668 224 jeremybenn
{
669
  /* GPR's */
670
  if (regnum < MAX_GPRS)
671 143 jeremybenn
    {
672 224 jeremybenn
      return or1ksim_read_spr (regnum + SPR_GPR_BASE, regval_ptr);
673 143 jeremybenn
    }
674 224 jeremybenn
 
675
  /* SPR's or unknown */
676
  switch (regnum)
677 143 jeremybenn
    {
678 224 jeremybenn
    case PPC_REGNUM: return or1ksim_read_spr (SPR_PPC, regval_ptr);
679
    case NPC_REGNUM: return or1ksim_read_spr (SPR_NPC, regval_ptr);
680
    case SR_REGNUM:  return or1ksim_read_spr (SPR_SR, regval_ptr);
681
    default:
682 143 jeremybenn
      /* Silent error response if we don't know the register */
683
      return  0;
684
    }
685
}       /* or1ksim_read_reg () */
686
 
687
 
688
/*---------------------------------------------------------------------------*/
689
/*!Write a single register
690
 
691
   The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
692 224 jeremybenn
   (i.e. SPR NPC) and SR (i.e. SPR SR).
693 143 jeremybenn
 
694 224 jeremybenn
   Map to the corresponding SPR
695 143 jeremybenn
 
696 224 jeremybenn
   @param[in] regval  The register to write.
697 143 jeremybenn
   @param[in] regnum  The register to write.
698
 
699 224 jeremybenn
   @return  Non-zero (TRUE) on success, zero (FALSE) otherwise.              */
700 143 jeremybenn
/*---------------------------------------------------------------------------*/
701
int
702 230 jeremybenn
or1ksim_write_reg (int                regnum,
703
                   unsigned long int  regval)
704 143 jeremybenn
{
705 224 jeremybenn
  /* GPR's */
706
  if (regnum < MAX_GPRS)
707 143 jeremybenn
    {
708 224 jeremybenn
      return or1ksim_write_spr (regnum + SPR_GPR_BASE, regval);
709 143 jeremybenn
    }
710
 
711 224 jeremybenn
  /* SPR's or unknown */
712
  switch (regnum)
713 143 jeremybenn
    {
714 224 jeremybenn
    case PPC_REGNUM: return or1ksim_write_spr (SPR_PPC, regval);
715
    case NPC_REGNUM: return or1ksim_write_spr (SPR_NPC, regval);
716
    case SR_REGNUM:  return or1ksim_write_spr (SPR_SR,  regval);
717
    default:
718 143 jeremybenn
      /* Silent error response if we don't know the register */
719
      return  0;
720
    }
721 224 jeremybenn
}       /* or1ksim_write_reg () */
722 143 jeremybenn
 
723 224 jeremybenn
 
724
/*---------------------------------------------------------------------------*/
725
/*!Set the simulator stall state.
726 143 jeremybenn
 
727 224 jeremybenn
   @param[in] state  The stall state to set.                                 */
728
/*---------------------------------------------------------------------------*/
729
void
730
or1ksim_set_stall_state (int  state)
731
{
732
  set_stall_state (state ? 1 : 0);
733 143 jeremybenn
 
734 224 jeremybenn
}       /* or1ksim_set_stall_state () */

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