URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [mmu/] [dmmu.c] - Blame information for rev 865

Go to most recent revision | Details | Compare with Previous | View Log


/* dmmu.c -- Data MMU simulation
 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2008 Embecosm Limited
 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */
 
/* DMMU model, perfectly functional. */
 
 
/* Autoconf and/or portability configuration */
#include "config.h"
#include "port.h"
 
/* System includes */
#include <stdlib.h>
 
/* Package includes */
#include "dmmu.h"
#include "sim-config.h"
#include "arch.h"
#include "execute.h"
#include "spr-defs.h"
#include "stats.h"
#include "except.h"
#include "sprs.h"
#include "misc.h"
#include "sim-cmd.h"
#include "pcu.h"
 
struct dmmu *dmmu_state;
 
/* Data MMU */
 
static uorreg_t *
dmmu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** dtlbmr_lru, struct dmmu *dmmu)
{
  int set;
  int i;
  oraddr_t vpn;
  uorreg_t *dtlbmr;
 
  /* Which set to check out? */
  set = DADDR_PAGE (virtaddr) >> dmmu->pagesize_log2;
  set &= dmmu->set_mask;
  vpn = virtaddr & dmmu->vpn_mask;
 
  dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE (0) + set];
  *dtlbmr_lru = dtlbmr;
 
  /* FIXME: Should this be reversed? */
  for (i = dmmu->nways; i; i--, dtlbmr += (128 * 2))
    {
      if (((*dtlbmr & dmmu->vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
        return dtlbmr;
    }
 
  return NULL;
}
 
oraddr_t
dmmu_translate (oraddr_t virtaddr, int write_access)
{
  int i;
  uorreg_t *dtlbmr;
  uorreg_t *dtlbtr;
  uorreg_t *dtlbmr_lru;
  struct dmmu *dmmu = dmmu_state;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
    {
      data_ci = (virtaddr >= 0x80000000);
      return virtaddr;
    }
 
  dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
 
  /* Did we find our tlb entry? */
  if (dtlbmr)
    {                           /* Yes, we did. */
      dmmu_stats.loads_tlbhit++;
 
      dtlbtr = dtlbmr + 128;
 
      /* Set LRUs */
      for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
        {
          if (*dtlbmr_lru & SPR_DTLBMR_LRU)
            *dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
              ((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
        }
 
      /* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
       * is always decremented and the number of sets is always a power of two and
       * as such lru_reload has all bits set that get touched during decrementing
       * SPR_DTLBMR_LRU */
      *dtlbmr |= dmmu->lru_reload;
 
      /* Check if page is cache inhibited */
      data_ci = *dtlbtr & SPR_DTLBTR_CI;
 
      runtime.sim.mem_cycles += dmmu->hitdelay;
 
      /* Test for page fault */
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
              || (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
            except_handle (EXCEPT_DPF, virtaddr);
        }
      else
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
              || (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
            except_handle (EXCEPT_DPF, virtaddr);
        }
 
      return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
                                           (dmmu->page_offset_mask));
    }
 
  /* No, we didn't. */
  dmmu_stats.loads_tlbmiss++;
 
  runtime.sim.mem_cycles += dmmu->missdelay;
  /* if tlb refill implemented in HW */
  /* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
 
  except_handle (EXCEPT_DTLBMISS, virtaddr);
 
  if (config.pcu.enabled)
    pcu_count_event(SPR_PCMR_DTLBM);
 
  return 0;
}
 
/* DESC: try to find EA -> PA transaltion without changing
 *       any of precessor states. if this is not passible gives up
 *       (without triggering exceptions)
 *
 * PRMS: virtaddr     - EA for which to find translation
 *
 *       write_access - 0 ignore testing for write access
 *                      1 test for write access, if fails
 *                        do not return translation
 *
 *       through_dc   - 1 go through data cache
 *                      0 ignore data cache
 *
 * RTRN: 0            - no DMMU, DMMU disabled or ITLB miss
 *       else         - appropriate PA (note it DMMU is not present
 *                      PA === EA)
 */
oraddr_t
peek_into_dtlb (oraddr_t virtaddr, int write_access, int through_dc)
{
  uorreg_t *dtlbmr;
  uorreg_t *dtlbtr;
  uorreg_t *dtlbmr_lru;
  struct dmmu *dmmu = dmmu_state;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
    {
      if (through_dc)
        data_ci = (virtaddr >= 0x80000000);
      return virtaddr;
    }
 
  dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
 
  /* Did we find our tlb entry? */
  if (dtlbmr)
    {                           /* Yes, we did. */
      dmmu_stats.loads_tlbhit++;
 
      dtlbtr = dtlbmr + 128;
 
      /* Test for page fault */
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
              (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
 
            /* otherwise exception DPF would be raised */
            return (0);
        }
      else
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) ||
              (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
 
            /* otherwise exception DPF would be raised */
            return (0);
        }
 
      if (through_dc)
        {
          /* Check if page is cache inhibited */
          data_ci = *dtlbtr & SPR_DTLBTR_CI;
        }
 
      return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
                                           (dmmu->page_offset_mask));
    }
 
  return (0);
}
 
/* FIXME: Is this comment valid? */
/* First check if virtual address is covered by DTLB and if it is:
    - increment DTLB read hit stats,
    - set 'lru' at this way to dmmu->ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
    - check page access attributes and invoke DMMU page fault exception
      handler if necessary
   and if not:
    - increment DTLB read miss stats
    - find lru way and entry and invoke DTLB miss exception handler
    - set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/
 
static void
dtlb_status (void *dat)
{
  struct dmmu *dmmu = dat;
  int set;
  int way;
  int end_set = dmmu->nsets;
 
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
    {
      PRINTF ("DMMU not implemented. Set UPR[DMP].\n");
      return;
    }
 
  if (0 < end_set)
    PRINTF ("\nDMMU: ");
  /* Scan set(s) and way(s). */
  for (set = 0; set < end_set; set++)
    {
      for (way = 0; way < dmmu->nways; way++)
        {
          PRINTF ("%s\n", dump_spr (SPR_DTLBMR_BASE (way) + set,
                                    cpu_state.sprs[SPR_DTLBMR_BASE (way) +
                                                   set]));
          PRINTF ("%s\n",
                  dump_spr (SPR_DTLBTR_BASE (way) + set,
                            cpu_state.sprs[SPR_DTLBTR_BASE (way) + set]));
        }
    }
  if (0 < end_set)
    PRINTF ("\n");
}
 
/*---------------------------------------------------[ DMMU configuration ]---*/
 
/*---------------------------------------------------------------------------*/
/*!Enable or disable the DMMU
 
   Set the corresponding field in the UPR
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_enabled (union param_val val, void *dat)
{
  struct dmmu *dmmu = dat;
 
  if (val.int_val)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
    }
 
  dmmu->enabled = val.int_val;
 
}       /* dmmu_enabled() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU sets
 
   Value must be a power of 2 <= 256. Ignore any other values with a
   warning. Set the corresponding DMMU configuration flags.
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_nsets (union param_val  val,
            void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (is_power2 (val.int_val) && val.int_val <= 128)
    {
      int  set_bits = log2_int (val.int_val);
 
      dmmu->nsets = val.int_val;
 
      cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
      cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
    }
  else
    {
      fprintf (stderr, "Warning DMMU nsets not a power of 2 <= 128: ignored\n");
    }
}       /* dmmu_nsets() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU ways
 
   Value must be in the range 1-4. Ignore other values with a warning. Set the
   corresponding DMMU configuration flags.
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_nways (union param_val  val,
            void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (val.int_val >= 1 && val.int_val <= 4)
    {
      int  way_bits = val.int_val - 1;
 
      dmmu->nways = val.int_val;
 
      cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
      cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
    }
  else
    {
      fprintf (stderr, "Warning DMMU nways not in range 1-4: ignored\n");
    }
}       /* dmmu_nways() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the DMMU page size
 
   Value must be a power of 2. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_pagesize (union param_val  val,
               void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (is_power2 (val.int_val))
    {
      dmmu->pagesize = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning DMMU page size must be power of 2: ignored\n");
    }
}       /* dmmu_pagesize() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the DMMU entry size
 
   Value must be a power of 2. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_entrysize (union param_val  val,
                void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (is_power2 (val.int_val))
    {
      dmmu->entrysize = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning DMMU entry size must be power of 2: ignored\n");
    }
}       /* dmmu_entrysize() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU usage states
 
   Value must be 2, 3 or 4. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_ustates (union param_val  val,
              void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if ((val.int_val >= 2) && (val.int_val <= 4))
    {
      dmmu->ustates = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning number of DMMU usage states must be 2, 3 or 4:"
               "ignored\n");
    }
}       /* dmmu_ustates() */
 
 
static void
dmmu_missdelay (union param_val val, void *dat)
{
  struct dmmu *dmmu = dat;
 
  dmmu->missdelay = val.int_val;
}
 
static void
dmmu_hitdelay (union param_val val, void *dat)
{
  struct dmmu *dmmu = dat;
 
  dmmu->hitdelay = val.int_val;
}
 
/*---------------------------------------------------------------------------*/
/*!Initialize a new DMMU configuration
 
   ALL parameters are set explicitly to default values. Corresponding SPR
   flags are set as appropriate.
 
   @return  The new memory configuration data structure                      */
/*---------------------------------------------------------------------------*/
static void *
dmmu_start_sec ()
{
  struct dmmu *dmmu;
  int          set_bits;
  int          way_bits;
 
  if (NULL == (dmmu = malloc (sizeof (struct dmmu))))
    {
      fprintf (stderr, "OOM\n");
      exit (1);
    }
 
  dmmu->enabled   = 0;
  dmmu->nsets     = 1;
  dmmu->nways     = 1;
  dmmu->pagesize  = 8192;
  dmmu->entrysize = 1;          /* Not currently used */
  dmmu->ustates   = 2;
  dmmu->hitdelay  = 1;
  dmmu->missdelay = 1;
 
  if (dmmu->enabled)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
    }
 
  set_bits = log2_int (dmmu->nsets);
  cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
  cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
 
  way_bits = dmmu->nways - 1;
  cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
  cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
 
  dmmu_state = dmmu;
  return dmmu;
 
}       /* dmmu_start_sec() */
 
 
static void
dmmu_end_sec (void *dat)
{
  struct dmmu *dmmu = dat;
 
  /* Precalculate some values for use during address translation */
  dmmu->pagesize_log2 = log2_int (dmmu->pagesize);
  dmmu->page_offset_mask = dmmu->pagesize - 1;
  dmmu->page_mask = ~dmmu->page_offset_mask;
  dmmu->vpn_mask = ~((dmmu->pagesize * dmmu->nsets) - 1);
  dmmu->set_mask = dmmu->nsets - 1;
  dmmu->lru_reload = (dmmu->set_mask << 6) & SPR_DTLBMR_LRU;
 
  if (dmmu->enabled)
    {
      PRINTF ("Data MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
              dmmu->nsets * dmmu->entrysize * dmmu->nways / 1024, dmmu->nways,
              dmmu->nsets, dmmu->entrysize);
      reg_sim_stat (dtlb_status, dmmu);
    }
}
 
void
reg_dmmu_sec (void)
{
  struct config_section *sec = reg_config_sec ("dmmu", dmmu_start_sec,
                                               dmmu_end_sec);
 
  reg_config_param (sec, "enabled",   PARAMT_INT, dmmu_enabled);
  reg_config_param (sec, "nsets",     PARAMT_INT, dmmu_nsets);
  reg_config_param (sec, "nways",     PARAMT_INT, dmmu_nways);
  reg_config_param (sec, "pagesize",  PARAMT_INT, dmmu_pagesize);
  reg_config_param (sec, "entrysize", PARAMT_INT, dmmu_entrysize);
  reg_config_param (sec, "ustates",   PARAMT_INT, dmmu_ustates);
  reg_config_param (sec, "hitdelay",  PARAMT_INT, dmmu_hitdelay);
  reg_config_param (sec, "missdelay", PARAMT_INT, dmmu_missdelay);
}

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [mmu/] [dmmu.c] - Blame information for rev 865

Line No.	Rev	Author	Line
1	19	jeremybenn	`/* dmmu.c -- Data MMU simulation`
2
3			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
4			`Copyright (C) 2008 Embecosm Limited`
5
6			`Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
7
8			`This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.`
9
10			`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14
15			`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19
20			`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see <http://www.gnu.org/licenses/>. */`
22
23			`/* This program is commented throughout in a fashion suitable for processing`
24			`with Doxygen. */`
25
26			`/* DMMU model, perfectly functional. */`
27
28
29			`/* Autoconf and/or portability configuration */`
30			`#include "config.h"`
31			`#include "port.h"`
32
33			`/* System includes */`
34			`#include <stdlib.h>`
35
36			`/* Package includes */`
37			`#include "dmmu.h"`
38			`#include "sim-config.h"`
39			`#include "arch.h"`
40			`#include "execute.h"`
41			`#include "spr-defs.h"`
42			`#include "stats.h"`
43			`#include "except.h"`
44			`#include "sprs.h"`
45			`#include "misc.h"`
46			`#include "sim-cmd.h"`
47	556	julius	`#include "pcu.h"`
48	19	jeremybenn
49			`struct dmmu *dmmu_state;`
50
51			`/* Data MMU */`
52
53			`static uorreg_t *`
54			`dmmu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** dtlbmr_lru, struct dmmu *dmmu)`
55			`{`
56			`int set;`
57			`int i;`
58			`oraddr_t vpn;`
59			`uorreg_t *dtlbmr;`
60
61			`/* Which set to check out? */`
62			`set = DADDR_PAGE (virtaddr) >> dmmu->pagesize_log2;`
63			`set &= dmmu->set_mask;`
64			`vpn = virtaddr & dmmu->vpn_mask;`
65
66			`dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE (0) + set];`
67			`*dtlbmr_lru = dtlbmr;`
68
69			`/* FIXME: Should this be reversed? */`
70			`for (i = dmmu->nways; i; i--, dtlbmr += (128 * 2))`
71			`{`
72			`if (((dtlbmr & dmmu->vpn_mask) == vpn) && (dtlbmr & SPR_DTLBMR_V))`
73			`return dtlbmr;`
74			`}`
75
76			`return NULL;`
77			`}`
78
79			`oraddr_t`
80			`dmmu_translate (oraddr_t virtaddr, int write_access)`
81			`{`
82			`int i;`
83			`uorreg_t *dtlbmr;`
84			`uorreg_t *dtlbtr;`
85			`uorreg_t *dtlbmr_lru;`
86			`struct dmmu *dmmu = dmmu_state;`
87
88			`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) \|\|`
89			`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))`
90			`{`
91			`data_ci = (virtaddr >= 0x80000000);`
92			`return virtaddr;`
93			`}`
94
95			`dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);`
96
97			`/* Did we find our tlb entry? */`
98			`if (dtlbmr)`
99			`{ /* Yes, we did. */`
100			`dmmu_stats.loads_tlbhit++;`
101
102			`dtlbtr = dtlbmr + 128;`
103
104			`/* Set LRUs */`
105			`for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))`
106			`{`
107			`if (*dtlbmr_lru & SPR_DTLBMR_LRU)`
108			`dtlbmr_lru = (dtlbmr_lru & ~SPR_DTLBMR_LRU) \|`
109			`((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);`
110			`}`
111
112			/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
113			`* is always decremented and the number of sets is always a power of two and`
114			`* as such lru_reload has all bits set that get touched during decrementing`
115			`* SPR_DTLBMR_LRU */`
116			`*dtlbmr \|= dmmu->lru_reload;`
117
118			`/* Check if page is cache inhibited */`
119			`data_ci = *dtlbtr & SPR_DTLBTR_CI;`
120
121			`runtime.sim.mem_cycles += dmmu->hitdelay;`
122
123			`/* Test for page fault */`
124			`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
125			`{`
126			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE))`
127			`\|\| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))`
128			`except_handle (EXCEPT_DPF, virtaddr);`
129			`}`
130			`else`
131			`{`
132			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))`
133			`\|\| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))`
134			`except_handle (EXCEPT_DPF, virtaddr);`
135			`}`
136
137			`return (*dtlbtr & SPR_DTLBTR_PPN) \| (virtaddr &`
138			`(dmmu->page_offset_mask));`
139			`}`
140
141			`/* No, we didn't. */`
142			`dmmu_stats.loads_tlbmiss++;`
143
144			`runtime.sim.mem_cycles += dmmu->missdelay;`
145			`/* if tlb refill implemented in HW */`
146			`/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */`
147
148			`except_handle (EXCEPT_DTLBMISS, virtaddr);`
149	556	julius
150			`if (config.pcu.enabled)`
151			`pcu_count_event(SPR_PCMR_DTLBM);`
152
153	19	jeremybenn	`return 0;`
154			`}`
155
156			`/* DESC: try to find EA -> PA transaltion without changing`
157			`* any of precessor states. if this is not passible gives up`
158			`* (without triggering exceptions)`
159			`*`
160			`* PRMS: virtaddr - EA for which to find translation`
161			`*`
162			`* write_access - 0 ignore testing for write access`
163			`* 1 test for write access, if fails`
164			`* do not return translation`
165			`*`
166			`* through_dc - 1 go through data cache`
167			`* 0 ignore data cache`
168			`*`
169			`* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss`
170			`* else - appropriate PA (note it DMMU is not present`
171			`* PA === EA)`
172			`*/`
173			`oraddr_t`
174			`peek_into_dtlb (oraddr_t virtaddr, int write_access, int through_dc)`
175			`{`
176			`uorreg_t *dtlbmr;`
177			`uorreg_t *dtlbtr;`
178			`uorreg_t *dtlbmr_lru;`
179			`struct dmmu *dmmu = dmmu_state;`
180
181			`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) \|\|`
182			`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))`
183			`{`
184			`if (through_dc)`
185			`data_ci = (virtaddr >= 0x80000000);`
186			`return virtaddr;`
187			`}`
188
189			`dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);`
190
191			`/* Did we find our tlb entry? */`
192			`if (dtlbmr)`
193			`{ /* Yes, we did. */`
194			`dmmu_stats.loads_tlbhit++;`
195
196			`dtlbtr = dtlbmr + 128;`
197
198			`/* Test for page fault */`
199			`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
200			`{`
201			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) \|\|`
202			`(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))`
203
204			`/* otherwise exception DPF would be raised */`
205			`return (0);`
206			`}`
207			`else`
208			`{`
209			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) \|\|`
210			`(!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))`
211
212			`/* otherwise exception DPF would be raised */`
213			`return (0);`
214			`}`
215
216			`if (through_dc)`
217			`{`
218			`/* Check if page is cache inhibited */`
219			`data_ci = *dtlbtr & SPR_DTLBTR_CI;`
220			`}`
221
222			`return (*dtlbtr & SPR_DTLBTR_PPN) \| (virtaddr &`
223			`(dmmu->page_offset_mask));`
224			`}`
225
226			`return (0);`
227			`}`
228
229			`/* FIXME: Is this comment valid? */`
230			`/* First check if virtual address is covered by DTLB and if it is:`
231			`- increment DTLB read hit stats,`
232			`- set 'lru' at this way to dmmu->ustates - 1 and`
233			`decrement 'lru' of other ways unless they have reached 0,`
234			`- check page access attributes and invoke DMMU page fault exception`
235			`handler if necessary`
236			`and if not:`
237			`- increment DTLB read miss stats`
238			`- find lru way and entry and invoke DTLB miss exception handler`
239			`- set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other`
240			`ways unless they have reached 0`
241			`*/`
242
243			`static void`
244			`dtlb_status (void *dat)`
245			`{`
246			`struct dmmu *dmmu = dat;`
247			`int set;`
248			`int way;`
249			`int end_set = dmmu->nsets;`
250
251			`if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))`
252			`{`
253			`PRINTF ("DMMU not implemented. Set UPR[DMP].\n");`
254			`return;`
255			`}`
256
257			`if (0 < end_set)`
258			`PRINTF ("\nDMMU: ");`
259			`/* Scan set(s) and way(s). */`
260			`for (set = 0; set < end_set; set++)`
261			`{`
262			`for (way = 0; way < dmmu->nways; way++)`
263			`{`
264			`PRINTF ("%s\n", dump_spr (SPR_DTLBMR_BASE (way) + set,`
265			`cpu_state.sprs[SPR_DTLBMR_BASE (way) +`
266			`set]));`
267			`PRINTF ("%s\n",`
268			`dump_spr (SPR_DTLBTR_BASE (way) + set,`
269			`cpu_state.sprs[SPR_DTLBTR_BASE (way) + set]));`
270			`}`
271			`}`
272			`if (0 < end_set)`
273			`PRINTF ("\n");`
274			`}`
275
276			`/---------------------------------------------------[ DMMU configuration ]---/`
277
278			`/---------------------------------------------------------------------------/`
279			`/*!Enable or disable the DMMU`
280
281			`Set the corresponding field in the UPR`
282
283			`@param[in] val The value to use`
284			`@param[in] dat The config data structure */`
285			`/---------------------------------------------------------------------------/`
286			`static void`
287			`dmmu_enabled (union param_val val, void *dat)`
288			`{`
289			`struct dmmu *dmmu = dat;`
290
291			`if (val.int_val)`
292			`{`
293			`cpu_state.sprs[SPR_UPR] \|= SPR_UPR_DMP;`
294			`}`
295			`else`
296			`{`
297			`cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;`
298			`}`
299
300			`dmmu->enabled = val.int_val;`
301
302			`} /* dmmu_enabled() */`
303
304
305			`/---------------------------------------------------------------------------/`
306			`/*!Set the number of DMMU sets`
307
308			`Value must be a power of 2 <= 256. Ignore any other values with a`
309			`warning. Set the corresponding DMMU configuration flags.`
310
311			`@param[in] val The value to use`
312			`@param[in] dat The config data structure */`
313			`/---------------------------------------------------------------------------/`
314			`static void`
315			`dmmu_nsets (union param_val val,`
316			`void *dat)`
317			`{`
318			`struct dmmu *dmmu = dat;`
319
320			`if (is_power2 (val.int_val) && val.int_val <= 128)`
321			`{`
322			`int set_bits = log2_int (val.int_val);`
323
324			`dmmu->nsets = val.int_val;`
325
326			`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;`
327			`cpu_state.sprs[SPR_DMMUCFGR] \|= set_bits << SPR_DMMUCFGR_NTS_OFF;`
328			`}`
329			`else`
330			`{`
331			`fprintf (stderr, "Warning DMMU nsets not a power of 2 <= 128: ignored\n");`
332			`}`
333			`} /* dmmu_nsets() */`
334
335
336			`/---------------------------------------------------------------------------/`
337			`/*!Set the number of DMMU ways`
338
339			`Value must be in the range 1-4. Ignore other values with a warning. Set the`
340			`corresponding DMMU configuration flags.`
341
342			`@param[in] val The value to use`
343			`@param[in] dat The config data structure */`
344			`/---------------------------------------------------------------------------/`
345			`static void`
346			`dmmu_nways (union param_val val,`
347			`void *dat)`
348			`{`
349			`struct dmmu *dmmu = dat;`
350
351			`if (val.int_val >= 1 && val.int_val <= 4)`
352			`{`
353			`int way_bits = val.int_val - 1;`
354
355			`dmmu->nways = val.int_val;`
356
357			`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;`
358			`cpu_state.sprs[SPR_DMMUCFGR] \|= way_bits << SPR_DMMUCFGR_NTW_OFF;`
359			`}`
360			`else`
361			`{`
362			`fprintf (stderr, "Warning DMMU nways not in range 1-4: ignored\n");`
363			`}`
364			`} /* dmmu_nways() */`
365
366
367			`/---------------------------------------------------------------------------/`
368			`/*!Set the DMMU page size`
369
370			`Value must be a power of 2. Ignore other values with a warning`
371
372			`@param[in] val The value to use`
373			`@param[in] dat The config data structure */`
374			`/---------------------------------------------------------------------------/`
375			`static void`
376			`dmmu_pagesize (union param_val val,`
377			`void *dat)`
378			`{`
379			`struct dmmu *dmmu = dat;`
380
381			`if (is_power2 (val.int_val))`
382			`{`
383			`dmmu->pagesize = val.int_val;`
384			`}`
385			`else`
386			`{`
387			`fprintf (stderr, "Warning DMMU page size must be power of 2: ignored\n");`
388			`}`
389			`} /* dmmu_pagesize() */`
390
391
392			`/---------------------------------------------------------------------------/`
393			`/*!Set the DMMU entry size`
394
395			`Value must be a power of 2. Ignore other values with a warning`
396
397			`@param[in] val The value to use`
398			`@param[in] dat The config data structure */`
399			`/---------------------------------------------------------------------------/`
400			`static void`
401			`dmmu_entrysize (union param_val val,`
402			`void *dat)`
403			`{`
404			`struct dmmu *dmmu = dat;`
405
406			`if (is_power2 (val.int_val))`
407			`{`
408			`dmmu->entrysize = val.int_val;`
409			`}`
410			`else`
411			`{`
412			`fprintf (stderr, "Warning DMMU entry size must be power of 2: ignored\n");`
413			`}`
414			`} /* dmmu_entrysize() */`
415
416
417			`/---------------------------------------------------------------------------/`
418			`/*!Set the number of DMMU usage states`
419
420			`Value must be 2, 3 or 4. Ignore other values with a warning`
421
422			`@param[in] val The value to use`
423			`@param[in] dat The config data structure */`
424			`/---------------------------------------------------------------------------/`
425			`static void`
426			`dmmu_ustates (union param_val val,`
427			`void *dat)`
428			`{`
429			`struct dmmu *dmmu = dat;`
430
431			`if ((val.int_val >= 2) && (val.int_val <= 4))`
432			`{`
433			`dmmu->ustates = val.int_val;`
434			`}`
435			`else`
436			`{`
437			`fprintf (stderr, "Warning number of DMMU usage states must be 2, 3 or 4:"`
438			`"ignored\n");`
439			`}`
440			`} /* dmmu_ustates() */`
441
442
443			`static void`
444			`dmmu_missdelay (union param_val val, void *dat)`
445			`{`
446			`struct dmmu *dmmu = dat;`
447
448			`dmmu->missdelay = val.int_val;`
449			`}`
450
451			`static void`
452			`dmmu_hitdelay (union param_val val, void *dat)`
453			`{`
454			`struct dmmu *dmmu = dat;`
455
456			`dmmu->hitdelay = val.int_val;`
457			`}`
458
459			`/---------------------------------------------------------------------------/`
460			`/*!Initialize a new DMMU configuration`
461
462			`ALL parameters are set explicitly to default values. Corresponding SPR`
463			`flags are set as appropriate.`
464
465			`@return The new memory configuration data structure */`
466			`/---------------------------------------------------------------------------/`
467			`static void *`
468			`dmmu_start_sec ()`
469			`{`
470			`struct dmmu *dmmu;`
471			`int set_bits;`
472			`int way_bits;`
473
474			`if (NULL == (dmmu = malloc (sizeof (struct dmmu))))`
475			`{`
476			`fprintf (stderr, "OOM\n");`
477			`exit (1);`
478			`}`
479
480			`dmmu->enabled = 0;`
481			`dmmu->nsets = 1;`
482			`dmmu->nways = 1;`
483			`dmmu->pagesize = 8192;`
484			`dmmu->entrysize = 1; /* Not currently used */`
485			`dmmu->ustates = 2;`
486			`dmmu->hitdelay = 1;`
487			`dmmu->missdelay = 1;`
488
489			`if (dmmu->enabled)`
490			`{`
491			`cpu_state.sprs[SPR_UPR] \|= SPR_UPR_DMP;`
492			`}`
493			`else`
494			`{`
495			`cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;`
496			`}`
497
498			`set_bits = log2_int (dmmu->nsets);`
499			`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;`
500			`cpu_state.sprs[SPR_DMMUCFGR] \|= set_bits << SPR_DMMUCFGR_NTS_OFF;`
501
502			`way_bits = dmmu->nways - 1;`
503			`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;`
504			`cpu_state.sprs[SPR_DMMUCFGR] \|= way_bits << SPR_DMMUCFGR_NTW_OFF;`
505
506			`dmmu_state = dmmu;`
507			`return dmmu;`
508
509			`} /* dmmu_start_sec() */`
510
511
512			`static void`
513			`dmmu_end_sec (void *dat)`
514			`{`
515			`struct dmmu *dmmu = dat;`
516
517			`/* Precalculate some values for use during address translation */`
518			`dmmu->pagesize_log2 = log2_int (dmmu->pagesize);`
519			`dmmu->page_offset_mask = dmmu->pagesize - 1;`
520			`dmmu->page_mask = ~dmmu->page_offset_mask;`
521			`dmmu->vpn_mask = ~((dmmu->pagesize * dmmu->nsets) - 1);`
522			`dmmu->set_mask = dmmu->nsets - 1;`
523			`dmmu->lru_reload = (dmmu->set_mask << 6) & SPR_DTLBMR_LRU;`
524
525			`if (dmmu->enabled)`
526			`{`
527			`PRINTF ("Data MMU %dKB: %d ways, %d sets, entry size %d bytes\n",`
528			`dmmu->nsets * dmmu->entrysize * dmmu->nways / 1024, dmmu->nways,`
529			`dmmu->nsets, dmmu->entrysize);`
530			`reg_sim_stat (dtlb_status, dmmu);`
531			`}`
532			`}`
533
534			`void`
535			`reg_dmmu_sec (void)`
536			`{`
537			`struct config_section *sec = reg_config_sec ("dmmu", dmmu_start_sec,`
538			`dmmu_end_sec);`
539
540	224	jeremybenn	`reg_config_param (sec, "enabled", PARAMT_INT, dmmu_enabled);`
541			`reg_config_param (sec, "nsets", PARAMT_INT, dmmu_nsets);`
542			`reg_config_param (sec, "nways", PARAMT_INT, dmmu_nways);`
543			`reg_config_param (sec, "pagesize", PARAMT_INT, dmmu_pagesize);`
544			`reg_config_param (sec, "entrysize", PARAMT_INT, dmmu_entrysize);`
545			`reg_config_param (sec, "ustates", PARAMT_INT, dmmu_ustates);`
546			`reg_config_param (sec, "hitdelay", PARAMT_INT, dmmu_hitdelay);`
547			`reg_config_param (sec, "missdelay", PARAMT_INT, dmmu_missdelay);`
548	19	jeremybenn	`}`