OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [mmu/] [immu.c] - Blame information for rev 733

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* immu.c -- Instruction MMU simulation
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
/* Autoconf and/or portability configuration */
28
#include "config.h"
29
 
30
/* System includes */
31
#include <stdlib.h>
32
 
33
/* Package includes */
34
#include "immu.h"
35
#include "sim-config.h"
36
#include "execute.h"
37
#include "stats.h"
38
#include "except.h"
39
#include "spr-dump.h"
40
#include "misc.h"
41
#include "sim-cmd.h"
42 556 julius
#include "pcu.h"
43 19 jeremybenn
 
44
 
45
struct immu *immu_state;
46
 
47
/* Insn MMU */
48
 
49
static uorreg_t *
50
immu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** itlbmr_lru, struct immu *immu)
51
{
52
  int set;
53
  int i;
54
  oraddr_t vpn;
55
  uorreg_t *itlbmr;
56
 
57
  /* Which set to check out? */
58
  set = IADDR_PAGE (virtaddr) >> immu->pagesize_log2;
59
  set &= immu->set_mask;
60
  vpn = virtaddr & immu->vpn_mask;
61
 
62
  itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE (0) + set];
63
  *itlbmr_lru = itlbmr;
64
 
65
  /* Scan all ways and try to find a matching way. */
66
  /* FIXME: Should this be reversed? */
67
  for (i = immu->nways; i; i--, itlbmr += (128 * 2))
68
    {
69
      if (((*itlbmr & immu->vpn_mask) == vpn) && (*itlbmr & SPR_ITLBMR_V))
70
        return itlbmr;
71
    }
72
 
73
  return NULL;
74
}
75
 
76
oraddr_t
77
immu_translate (oraddr_t virtaddr)
78
{
79
  int i;
80
  uorreg_t *itlbmr;
81
  uorreg_t *itlbtr;
82
  uorreg_t *itlbmr_lru;
83
  struct immu *immu = immu_state;
84
 
85
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
86
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
87
    {
88
      insn_ci = (virtaddr >= 0x80000000);
89
      return virtaddr;
90
    }
91
 
92
  itlbmr = immu_find_tlbmr (virtaddr, &itlbmr_lru, immu);
93
 
94
  /* Did we find our tlb entry? */
95
  if (itlbmr)
96
    {                           /* Yes, we did. */
97
      immu_stats.fetch_tlbhit++;
98
      itlbtr = itlbmr + 128;
99
 
100
      /* Set LRUs */
101
      for (i = 0; i < immu->nways; i++, itlbmr_lru += (128 * 2))
102
        {
103
          if (*itlbmr_lru & SPR_ITLBMR_LRU)
104
            *itlbmr_lru = (*itlbmr_lru & ~SPR_ITLBMR_LRU) |
105
              ((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);
106
        }
107
 
108
      /* This is not necessary `*itlbmr &= ~SPR_ITLBMR_LRU;' since SPR_DTLBMR_LRU
109
       * is always decremented and the number of sets is always a power of two and
110
       * as such lru_reload has all bits set that get touched during decrementing
111
       * SPR_DTLBMR_LRU */
112
      *itlbmr |= immu->lru_reload;
113
 
114
      /* Check if page is cache inhibited */
115
      insn_ci = *itlbtr & SPR_ITLBTR_CI;
116
 
117
      runtime.sim.mem_cycles += immu->hitdelay;
118
 
119
      /* Test for page fault */
120
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
121
        {
122
          if (!(*itlbtr & SPR_ITLBTR_SXE))
123
            except_handle (EXCEPT_IPF, virtaddr);
124
        }
125
      else
126
        {
127
          if (!(*itlbtr & SPR_ITLBTR_UXE))
128
            except_handle (EXCEPT_IPF, virtaddr);
129
        }
130
 
131
      return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
132
    }
133
 
134
  /* No, we didn't. */
135
  immu_stats.fetch_tlbmiss++;
136
 
137
  /* if tlb refill implemented in HW */
138
  /* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * immu->pagesize + (virtaddr % immu->pagesize); */
139
  runtime.sim.mem_cycles += immu->missdelay;
140
 
141
  except_handle (EXCEPT_ITLBMISS, virtaddr);
142 556 julius
 
143
  if (config.pcu.enabled)
144
    pcu_count_event(SPR_PCMR_ITLBM);
145
 
146 19 jeremybenn
  return 0;
147
}
148
 
149
/* DESC: try to find EA -> PA transaltion without changing
150
 *       any of precessor states. if this is not passible gives up
151
 *       (without triggering exceptions).
152
 *
153
 * PRMS: virtaddr  - EA for which to find translation
154
 *
155
 * RTRN: 0         - no IMMU, IMMU disabled or ITLB miss
156
 *       else      - appropriate PA (note it IMMU is not present
157
 *                   PA === EA)
158
 */
159
oraddr_t
160
peek_into_itlb (oraddr_t virtaddr)
161
{
162
  uorreg_t *itlbmr;
163
  uorreg_t *itlbtr;
164
  uorreg_t *itlbmr_lru;
165
  struct immu *immu = immu_state;
166
 
167
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
168
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
169
    {
170
      return (virtaddr);
171
    }
172
 
173
  itlbmr = immu_find_tlbmr (virtaddr, &itlbmr_lru, immu);
174
 
175
  /* Did we find our tlb entry? */
176
  if (itlbmr)
177
    {                           /* Yes, we did. */
178
      itlbtr = itlbmr + 128;
179
 
180
      /* Test for page fault */
181
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
182
        {
183
          if (!(*itlbtr & SPR_ITLBTR_SXE))
184
            {
185
              /* no luck, giving up */
186
              return (0);
187
            }
188
        }
189
      else
190
        {
191
          if (!(*itlbtr & SPR_ITLBTR_UXE))
192
            {
193
              /* no luck, giving up */
194
              return (0);
195
            }
196
        }
197
 
198
      return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
199
    }
200
 
201
  return (0);
202
}
203
 
204
 
205
/* FIXME: Check validity */
206
/* First check if virtual address is covered by ITLB and if it is:
207
    - increment ITLB read hit stats,
208
    - set 'lru' at this way to immu->ustates - 1 and
209
      decrement 'lru' of other ways unless they have reached 0,
210
    - check page access attributes and invoke IMMU page fault exception
211
      handler if necessary
212
   and if not:
213
    - increment ITLB read miss stats
214
    - find lru way and entry and invoke ITLB miss exception handler
215
    - set 'lru' with immu->ustates - 1 and decrement 'lru' of other
216
      ways unless they have reached 0
217
*/
218
 
219
static void
220
itlb_status (void *dat)
221
{
222
  struct immu *immu = dat;
223
  int set;
224
  int way;
225
  int end_set = immu->nsets;
226
 
227
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
228
    {
229
      PRINTF ("IMMU not implemented. Set UPR[IMP].\n");
230
      return;
231
    }
232
 
233
  if (0 < end_set)
234
    PRINTF ("\nIMMU: ");
235
  /* Scan set(s) and way(s). */
236
  for (set = 0; set < end_set; set++)
237
    {
238
      for (way = 0; way < immu->nways; way++)
239
        {
240
          PRINTF ("%s\n", dump_spr (SPR_ITLBMR_BASE (way) + set,
241
                                    cpu_state.sprs[SPR_ITLBMR_BASE (way) +
242
                                                   set]));
243
          PRINTF ("%s\n",
244
                  dump_spr (SPR_ITLBTR_BASE (way) + set,
245
                            cpu_state.sprs[SPR_ITLBTR_BASE (way) + set]));
246
        }
247
    }
248
  if (0 < end_set)
249
    PRINTF ("\n");
250
}
251
 
252
/*---------------------------------------------------[ IMMU configuration ]---*/
253
 
254
/*---------------------------------------------------------------------------*/
255
/*!Enable or disable the IMMU
256
 
257
   Set the corresponding field in the UPR
258
 
259
   @param[in] val  The value to use
260
   @param[in] dat  The config data structure                                 */
261
/*---------------------------------------------------------------------------*/
262
static void
263
immu_enabled (union param_val val, void *dat)
264
{
265
  struct immu *immu = dat;
266
 
267
  if (val.int_val)
268
    {
269
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
270
    }
271
  else
272
    {
273
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
274
    }
275
 
276
  immu->enabled = val.int_val;
277
}
278
 
279
 
280
/*---------------------------------------------------------------------------*/
281
/*!Set the number of DMMU sets
282
 
283
   Value must be a power of 2 <= 256. Ignore any other values with a
284
   warning. Set the corresponding IMMU configuration flags.
285
 
286
   @param[in] val  The value to use
287
   @param[in] dat  The config data structure                                 */
288
/*---------------------------------------------------------------------------*/
289
static void
290
immu_nsets (union param_val  val,
291
            void            *dat)
292
{
293
  struct immu *immu = dat;
294
 
295
  if (is_power2 (val.int_val) && (val.int_val <= 128))
296
    {
297
      int  set_bits = log2_int (val.int_val);
298
 
299
      immu->nsets = val.int_val;
300
 
301
      cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
302
      cpu_state.sprs[SPR_IMMUCFGR] |= set_bits << SPR_IMMUCFGR_NTS_OFF;
303
    }
304
  else
305
    {
306
      fprintf (stderr, "Warning IMMU nsets not a power of 2 <= 128: ignored\n");
307
    }
308
}       /* immu_nsets() */
309
 
310
 
311
/*---------------------------------------------------------------------------*/
312
/*!Set the number of IMMU ways
313
 
314
   Value must be in the range 1-4. Ignore other values with a warning.  Set
315
   the corresponding IMMU configuration flags.
316
 
317
   @param[in] val  The value to use
318
   @param[in] dat  The config data structure                                 */
319
/*---------------------------------------------------------------------------*/
320
static void
321
immu_nways (union param_val  val,
322
            void            *dat)
323
{
324
  struct immu *immu = dat;
325
 
326
  if (val.int_val >= 1 && val.int_val <= 4)
327
    {
328
      int  way_bits = val.int_val - 1;
329
 
330
      immu->nways = val.int_val;
331
 
332
      cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
333
      cpu_state.sprs[SPR_IMMUCFGR] |= way_bits << SPR_IMMUCFGR_NTW_OFF;
334
    }
335
  else
336
    {
337
      fprintf (stderr, "Warning IMMU nways not in range 1-4: ignored\n");
338
    }
339
}       /* immu_nways() */
340
 
341
 
342
/*---------------------------------------------------------------------------*/
343
/*!Set the IMMU page size
344
 
345
   Value must be a power of 2. Ignore other values with a warning
346
 
347
   @param[in] val  The value to use
348
   @param[in] dat  The config data structure                                 */
349
/*---------------------------------------------------------------------------*/
350
static void
351
immu_pagesize (union param_val  val,
352
               void            *dat)
353
{
354
  struct immu *immu = dat;
355
 
356
  if (is_power2 (val.int_val))
357
    {
358
      immu->pagesize = val.int_val;
359
    }
360
  else
361
    {
362
      fprintf (stderr, "Warning IMMU page size must be power of 2: ignored\n");
363
    }
364
}       /* immu_pagesize() */
365
 
366
 
367
/*---------------------------------------------------------------------------*/
368
/*!Set the IMMU entry size
369
 
370
   Value must be a power of 2. Ignore other values with a warning
371
 
372
   @param[in] val  The value to use
373
   @param[in] dat  The config data structure                                 */
374
/*---------------------------------------------------------------------------*/
375
static void
376
immu_entrysize (union param_val  val,
377
                void            *dat)
378
{
379
  struct immu *immu = dat;
380
 
381
  if (is_power2 (val.int_val))
382
    {
383
      immu->entrysize = val.int_val;
384
    }
385
  else
386
    {
387
      fprintf (stderr, "Warning IMMU entry size must be power of 2: ignored\n");
388
    }
389
}       /* immu_entrysize() */
390
 
391
 
392
/*---------------------------------------------------------------------------*/
393
/*!Set the number of IMMU usage states
394
 
395
   Value must be 2, 3 or 4. Ignore other values with a warning
396
 
397
   @param[in] val  The value to use
398
   @param[in] dat  The config data structure                                 */
399
/*---------------------------------------------------------------------------*/
400
static void
401
immu_ustates (union param_val  val,
402
              void            *dat)
403
{
404
  struct immu *immu = dat;
405
 
406
  if ((val.int_val >= 2) && (val.int_val <= 4))
407
    {
408
      immu->ustates = val.int_val;
409
    }
410
  else
411
    {
412
      fprintf (stderr, "Warning number of IMMU usage states must be 2, 3 or 4:"
413
               "ignored\n");
414
    }
415
}       /* immu_ustates() */
416
 
417
 
418
static void
419
immu_missdelay (union param_val val, void *dat)
420
{
421
  struct immu *immu = dat;
422
 
423
  immu->missdelay = val.int_val;
424
}
425
 
426
static void
427
immu_hitdelay (union param_val val, void *dat)
428
{
429
  struct immu *immu = dat;
430
 
431
  immu->hitdelay = val.int_val;
432
}
433
 
434
/*---------------------------------------------------------------------------*/
435
/*!Initialize a new DMMU configuration
436
 
437
   ALL parameters are set explicitly to default values.                      */
438
/*---------------------------------------------------------------------------*/
439
static void *
440
immu_start_sec ()
441
{
442
  struct immu *immu;
443
  int          set_bits;
444
  int          way_bits;
445
 
446
  if (NULL == (immu = malloc (sizeof (struct immu))))
447
    {
448
      fprintf (stderr, "OOM\n");
449
      exit (1);
450
    }
451
 
452
  immu->enabled   = 0;
453
  immu->nsets     = 1;
454
  immu->nways     = 1;
455
  immu->pagesize  = 8192;
456
  immu->entrysize = 1;          /* Not currently used */
457
  immu->ustates   = 2;
458
  immu->hitdelay  = 1;
459
  immu->missdelay = 1;
460
 
461
  if (immu->enabled)
462
    {
463
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
464
    }
465
  else
466
    {
467
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
468
    }
469
 
470
  set_bits = log2_int (immu->nsets);
471
  cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
472
  cpu_state.sprs[SPR_IMMUCFGR] |= set_bits << SPR_IMMUCFGR_NTS_OFF;
473
 
474
  way_bits = immu->nways - 1;
475
  cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
476
  cpu_state.sprs[SPR_IMMUCFGR] |= way_bits << SPR_IMMUCFGR_NTW_OFF;
477
 
478
  immu_state = immu;
479
  return immu;
480
 
481
}       /* immu_start_sec() */
482
 
483
 
484
static void
485
immu_end_sec (void *dat)
486
{
487
  struct immu *immu = dat;
488
 
489
  /* Precalculate some values for use during address translation */
490
  immu->pagesize_log2 = log2_int (immu->pagesize);
491
  immu->page_offset_mask = immu->pagesize - 1;
492
  immu->page_mask = ~immu->page_offset_mask;
493
  immu->vpn_mask = ~((immu->pagesize * immu->nsets) - 1);
494
  immu->set_mask = immu->nsets - 1;
495
  immu->lru_reload = (immu->set_mask << 6) & SPR_ITLBMR_LRU;
496
 
497
  if (immu->enabled)
498
    {
499
      PRINTF ("Insn MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
500
              immu->nsets * immu->entrysize * immu->nways / 1024, immu->nways,
501
              immu->nsets, immu->entrysize);
502
      reg_sim_stat (itlb_status, immu);
503
    }
504
}
505
 
506
void
507
reg_immu_sec (void)
508
{
509
  struct config_section *sec = reg_config_sec ("immu", immu_start_sec,
510
                                               immu_end_sec);
511
 
512 224 jeremybenn
  reg_config_param (sec, "enabled",   PARAMT_INT, immu_enabled);
513
  reg_config_param (sec, "nsets",     PARAMT_INT, immu_nsets);
514
  reg_config_param (sec, "nways",     PARAMT_INT, immu_nways);
515
  reg_config_param (sec, "pagesize",  PARAMT_INT, immu_pagesize);
516
  reg_config_param (sec, "entrysize", PARAMT_INT, immu_entrysize);
517
  reg_config_param (sec, "ustates",   PARAMT_INT, immu_ustates);
518
  reg_config_param (sec, "missdelay", PARAMT_INT, immu_missdelay);
519
  reg_config_param (sec, "hitdelay",  PARAMT_INT, immu_hitdelay);
520 19 jeremybenn
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.