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jeremybenn |
/* atahost.h -- ATA Host code simulation
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Definitions for the Opencores ATA Host Controller Core */
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#ifndef ATAHOST__H
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#define ATAHOST__H
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#include "arch.h"
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#include "atadevice.h"
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/* --- Register definitions --- */
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/* ----- Core Registers */
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#define ATA_CTRL 0x00 /* Control register */
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#define ATA_STAT 0x04 /* Status register */
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#define ATA_PCTR 0x08 /* PIO command timing register */
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#define ATA_PFTR0 0x0c /* PIO Fast Timing register Device0 */
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#define ATA_PFTR1 0x10 /* PIO Fast Timing register Device1 */
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#define ATA_DTR0 0x14 /* DMA Timing register Device2 */
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#define ATA_DTR1 0x18 /* DMA Timing register Device1 */
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#define ATA_TXB 0x3c /* DMA Transmit buffer */
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#define ATA_RXB 0x3c /* DMA Receive buffer */
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/* ---------------------------- */
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/* ----- Bits definitions ----- */
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/* ---------------------------- */
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/* ----- Core Control register */
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/* bits 31-16 are reserved */
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#define ATA_DMA_EN (0<<15) /* DMAen, DMA enable bit */
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/* bit 14 is reserved */
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#define ATA_DMA_WR (1<<14) /* DMA Write transaction */
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#define ATA_DMA_RD (0<<14) /* DMA Read transaction */
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/* bits 13-10 are reserved */
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#define ATA_BELEC1 (1<< 9) /* Big-Little endian conversion */
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/* enable bit for Device1 */
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#define ATA_BELEC0 (1<< 8) /* Big-Little endian conversion */
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/* enable bit for Device0 */
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#define ATA_IDE_EN (1<< 7) /* IDE core enable bit */
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#define ATA_FTE1 (1<< 6) /* Device1 Fast PIO Timing Enable bit */
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#define ATA_FTE0 (1<< 5) /* Device0 Fast PIO Timing Enable bit */
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#define ATA_PWPP (1<< 4) /* PIO Write Ping-Pong Enable bit */
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#define ATA_IORDY_FTE1 (1<< 3) /* Device1 Fast PIO Timing IORDY */
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/* enable bit */
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#define ATA_IORDY_FTE0 (1<< 2) /* Device0 Fast PIO Timing IORDY */
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/* enable bit */
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#define ATA_IORDY (1<< 1) /* PIO Command Timing IORDY enable bit */
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#define ATA_RST (1<< 0) /* ATA Reset bit */
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/* ----- Core Status register */
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#define ATA_DEVID 0xf0000000 /* bits 31-28 Device-ID */
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#define ATA_REVNO 0x0f000000 /* bits 27-24 Revision number */
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/* bits 23-16 are reserved */
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#define ATA_DMA_TIP (1<<15) /* DMA Transfer in progress */
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/* bits 14-10 are reserved */
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#define ATA_DRBE (1<<10) /* DMA Receive buffer empty */
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#define ATA_DTBF (1<< 9) /* DMA Transmit buffer full */
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#define ATA_DMARQ (1<< 8) /* DMARQ Line status */
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#define ATA_PIO_TIP (1<< 7 /* PIO Transfer in progress */
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#define ATA_PWPPF (1<< 6) /* PIO write ping-pong full */
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/* bits 5-1 are reserved */
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#define ATA_IDEIS (1<< 0) /* IDE Interrupt status */
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/* ----- Core Timing registers */
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#define ATA_TEOC 24 /* End of cycle time DMA/PIO */
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#define ATA_T4 16 /* DIOW- data hold time PIO */
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#define ATA_T2 8 /* DIOR-/DIOW- pulse width PIO */
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#define ATA_TD 8 /* DIOR-/DIOW- pulse width DMA */
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#define ATA_T1 0 /* Address valid to DIOR-/DIOW- PIO */
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#define ATA_TM 0 /* CS[1:0]valid to DIOR-/DIOW- DMA */
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/* ----------------------------- */
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/* ----- Simulator defines ----- */
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/* ----------------------------- */
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#define ATA_ADDR_SPACE 0x80
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/* ---------------------------- */
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/* ----- Structs ----- */
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/* ---------------------------- */
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struct ata_host
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{
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/* Is peripheral enabled? */
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int enabled;
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/* Base address in memory */
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oraddr_t baseaddr;
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/* Registered memory area */
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struct dev_memarea *mem;
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/* Which IRQ to generate */
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int irq;
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/* Which ocidec version is implemented */
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int dev_id;
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/* OCIDEC revision */
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int rev;
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/* Current selected device */
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int dev_sel;
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/* PIO T1 reset value */
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uint8_t pio_mode0_t1;
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/* PIO T2 reset value */
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uint8_t pio_mode0_t2;
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/* PIO T4 reset value */
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uint8_t pio_mode0_t4;
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/* PIO Teoc reset value */
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uint8_t pio_mode0_teoc;
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/* DMA Tm reset value */
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uint8_t dma_mode0_tm;
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/* DMA Td reset value */
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uint8_t dma_mode0_td;
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/* DMA Teoc reset value */
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uint8_t dma_mode0_teoc;
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/* ata host registers */
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struct
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{
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uint32_t ctrl;
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uint32_t stat;
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uint32_t pctr;
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uint32_t pftr0;
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uint32_t pftr1;
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uint32_t dtr0;
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uint32_t dtr1;
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uint32_t txb;
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uint32_t rxb;
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} regs;
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/* connected ATA devices (slaves) */
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struct ata_devices devices;
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};
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/* ---------------------------- */
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/* ----- Prototypes ----- */
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/* ---------------------------- */
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void ata_int (void *dat);
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/* ---------------------------- */
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/* ----- Macros ----- */
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/* ---------------------------- */
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#define is_ata_hostadr(adr) (!(adr & 0x40))
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// FIXME
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#define ata_pio_delay(pioreg) ( (((pioreg >> ATA_T1) & 0xff) +1) + (((pioreg >> ATA_T2) & 0xff) +1) + (((pioreg >> ATA_T4) & 0xff) +1) +1 )
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#define ata_dma_delay(dmareg) ( (((dmareg >> ATA_TD) & 0xff) +1) + (((pioreg >> ATA_TM) & 0xff) +1) +1 )
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/* Prototypes for external use */
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void reg_ata_sec ();
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#endif /* ATAHOST__H */
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