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[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [dma-defs.h] - Blame information for rev 228

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1 19 jeremybenn
/* dma-defs.h -- Definition of relative addresses/register bits for DMA
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   Copyright (C) 2001 by Erez Volk, erez@opencores.org
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   Copyright (C) 2008 Embecosm Limited
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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/* This program is commented throughout in a fashion suitable for processing
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   with Doxygen. */
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#ifndef DMA_DEFS__H
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#define DMA_DEFS__H
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/* Number of channel per DMA controller */
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#define DMA_NUM_CHANNELS  31
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/* Address space required by one DMA controller */
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#define DMA_ADDR_SPACE  0x400
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/* Relative Register Addresses */
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#define DMA_CSR        0x00
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#define DMA_INT_MSK_A  0x04
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#define DMA_INT_MSK_B  0x08
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#define DMA_INT_SRC_A  0x0C
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#define DMA_INT_SRC_B  0x10
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/* Channel registers definitions */
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#define DMA_CH_BASE  0x20       /*!< Offset of first channel registers */
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#define DMA_CH_SIZE  0x20       /*!< Per-channel address space */
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/* Per-channel Register Addresses, relative to channel start */
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#define DMA_CH_CSR    0x00
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#define DMA_CH_SZ     0x04
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#define DMA_CH_A0     0x08
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#define DMA_CH_AM0    0x0C
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#define DMA_CH_A1     0x10
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#define DMA_CH_AM1    0x14
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#define DMA_CH_DESC   0x18
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#define DMA_CH_SWPTR  0x1C
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/* Field Definitions for the Main CSR */
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#define DMA_CSR_PAUSE_OFFSET             0
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/* Field Definitions for the Channel CSR(s) */
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#define DMA_CH_CSR_CH_EN_OFFSET           0
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#define DMA_CH_CSR_DST_SEL_OFFSET         1
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#define DMA_CH_CSR_SRC_SEL_OFFSET         2
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#define DMA_CH_CSR_INC_DST_OFFSET         3
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#define DMA_CH_CSR_INC_SRC_OFFSET         4
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#define DMA_CH_CSR_MODE_OFFSET            5
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#define DMA_CH_CSR_ARS_OFFSET             6
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#define DMA_CH_CSR_USE_ED_OFFSET          7
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#define DMA_CH_CSR_SZ_WB_OFFSET           8
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#define DMA_CH_CSR_STOP_OFFSET            9
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#define DMA_CH_CSR_BUSY_OFFSET           10
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#define DMA_CH_CSR_DONE_OFFSET           11
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#define DMA_CH_CSR_ERR_OFFSET            12
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#define DMA_CH_CSR_PRIORITY_OFFSET       13
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#define DMA_CH_CSR_PRIORITY_WIDTH         3
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#define DMA_CH_CSR_REST_EN_OFFSET        16
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#define DMA_CH_CSR_INE_ERR_OFFSET        17
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#define DMA_CH_CSR_INE_DONE_OFFSET       18
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#define DMA_CH_CSR_INE_CHK_DONE_OFFSET   19
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#define DMA_CH_CSR_INT_ERR_OFFSET        20
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#define DMA_CH_CSR_INT_DONE_OFFSET       21
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#define DMA_CH_CSR_INT_CHUNK_DONE_OFFSET 22
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#define DMA_CH_CSR_RESERVED_OFFSET       23
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#define DMA_CH_CSR_RESERVED_WIDTH         9
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/* Masks -- Writable and readonly parts of the register */
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#define DMA_CH_CSR_WRITE_MASK            0x000FE3FF
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/* Field definitions for Channel Size Registers */
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#define DMA_CH_SZ_TOT_SZ_OFFSET           0
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#define DMA_CH_SZ_TOT_SZ_WIDTH           12
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#define DMA_CH_SZ_CHK_SZ_OFFSET          16
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#define DMA_CH_SZ_CHK_SZ_WIDTH            9
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/* Field definitions for Channel Address Registers CHn_Am */
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#define DMA_CH_A0_ADDR_OFFSET             2
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#define DMA_CH_A0_ADDR_WIDTH             30
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#define DMA_CH_A1_ADDR_OFFSET             2
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#define DMA_CH_A1_ADDR_WIDTH             30
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/* Field definitions for Channel Address Mask Registers CHn_AMm */
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#define DMA_CH_AM0_MASK_OFFSET            4
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#define DMA_CH_AM0_MASK_WIDTH            28
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#define DMA_CH_AM1_MASK_OFFSET            4
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#define DMA_CH_AM1_MASK_WIDTH            28
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/* Field definitions for Channel Linked List descriptor Pointer CHn_DESC */
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#define DMA_CH_DESC_ADDR_OFFSET           2
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#define DMA_CH_DESC_ADDR_WIDTH           30
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/* Field definitions for Channel Software Pointer */
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#define DMA_CH_SWPTR_PTR_OFFSET           2
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#define DMA_CH_SWPTR_PTR_WIDTH           29
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#define DMA_CH_SWPTR_EN_OFFSET           31
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/* Structure of linked list descriptors (offsets of elements)  */
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#define DMA_DESC_CSR                     0x00
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#define DMA_DESC_ADR0                    0x04
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#define DMA_DESC_ADR1                    0x08
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#define DMA_DESC_NEXT                    0x0C
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/* Field definitions for linked list descriptor DESC_CSR */
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#define DMA_DESC_CSR_EOL_OFFSET          20
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#define DMA_DESC_CSR_INC_SRC_OFFSET      19
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#define DMA_DESC_CSR_INC_DST_OFFSET      18
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#define DMA_DESC_CSR_SRC_SEL_OFFSET      17
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#define DMA_DESC_CSR_DST_SEL_OFFSET      16
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#define DMA_DESC_CSR_TOT_SZ_OFFSET        0
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#define DMA_DESC_CSR_TOT_SZ_WIDTH        12
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#endif  /* DMA_DEFS__H */

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