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[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [dma.h] - Blame information for rev 249

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1 19 jeremybenn
/* dma.h -- Definition of DMA<->peripheral interface
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   Copyright (C) 2001 by Erez Volk, erez@opencores.org
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   Copyright (C) 2008 Embecosm Limited
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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/* This program is commented throughout in a fashion suitable for processing
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   with Doxygen. */
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#ifndef DMA__H
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#define DMA__H
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/* Package includes */
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#include "dma-defs.h"
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#include "sim-config.h"
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/* Implementation of DMA Channel Registers and State */
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struct dma_channel
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{
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  /* The controller we belong to */
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  struct dma_controller *controller;
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  /* Our channel number and bit mask */
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  unsigned channel_number;
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  unsigned long channel_mask;
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  /* Used for dump, to save dumping all 32 channels */
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  unsigned referenced;
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  /* Inner state of transfer etc. */
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  unsigned load_next_descriptor_when_done;
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  unsigned long current_descriptor;
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  oraddr_t source, destination, source_mask, destination_mask;
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  unsigned long chunk_size, total_size, words_transferred;
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  /* The interface registers */
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  struct
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  {
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    unsigned long csr;
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    unsigned long sz;
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    unsigned long a0;
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    unsigned long am0;
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    unsigned long a1;
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    unsigned long am1;
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    unsigned long desc;
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    unsigned long swptr;
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  } regs;
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  /* Some control signals */
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  unsigned dma_req_i;
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  unsigned dma_ack_o;
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  unsigned dma_nd_i;
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};
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/* Implementation of DMA Controller Registers and State */
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struct dma_controller
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{
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  /* Is peripheral enabled */
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  int enabled;
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  /* Base address in memory */
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  oraddr_t baseaddr;
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  /* Which interrupt number we generate */
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  unsigned irq;
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  /* VAPI id */
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  int vapi_id;
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  /* Controller Registers */
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  struct
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  {
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    unsigned long csr;
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    unsigned long int_msk_a;
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    unsigned long int_msk_b;
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    unsigned long int_src_a;
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    unsigned long int_src_b;
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  } regs;
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  /* Channels */
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  struct dma_channel ch[DMA_NUM_CHANNELS];
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  struct dma_controller *next;
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};
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void set_dma_req_i (struct dma_channel *channel);
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void clear_dma_req_i (struct dma_channel *channel);
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void set_dma_nd_i (struct dma_channel *channel);
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void clear_dma_nd_i (struct dma_channel *channel);
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unsigned check_dma_ack_o (struct dma_channel *channel);
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struct dma_channel *find_dma_controller_ch (unsigned controller,
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                                            unsigned channel);
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/* Prototype for external use */
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extern void  reg_dma_sec ();
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#endif  /* DMA__H */

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