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[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [eth.h] - Blame information for rev 584

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1 19 jeremybenn
/* eth.h -- Simulation of Ethernet MAC header
2
 
3
   Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
#ifndef ETH__H
28
#define ETH__H
29
 
30 82 jeremybenn
#if HAVE_NET_ETHERNET_H
31
# include <net/ethernet.h>
32
#elif defined(HAVE_SYS_ETHERNET_H)
33
# include <sys/ethernet.h>
34
#else /* !HAVE_NET_ETHERNET_H && !HAVE_SYS_ETHERNET_H - */
35
#include <sys/types.h>
36
#endif
37
 
38
/* Address space required by one Ethernet MAC */
39
#define ETH_ADDR_SPACE 0x1000
40
 
41
/* Relative Register Addresses */
42
#define ETH_MODER       (4 * 0x00)
43
#define ETH_INT_SOURCE  (4 * 0x01)
44
#define ETH_INT_MASK    (4 * 0x02)
45
#define ETH_IPGT        (4 * 0x03)
46
#define ETH_IPGR1       (4 * 0x04)
47
#define ETH_IPGR2       (4 * 0x05)
48
#define ETH_PACKETLEN   (4 * 0x06)
49
#define ETH_COLLCONF    (4 * 0x07)
50
#define ETH_TX_BD_NUM   (4 * 0x08)
51
#define ETH_CTRLMODER   (4 * 0x09)
52
#define ETH_MIIMODER    (4 * 0x0A)
53
#define ETH_MIICOMMAND  (4 * 0x0B)
54
#define ETH_MIIADDRESS  (4 * 0x0C)
55
#define ETH_MIITX_DATA  (4 * 0x0D)
56
#define ETH_MIIRX_DATA  (4 * 0x0E)
57
#define ETH_MIISTATUS   (4 * 0x0F)
58
#define ETH_MAC_ADDR0   (4 * 0x10)
59
#define ETH_MAC_ADDR1   (4 * 0x11)
60
#define ETH_HASH0       (4 * 0x12)
61
#define ETH_HASH1       (4 * 0x13)
62
 
63
/* Where BD's are stored */
64
#define ETH_BD_BASE        0x400
65
#define ETH_BD_COUNT       0x100
66
#define ETH_BD_SPACE       (4 * ETH_BD_COUNT)
67
 
68
/* Where to point DMA to transmit/receive */
69
#define ETH_DMA_RX_TX      0x800
70
 
71
/* Field definitions for MODER */
72
#define ETH_MODER_DMAEN_OFFSET     17
73
#define ETH_MODER_RECSMALL_OFFSET  16
74
#define ETH_MODER_PAD_OFFSET       15
75
#define ETH_MODER_HUGEN_OFFSET     14
76
#define ETH_MODER_CRCEN_OFFSET     13
77
#define ETH_MODER_DLYCRCEN_OFFSET  12
78
#define ETH_MODER_RST_OFFSET       11
79
#define ETH_MODER_FULLD_OFFSET     10
80
#define ETH_MODER_EXDFREN_OFFSET   9
81
#define ETH_MODER_NOBCKOF_OFFSET   8
82
#define ETH_MODER_LOOPBCK_OFFSET   7
83
#define ETH_MODER_IFG_OFFSET       6
84
#define ETH_MODER_PRO_OFFSET       5
85
#define ETH_MODER_IAM_OFFSET       4
86
#define ETH_MODER_BRO_OFFSET       3
87
#define ETH_MODER_NOPRE_OFFSET     2
88
#define ETH_MODER_TXEN_OFFSET      1
89
#define ETH_MODER_RXEN_OFFSET      0
90
 
91
/* Field definitions for INT_SOURCE */
92
#define ETH_INT_SOURCE_RXC_OFFSET  6
93
#define ETH_INT_SOURCE_TXC_OFFSET  5
94
#define ETH_INT_SOURCE_BUSY_OFFSET 4
95
#define ETH_INT_SOURCE_RXE_OFFSET  3
96
#define ETH_INT_SOURCE_RXB_OFFSET  2
97
#define ETH_INT_SOURCE_TXE_OFFSET  1
98
#define ETH_INT_SOURCE_TXB_OFFSET  0
99
 
100
/* Field definitions for INT_MASK */
101
#define ETH_INT_MASK_RXC_M_OFFSET  6
102
#define ETH_INT_MASK_TXC_M_OFFSET  5
103
#define ETH_INT_MASK_BUSY_M_OFFSET 4
104
#define ETH_INT_MASK_RXE_M_OFFSET  3
105
#define ETH_INT_MASK_RXB_M_OFFSET  2
106
#define ETH_INT_MASK_TXE_M_OFFSET  1
107
#define ETH_INT_MASK_TXB_M_OFFSET  0
108
 
109
/* Field definitions for PACKETLEN */
110
#define ETH_PACKETLEN_MINFL_OFFSET 16
111
#define ETH_PACKETLEN_MINFL_WIDTH  16
112
#define ETH_PACKETLEN_MAXFL_OFFSET 0
113
#define ETH_PACKETLEN_MAXFL_WIDTH  16
114
 
115
/* Field definitions for COLLCONF */
116
#define ETH_COLLCONF_MAXRET_OFFSET 16
117
#define ETH_COLLCONF_MAXRET_WIDTH  4
118
#define ETH_COLLCONF_COLLVALID_OFFSET 0
119
#define ETH_COLLCONF_COLLVALID_WIDTH  6
120
 
121
/* Field definitions for CTRLMODER */
122
#define ETH_CMODER_TXFLOW_OFFSET   2
123
#define ETH_CMODER_RXFLOW_OFFSET   1
124
#define ETH_CMODER_PASSALL_OFFSET  0
125
 
126
/* Field definitions for MIIMODER */
127
#define ETH_MIIMODER_NOPRE_OFFSET  8
128
#define ETH_MIIMODER_CLKDIV_OFFSET 0
129 428 julius
#define ETH_MIIMODER_CLKDIV_MASK   0xff
130 82 jeremybenn
 
131
/* Field definitions for MIICOMMAND */
132
#define ETH_MIICOMM_WCDATA_OFFSET  2
133
#define ETH_MIICOMM_RSTAT_OFFSET   1
134
#define ETH_MIICOMM_SCANS_OFFSET   0
135
 
136
/* Field definitions for MIIADDRESS */
137
#define ETH_MIIADDR_RGAD_OFFSET    8
138 428 julius
#define ETH_MIIADDR_RGAD_MASK     0x1f     
139 82 jeremybenn
#define ETH_MIIADDR_FIAD_OFFSET    0
140 428 julius
#define ETH_MIIADDR_FIAD_MASK     0x1f
141 82 jeremybenn
 
142
/* Field definitions for MIISTATUS */
143
#define ETH_MIISTAT_NVALID_OFFSET  1
144
#define ETH_MIISTAT_BUSY_OFFSET    1
145
#define ETH_MIISTAT_FAIL_OFFSET    0
146
 
147
/* Field definitions for TX buffer descriptors */
148
#define ETH_TX_BD_LENGTH_OFFSET        16
149
#define ETH_TX_BD_LENGTH_WIDTH         16
150
#define ETH_TX_BD_READY_OFFSET         15
151
#define ETH_TX_BD_IRQ_OFFSET           14
152
#define ETH_TX_BD_WRAP_OFFSET          13
153
#define ETH_TX_BD_PAD_OFFSET           12
154
#define ETH_TX_BD_CRC_OFFSET           11
155
#define ETH_TX_BD_LAST_OFFSET          10
156
#define ETH_TX_BD_PAUSE_OFFSET         9
157
#define ETH_TX_BD_UNDERRUN_OFFSET      8
158
#define ETH_TX_BD_RETRY_OFFSET         4
159
#define ETH_TX_BD_RETRY_WIDTH          4
160
#define ETH_TX_BD_RETRANSMIT_OFFSET    3
161
#define ETH_TX_BD_COLLISION_OFFSET     2
162
#define ETH_TX_BD_DEFER_OFFSET         1
163
#define ETH_TX_BD_NO_CARRIER_OFFSET    0
164
 
165
 
166
/* Field definitions for RX buffer descriptors */
167
#define ETH_RX_BD_LENGTH_OFFSET        16
168
#define ETH_RX_BD_LENGTH_WIDTH         16
169
#define ETH_RX_BD_READY_OFFSET         15
170
#define ETH_RX_BD_IRQ_OFFSET           14
171
#define ETH_RX_BD_WRAP_OFFSET          13
172
#define ETH_RX_BD_MISS_OFFSET          7
173
#define ETH_RX_BD_UVERRUN_OFFSET       6
174
#define ETH_RX_BD_INVALID_OFFSET       5
175
#define ETH_RX_BD_DRIBBLE_OFFSET       4
176
#define ETH_RX_BD_TOOBIG_OFFSET        3
177
#define ETH_RX_BD_TOOSHORT_OFFSET      2
178
#define ETH_RX_BD_CRC_OFFSET           1
179
#define ETH_RX_BD_COLLISION_OFFSET     0
180
 
181
/*
182
 * Ethernet protocol definitions
183
 */
184
#ifdef HAVE_NET_ETHERNET_H
185
#elif defined(HAVE_SYS_ETHERNET_H)
186
#ifndef ETHER_ADDR_LEN
187
#define ETHER_ADDR_LEN ETHERADDRL
188
#endif
189
#ifndef ETHER_HDR_LEN
190
#define ETHER_HDR_LEN sizeof(struct ether_header)
191
#endif
192
#else /* !HAVE_NET_ETHERNET_H && !HAVE_SYS_ETHERNET_H - */
193
#ifdef __CYGWIN__
194
/* define some missing cygwin defines.
195
 */
196
#define ETH_HLEN      14
197
#endif /* __CYGWIN__ */
198
 
199
#define ETH_ALEN    6
200
 
201
struct ether_addr
202
{
203
  u_int8_t ether_addr_octet[ETH_ALEN];
204
};
205
 
206
struct ether_header
207
{
208
  u_int8_t ether_dhost[ETH_ALEN];       /* destination eth addr */
209
  u_int8_t ether_shost[ETH_ALEN];       /* source ether addr    */
210
  u_int16_t ether_type;         /* packet type ID field */
211
};
212
 
213
/* Ethernet protocol ID's */
214
#define ETHERTYPE_PUP           0x0200  /* Xerox PUP */
215
#define ETHERTYPE_IP            0x0800  /* IP */
216
#define ETHERTYPE_ARP           0x0806  /* Address resolution */
217
#define ETHERTYPE_REVARP        0x8035  /* Reverse ARP */
218
 
219
#define ETHER_ADDR_LEN  ETH_ALEN        /* size of ethernet addr */
220
#define ETHER_TYPE_LEN  2       /* bytes in type field */
221
#define ETHER_CRC_LEN   4       /* bytes in CRC field */
222
#define ETHER_HDR_LEN   ETH_HLEN        /* total octets in header */
223
#define ETHER_MIN_LEN   (ETH_ZLEN + ETHER_CRC_LEN)      /* min packet length */
224
#define ETHER_MAX_LEN   (ETH_FRAME_LEN + ETHER_CRC_LEN) /* max packet length */
225
 
226
/* make sure ethenet length is valid */
227
#define ETHER_IS_VALID_LEN(foo) \
228
        ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
229
 
230
/*
231
 * The ETHERTYPE_NTRAILER packet types starting at ETHERTYPE_TRAIL have
232
 * (type-ETHERTYPE_TRAIL)*512 bytes of data followed
233
 * by an ETHER type (as given above) and then the (variable-length) header.
234
 */
235
#define ETHERTYPE_TRAIL         0x1000  /* Trailer packet */
236
#define ETHERTYPE_NTRAILER      16
237
 
238
#define ETHERMTU        ETH_DATA_LEN
239
#define ETHERMIN        (ETHER_MIN_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
240
 
241
#endif /* HAVE_NET_ETHERNET_H */
242
 
243
/*
244
 * Implementatino of Ethernet MAC Registers and State
245
 */
246
#define ETH_RTX_FILE    0
247 434 jeremybenn
#define ETH_RTX_TAP     1
248 82 jeremybenn
#define ETH_RTX_VAPI    2
249
 
250
#define ETH_MAXPL   0x10000
251
 
252
enum
253
{ ETH_VAPI_DATA = 0,
254
  ETH_VAPI_CTRL,
255
  ETH_NUM_VAPI_IDS
256
};
257
 
258
 
259 19 jeremybenn
/* Prototypes for external use */
260
extern void  reg_ethernet_sec ();
261
 
262 428 julius
 
263
/* Defines taken from linux-2.6.36/include/linux/mii.h for PHY register IF */
264
 
265
#define MII_BMCR            0x00        /* Basic mode control register */
266
#define MII_BMSR            0x01        /* Basic mode status register  */
267
#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
268
#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
269
#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
270
#define MII_LPA             0x05        /* Link partner ability reg    */
271
#define MII_EXPANSION       0x06        /* Expansion register          */
272
#define MII_CTRL1000        0x09        /* 1000BASE-T control          */
273
#define MII_STAT1000        0x0a        /* 1000BASE-T status           */
274
#define MII_ESTATUS         0x0f        /* Extended Status */
275
#define MII_DCOUNTER        0x12        /* Disconnect counter          */
276
#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
277
#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
278
#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
279
#define MII_SREVISION       0x16        /* Silicon revision            */
280
#define MII_RESV1           0x17        /* Reserved...                 */
281
#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
282
#define MII_PHYADDR         0x19        /* PHY address                 */
283
#define MII_RESV2           0x1a        /* Reserved...                 */
284
#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
285
#define MII_NCONFIG         0x1c        /* Network interface config    */
286
 
287
/* Basic mode control register. */
288
#define BMCR_RESV               0x003f  /* Unused...                   */
289
#define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
290
#define BMCR_CTST               0x0080  /* Collision test              */
291
#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
292
#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
293
#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
294
#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
295
#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
296
#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
297
#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
298
#define BMCR_RESET              0x8000  /* Reset the DP83840           */
299
 
300
/* Basic mode status register. */
301
#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
302
#define BMSR_JCD                0x0002  /* Jabber detected             */
303
#define BMSR_LSTATUS            0x0004  /* Link status                 */
304
#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
305
#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
306
#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
307
#define BMSR_RESV               0x00c0  /* Unused...                   */
308
#define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
309
#define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
310
#define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
311
#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
312
#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
313
#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
314
#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
315
#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
316
 
317
/* Advertisement control register. */
318
#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
319
#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
320
#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
321
#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
322
#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
323
#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
324
#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
325
#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
326
#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
327
#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
328
#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
329
#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
330
#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
331
#define ADVERTISE_RESV          0x1000  /* Unused...                   */
332
#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
333
#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
334
#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
335
 
336
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
337
                        ADVERTISE_CSMA)
338
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
339
                       ADVERTISE_100HALF | ADVERTISE_100FULL)
340
 
341
/* Link partner ability register. */
342
#define LPA_SLCT                0x001f  /* Same as advertise selector  */
343
#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
344
#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
345
#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
346
#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
347
#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
348
#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
349
#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
350
#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
351
#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
352
#define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
353
#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
354
#define LPA_RESV                0x1000  /* Unused...                   */
355
#define LPA_RFAULT              0x2000  /* Link partner faulted        */
356
#define LPA_LPACK               0x4000  /* Link partner acked us       */
357
#define LPA_NPAGE               0x8000  /* Next page bit               */
358
 
359
#define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
360
#define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
361
 
362
/* Expansion register for auto-negotiation. */
363
#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
364
#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
365
#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
366
#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
367
#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
368
#define EXPANSION_RESV          0xffe0  /* Unused...                   */
369
 
370
#define ESTATUS_1000_TFULL      0x2000  /* Can do 1000BT Full */
371
#define ESTATUS_1000_THALF      0x1000  /* Can do 1000BT Half */
372
 
373
/* N-way test register. */
374
#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
375
#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
376
#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
377
 
378
/* 1000BASE-T Control register */
379
#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
380
#define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
381
 
382
/* 1000BASE-T Status register */
383
#define LPA_1000LOCALRXOK       0x2000  /* Link partner local receiver status */
384
#define LPA_1000REMRXOK         0x1000  /* Link partner remote receiver status */
385
#define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex */
386
#define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
387
 
388
/* Flow control flags */
389
#define FLOW_CTRL_TX            0x01
390
#define FLOW_CTRL_RX            0x02
391
 
392
 
393
 
394 19 jeremybenn
#endif /* ETH__H */

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