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[/] [openrisc/] [trunk/] [or1ksim/] [pic/] [pic.c] - Blame information for rev 496

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Line No. Rev Author Line
1 19 jeremybenn
/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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   Copyright (C) 2008 Embecosm Limited
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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   with Doxygen. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "port.h"
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/* System includes */
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#include <stdlib.h>
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#include <stdio.h>
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/* Package includes */
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#include "arch.h"
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#include "abstract.h"
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#include "pic.h"
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#include "opcode/or32.h"
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#include "spr-defs.h"
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#include "execute.h"
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#include "except.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sched.h"
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48 432 jeremybenn
/* -------------------------------------------------------------------------- */
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/* Reset the PIC.
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   Sets registers to consistent values.                                       */
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/* -------------------------------------------------------------------------- */
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void
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pic_reset (void)
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{
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  PRINTFQ ("Resetting PIC.\n");
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  cpu_state.sprs[SPR_PICMR] = config.pic.use_nmi ? 0x00000003 : 0x00000000;
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  cpu_state.sprs[SPR_PICSR] = 0x00000000;
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}       /* pic_reset () */
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/* -------------------------------------------------------------------------- */
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/* Handle the reporting of an interrupt
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   PIC interrupts are scheduled to take place after the current instruction
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   has completed execution.
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   @param[in] dat  Data associated with the exception (not used)              */
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/* -------------------------------------------------------------------------- */
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static void
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pic_rep_int (void *dat)
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{
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  /* printf ("Handling interrupt PICSR: 0x%08x\n", cpu_state.sprs[SPR_PICSR]);
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   */
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  if (cpu_state.sprs[SPR_PICSR])
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    {
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      except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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    }
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}       /* pic_rep_int () */
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/* -------------------------------------------------------------------------- */
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/* Enable interrupts.
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   Called whenever interrupts get enabled, or when PICMR is written.
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   @todo Not sure if calling whenever PICMR is written is a good
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         idea. However, so long as interrupts are properly cleared, it should
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         not be a problem.                                                    */
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/* -------------------------------------------------------------------------- */
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void
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pic_ints_en (void)
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{
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  if ((cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR]))
97 432 jeremybenn
    {
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      SCHED_ADD (pic_rep_int, NULL, 0);
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    }
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}       /* pic_ints_en () */
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/* -------------------------------------------------------------------------- */
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/*!Assert an interrupt to the PIC
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   OpenRISC supports both edge and level triggered interrupt. The only
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   difference is how the interrupt is cleared. For edge triggered, it is by
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   clearing the corresponding bit in PICSR. For level triggered it is by
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   deasserting the interrupt line.
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   For integrated peripherals, these amount to the same thing (using
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   clear_interrupt ()). For external peripherals, the library provides two
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   distinct interfaces.
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   An interrupt disables any power management activity.
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   We warn if an interrupt is received on a line that already has an interrupt
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   pending.
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   @note If this is called during a simulated instruction (ie. from a read/
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         write mem callback), the interrupt will be delivered after the
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         instruction has finished executing.
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   @param[in] line  The interrupt being asserted.                             */
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/* -------------------------------------------------------------------------- */
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void
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report_interrupt (int line)
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{
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  uint32_t lmask = 1 << line;
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  /* printf ("Interrupt reported on line %d\n", line); */
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  /* Disable doze and sleep mode */
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  cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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  /* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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  if (!config.pic.enabled)
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    {
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      if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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        except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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      return;
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    }
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  /* We can't take another interrupt if the previous one has not been
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     cleared. */
146 430 julius
  if (cpu_state.sprs[SPR_PICSR] & lmask)
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    {
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      /* Interrupt already signaled and pending */
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      PRINTF ("Warning: Int on line %d pending: ignored\n", line);
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      return;
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    }
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  cpu_state.sprs[SPR_PICSR] |= lmask;
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  /* If we are enabled in the mask, and interrupts are globally enabled in the
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     SR, schedule the interrupt to take place after the next instruction. */
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  if ((cpu_state.sprs[SPR_PICMR] & lmask) &&
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      (cpu_state.sprs[SPR_SR] & SPR_SR_IEE))
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    {
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      /* printf ("Scheduling interrupt on line %d\n", line); */
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      SCHED_ADD (pic_rep_int, NULL, 0);
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    }
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}       /* report_interrupt () */
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/* -------------------------------------------------------------------------- */
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/* Clear an interrupt on a PIC line.
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   Logically this is different for a level sensitive interrupt (it lowers the
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   input line) and an edge sensitive interrupt (it clears the PICSR bit).
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   However within Or1ksim, these are implemented through the same operation -
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   clearing the bit in PICSR.
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   @param[in] line  The interrupt being cleared.                              */
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/* -------------------------------------------------------------------------- */
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void
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clear_interrupt (int line)
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{
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  cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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}       /* clear_interrupt */
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/*----------------------------------------------------[ PIC configuration ]---*/
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable the programmable interrupt controller
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   Set the corresponding field in the UPR
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   @param[in] val  The value to use
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   @param[in] dat  The config data structure (not used here)                 */
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/*---------------------------------------------------------------------------*/
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static void
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pic_enabled (union param_val  val,
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             void            *dat)
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{
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  if (val.int_val)
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    {
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      cpu_state.sprs[SPR_UPR] |= SPR_UPR_PICP;
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    }
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  else
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    {
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      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_PICP;
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    }
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  config.pic.enabled = val.int_val;
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}       /* pic_enabled() */
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable edge triggering of interrupts
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   @param[in] val  The value to use
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   @param[in] dat  The config data structure (not used here)                 */
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/*---------------------------------------------------------------------------*/
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static void
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pic_edge_trigger (union param_val  val,
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                  void            *dat)
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{
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  config.pic.edge_trigger = val.int_val;
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}       /* pic_edge_trigger() */
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/*---------------------------------------------------------------------------*/
230 432 jeremybenn
/*!Enable or disable non-maskable interrupts
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   @param[in] val  The value to use
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   @param[in] dat  The config data structure (not used here)                 */
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/*---------------------------------------------------------------------------*/
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static void
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pic_use_nmi (union param_val  val,
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                  void            *dat)
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{
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  config.pic.use_nmi = val.int_val;
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}       /* pic_use_nmi() */
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/*---------------------------------------------------------------------------*/
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/*!Initialize a new interrupt controller configuration
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   ALL parameters are set explicitly to default values in init_defconfig()   */
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/*---------------------------------------------------------------------------*/
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void
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reg_pic_sec ()
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{
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  struct config_section *sec = reg_config_sec ("pic", NULL, NULL);
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  reg_config_param (sec, "enabled",      PARAMT_INT, pic_enabled);
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  reg_config_param (sec, "edge_trigger", PARAMT_INT, pic_edge_trigger);
256 432 jeremybenn
  reg_config_param (sec, "use_nmi",      PARAMT_INT, pic_use_nmi);
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}       /* reg_pic_sec() */

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