URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.h] - Blame information for rev 850

Go to most recent revision | Details | Compare with Previous | View Log


/* sim-config.h -- Simulator configuration header file
 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2008 Embecosm Limited
 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */
 
 
#ifndef SIM_CONFIG_H
#define SIM_CONFIG_H
 
/* System includes */
#include <stdio.h>
 
/* Package includes */
#include "arch.h"
 
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
 
#define MAX_SBUF_LEN     256    /* Max. length of store buffer */
 
#define EXE_LOG_HARDWARE   0    /* Print out RTL states */
#define EXE_LOG_SIMPLE     1    /* Executed log prints out dissasembly */
#define EXE_LOG_SOFTWARE   2    /* Simple with some register output */
 
#define STR_SIZE         256
 
/* Number of cycles between checks to runtime.sim.iprompt */
#define CHECK_INT_TIME 100000
 
/* Print to the defined output stream */
#define PRINTF(x...) fprintf (runtime.sim.fout, x)
 
/* Print only if we are not running silently */
#define PRINTFQ(x...) if (!config.sim.quiet) { fprintf (runtime.sim.fout, x); }
 
/*! Data structure for configuration data */
struct config
{
  struct
  {                             /* External linkage for SystemC */
    void  *class_ptr;
    int  (*read_up) (void              *class_ptr,
                     unsigned long int  addr,
                     unsigned char      mask[],
                     unsigned char      rdata[],
                     int                data_len);
    int  (*write_up) (void              *class_ptr,
                      unsigned long int  addr,
                      unsigned char      mask[],
                      unsigned char      wdata[],
                      int                data_len);
  } ext;
 
  struct
  {
    int is_library;             /* Library operation */
    int debug;                  /* Simulator debugging */
    int verbose;                /* Force verbose output */
 
    int profile;                /* Is profiler running */
    char *prof_fn;              /* Profiler filename */
 
    int mprofile;               /* Is memory profiler running */
    char *mprof_fn;             /* Memory profiler filename */
 
    int history;                /* instruction stream history analysis */
    int exe_log;                /* Print out RTL states? */
    int exe_log_type;           /* Type of log */
    long long int exe_log_start;        /* First instruction to log */
    long long int exe_log_end;  /* Last instr to log, -1 if continuous */
    int exe_log_marker;         /* If nonzero, place markers before */
    /* each exe_log_marker instructions */
    char *exe_log_fn;           /* RTL state comparison filename */
    int exe_bin_insn_log;       /* Binary dump log of exec. instructions */
    char* exe_bin_insn_log_fn;  /* Binary dump log of exec. instructions name */
    long clkcycle_ps;           /* Clock duration in ps */
    int strict_npc;             /* JPB. NPC flushes pipeline when changed */
    int  quiet;                 /* Minimize message output */
    int  report_mem_errs;       /* Report out of memory accesses */
  } sim;
 
  struct
  {                             /* Verification API */
    int enabled;                /* Whether is VAPI module enabled */
    int server_port;            /* user specified port for services */
    int log_enabled;            /* Whether to log the vapi requests */
    int hide_device_id;         /* Whether to log dev ID each request */
    char *vapi_fn;              /* vapi log filename */
  } vapi;
 
  struct
  {
    char *timings_fn;           /* Filename of the timing table */
    int memory_order;           /* Memory access stricness */
    int calling_convention;     /* Do funcs follow std calling conv? */
    int enable_bursts;          /* Whether burst are enabled */
    int no_multicycle;          /* Generate no multicycle paths */
  } cuc;
 
  struct
  {
    int superscalar;            /* superscalara analysis */
    int hazards;                /* dependency hazards analysis */
    int dependstats;            /* dependency statistics */
    int sbuf_len;               /* length of store buffer, 0=disabled */
    int hardfloat;      /* whether hardfloat is enabled */
  } cpu;
 
  struct
  {
    int enabled;                /* Whether data cache is enabled */
    int nways;                  /* Number of DC ways */
    int nsets;                  /* Number of DC sets */
    int blocksize;              /* DC entry size */
    int ustates;                /* number of DC usage states */
    int store_missdelay;        /* cycles a store miss costs */
    int store_hitdelay;         /* cycles a store hit costs */
    int load_missdelay;         /* cycles a load miss costs */
    int load_hitdelay;          /* cycles a load hit costs */
  } dc;
 
  struct pic
  {
    int enabled;                /* Is interrupt controller enabled? */
    int edge_trigger;           /* Are interrupts edge triggered? */
    int use_nmi;                /* Do we have non-maskable interrupts? */
  } pic;
 
  struct
  {
    int enabled;                /* Is power management operational? */
  } pm;
 
  struct
  {
    int enabled;                /* Are performance counters enabled? */
  } pcu;
 
  struct
  {
    int enabled;                /* branch prediction buffer analysis */
    int sbp_bnf_fwd;            /* Static BP for l.bnf uses fwd predn */
    int sbp_bf_fwd;             /* Static BP for l.bf uses fwd predn */
    int btic;                   /* BP target insn cache analysis */
    int missdelay;              /* How much cycles does the miss cost */
    int hitdelay;               /* How much cycles does the hit cost */
  } bpb;
 
  struct
  {
    int enabled;                /* Is debug module enabled */
    int rsp_enabled;            /* Is RSP debugging with GDB possible */
    int rsp_port;               /* Port for RSP GDB connection */
    unsigned long vapi_id;      /* "Fake" vapi dev id for JTAG proxy */
    long int  jtagcycle_ps;     /* JTAG clock duration in ps */
  } debug;
};
 
/*! Data structure for run time data */
struct runtime
{
  struct
  {
    FILE *fprof;                /* Profiler file */
    FILE *fmprof;               /* Memory profiler file */
    FILE *fexe_log;             /* RTL state comparison file */
    FILE *fexe_bin_insn_log;    /* Binary instruction dump/log file */
    FILE *fout;                 /* file for standard output */
    char *filename;             /* Original Command Simulator file (CZ) */
    int iprompt;                /* Interactive prompt */
    int iprompt_run;            /* Interactive prompt is running */
    long long cycles;           /* Cycles counts fetch stages */
    long long int end_cycles;   /* JPB. Cycles to end of quantum */
    double time_point;          /* JPB. Time point in the simulation */
    unsigned long int ext_int_set;      /* JPB. External interrupts to set */
    unsigned long int ext_int_clr;      /* DXL. External interrupts ti clear */
 
    int mem_cycles;             /* Each cycle has counter of mem_cycles;
                                   this value is joined with cycles
                                   at the end of the cycle; no sim
                                   originated memory accesses should be
                                   performed inbetween. */
    int loadcycles;             /* Load and store stalls */
    int storecycles;
 
    long long reset_cycles;
 
    int  hush;                  /* Is simulator to do reg dumps */
    int  trace_phy;             /* Show physical instr addr when tracing */
    int  trace_virt;            /* Show virtual instr addr when tracing */
  } sim;
 
  struct
  {
    unsigned int  instr;        /* Current JTAG instruction */
    unsigned long int  mod_id;  /* Currently selected module */
    int  write_defined_p;       /* WRITE_COMMAND has set details for GO */
    unsigned char  acc_type;    /* Access type for GO */
    unsigned long int  addr;    /* Address to read/write for GO */
    unsigned long int  size;    /* Num bytes to read/write (up to 2^16) */
  } debug;
 
  struct
  {
    long long instructions;     /* Instructions executed */
    long long reset_instructions;
 
    int stalled;
    int halted;                 /* When library hits exit. */
    int hazardwait;             /* how many cycles were wasted because of hazards */
    int supercycles;            /* Superscalar cycles */
  } cpu;
 
  struct
  {                             /* Verification API, part of Adv Core Verif */
    int enabled;                /* Whether is VAPI module enabled */
    FILE *vapi_file;            /* vapi file */
    int server_port;            /* A user specified port number for services */
  } vapi;
 
/* CUC configuration parameters */
  struct
  {
    int mdelay[4];              /* average memory delays in cycles
                                   {read single, read burst, write single, write burst} */
    double cycle_duration;      /* in ns */
  } cuc;
};
 
/*! Union of all possible paramter values */
union param_val
{
  char          *str_val;
  int            int_val;
  long long int  longlong_val;
  oraddr_t       addr_val;
};
 
/*! Enum of all possible paramter types */
enum param_t
{
  PARAMT_NONE = 0,               /* No parameter */
  PARAMT_STR,                   /* String parm enclosed in double quotes (") */
  PARAMT_WORD,                  /* String parm NOT enclosed in double quotes */
  PARAMT_INT,                   /* Integer parameter */
  PARAMT_LONGLONG,              /* Long long int parameter */
  PARAMT_ADDR                   /* Address parameter */
};
 
/* Generic structure for a configuration section */
struct config_section
{
  char *name;
  void *(*sec_start) (void);
  void (*sec_end) (void *);
  void *dat;
  struct config_param *params;
  struct config_section *next;
};
 
/* Externally visible data structures*/
extern struct config          config;
extern struct runtime         runtime;
extern struct config_section *cur_section;
extern int                    do_stats;
 
/* Prototypes for external use */
extern void  set_config_command (int argc, char **argv);
extern void  init_defconfig (void);
extern int   parse_args (int argc, char *argv[]);
extern void  print_config (void);
extern void  reg_config_param (struct config_section *sec,
                               const char            *param,
                               enum param_t           type,
                               void (*param_cb)  (union param_val,
                                                  void *));
extern struct config_section *reg_config_sec (const char *section,
                                              void *(*sec_start) (void),
                                              void  (*sec_end) (void *));
 
extern void  reg_config_secs ();
 
#endif /* SIM_CONFIG_H */

Line No.	Rev	Author	Line
1	19	jeremybenn	`/* sim-config.h -- Simulator configuration header file`
2
3			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
4			`Copyright (C) 2008 Embecosm Limited`
5
6			`Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
7
8			`This file is part of OpenRISC 1000 Architectural Simulator.`
9
10			`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14
15			`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19
20			`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see <http://www.gnu.org/licenses/>. */`
22
23			`/* This program is commented throughout in a fashion suitable for processing`
24			`with Doxygen. */`
25
26
27			`#ifndef SIM_CONFIG_H`
28			`#define SIM_CONFIG_H`
29
30			`/* System includes */`
31			`#include <stdio.h>`
32
33			`/* Package includes */`
34			`#include "arch.h"`
35
36			`/* Simulator configuration macros. Eventually this one will be a lot bigger. */`
37
38			`#define MAX_SBUF_LEN 256 /* Max. length of store buffer */`
39
40			`#define EXE_LOG_HARDWARE 0 /* Print out RTL states */`
41			`#define EXE_LOG_SIMPLE 1 /* Executed log prints out dissasembly */`
42			`#define EXE_LOG_SOFTWARE 2 /* Simple with some register output */`
43
44			`#define STR_SIZE 256`
45
46			`/* Number of cycles between checks to runtime.sim.iprompt */`
47			`#define CHECK_INT_TIME 100000`
48
49	220	jeremybenn	`/* Print to the defined output stream */`
50	19	jeremybenn	`#define PRINTF(x...) fprintf (runtime.sim.fout, x)`
51
52	220	jeremybenn	`/* Print only if we are not running silently */`
53			`#define PRINTFQ(x...) if (!config.sim.quiet) { fprintf (runtime.sim.fout, x); }`
54
55	19	jeremybenn	`/! Data structure for configuration data /`
56			`struct config`
57			`{`
58			`struct`
59			`{ /* External linkage for SystemC */`
60	93	jeremybenn	`void *class_ptr;`
61			`int (read_up) (void class_ptr,`
62			`unsigned long int addr,`
63			`unsigned char mask[],`
64			`unsigned char rdata[],`
65			`int data_len);`
66			`int (write_up) (void class_ptr,`
67			`unsigned long int addr,`
68			`unsigned char mask[],`
69			`unsigned char wdata[],`
70			`int data_len);`
71	19	jeremybenn	`} ext;`
72
73			`struct`
74			`{`
75	143	jeremybenn	`int is_library; /* Library operation */`
76	19	jeremybenn	`int debug; /* Simulator debugging */`
77			`int verbose; /* Force verbose output */`
78
79			`int profile; /* Is profiler running */`
80			`char prof_fn; / Profiler filename */`
81
82			`int mprofile; /* Is memory profiler running */`
83			`char mprof_fn; / Memory profiler filename */`
84
85			`int history; /* instruction stream history analysis */`
86			`int exe_log; /* Print out RTL states? */`
87			`int exe_log_type; /* Type of log */`
88			`long long int exe_log_start; /* First instruction to log */`
89			`long long int exe_log_end; /* Last instr to log, -1 if continuous */`
90			`int exe_log_marker; /* If nonzero, place markers before */`
91			`/* each exe_log_marker instructions */`
92			`char exe_log_fn; / RTL state comparison filename */`
93	202	julius	`int exe_bin_insn_log; /* Binary dump log of exec. instructions */`
94			`char* exe_bin_insn_log_fn; /* Binary dump log of exec. instructions name */`
95	19	jeremybenn	`long clkcycle_ps; /* Clock duration in ps */`
96			`int strict_npc; /* JPB. NPC flushes pipeline when changed */`
97	220	jeremybenn	`int quiet; /* Minimize message output */`
98			`int report_mem_errs; /* Report out of memory accesses */`
99	19	jeremybenn	`} sim;`
100
101			`struct`
102			`{ /* Verification API */`
103			`int enabled; /* Whether is VAPI module enabled */`
104			`int server_port; /* user specified port for services */`
105			`int log_enabled; /* Whether to log the vapi requests */`
106			`int hide_device_id; /* Whether to log dev ID each request */`
107			`char vapi_fn; / vapi log filename */`
108			`} vapi;`
109
110			`struct`
111			`{`
112			`char timings_fn; / Filename of the timing table */`
113			`int memory_order; /* Memory access stricness */`
114			`int calling_convention; /* Do funcs follow std calling conv? */`
115			`int enable_bursts; /* Whether burst are enabled */`
116			`int no_multicycle; /* Generate no multicycle paths */`
117			`} cuc;`
118
119			`struct`
120			`{`
121			`int superscalar; /* superscalara analysis */`
122			`int hazards; /* dependency hazards analysis */`
123			`int dependstats; /* dependency statistics */`
124			`int sbuf_len; /* length of store buffer, 0=disabled */`
125	100	julius	`int hardfloat; /* whether hardfloat is enabled */`
126	19	jeremybenn	`} cpu;`
127
128			`struct`
129			`{`
130			`int enabled; /* Whether data cache is enabled */`
131			`int nways; /* Number of DC ways */`
132			`int nsets; /* Number of DC sets */`
133			`int blocksize; /* DC entry size */`
134			`int ustates; /* number of DC usage states */`
135			`int store_missdelay; /* cycles a store miss costs */`
136			`int store_hitdelay; /* cycles a store hit costs */`
137			`int load_missdelay; /* cycles a load miss costs */`
138			`int load_hitdelay; /* cycles a load hit costs */`
139			`} dc;`
140
141			`struct pic`
142			`{`
143			`int enabled; /* Is interrupt controller enabled? */`
144			`int edge_trigger; /* Are interrupts edge triggered? */`
145	432	jeremybenn	`int use_nmi; /* Do we have non-maskable interrupts? */`
146	19	jeremybenn	`} pic;`
147
148			`struct`
149			`{`
150			`int enabled; /* Is power management operational? */`
151			`} pm;`
152
153			`struct`
154			`{`
155	556	julius	`int enabled; /* Are performance counters enabled? */`
156			`} pcu;`
157
158			`struct`
159			`{`
160	19	jeremybenn	`int enabled; /* branch prediction buffer analysis */`
161			`int sbp_bnf_fwd; /* Static BP for l.bnf uses fwd predn */`
162			`int sbp_bf_fwd; /* Static BP for l.bf uses fwd predn */`
163			`int btic; /* BP target insn cache analysis */`
164			`int missdelay; /* How much cycles does the miss cost */`
165			`int hitdelay; /* How much cycles does the hit cost */`
166			`} bpb;`
167
168			`struct`
169			`{`
170			`int enabled; /* Is debug module enabled */`
171			`int rsp_enabled; /* Is RSP debugging with GDB possible */`
172			`int rsp_port; /* Port for RSP GDB connection */`
173			`unsigned long vapi_id; /* "Fake" vapi dev id for JTAG proxy */`
174	82	jeremybenn	`long int jtagcycle_ps; /* JTAG clock duration in ps */`
175	19	jeremybenn	`} debug;`
176			`};`
177
178			`/! Data structure for run time data /`
179			`struct runtime`
180			`{`
181			`struct`
182			`{`
183			`FILE fprof; / Profiler file */`
184			`FILE fmprof; / Memory profiler file */`
185			`FILE fexe_log; / RTL state comparison file */`
186	202	julius	`FILE fexe_bin_insn_log; / Binary instruction dump/log file */`
187	19	jeremybenn	`FILE fout; / file for standard output */`
188			`char filename; / Original Command Simulator file (CZ) */`
189			`int iprompt; /* Interactive prompt */`
190			`int iprompt_run; /* Interactive prompt is running */`
191			`long long cycles; /* Cycles counts fetch stages */`
192			`long long int end_cycles; /* JPB. Cycles to end of quantum */`
193			`double time_point; /* JPB. Time point in the simulation */`
194			`unsigned long int ext_int_set; /* JPB. External interrupts to set */`
195			`unsigned long int ext_int_clr; /* DXL. External interrupts ti clear */`
196
197			`int mem_cycles; /* Each cycle has counter of mem_cycles;`
198			`this value is joined with cycles`
199			`at the end of the cycle; no sim`
200			`originated memory accesses should be`
201			`performed inbetween. */`
202			`int loadcycles; /* Load and store stalls */`
203			`int storecycles;`
204
205			`long long reset_cycles;`
206
207			`int hush; /* Is simulator to do reg dumps */`
208	472	jeremybenn	`int trace_phy; /* Show physical instr addr when tracing */`
209			`int trace_virt; /* Show virtual instr addr when tracing */`
210	19	jeremybenn	`} sim;`
211
212			`struct`
213			`{`
214	82	jeremybenn	`unsigned int instr; /* Current JTAG instruction */`
215			`unsigned long int mod_id; /* Currently selected module */`
216			`int write_defined_p; /* WRITE_COMMAND has set details for GO */`
217			`unsigned char acc_type; /* Access type for GO */`
218			`unsigned long int addr; /* Address to read/write for GO */`
219	98	jeremybenn	`unsigned long int size; /* Num bytes to read/write (up to 2^16) */`
220	82	jeremybenn	`} debug;`
221
222			`struct`
223			`{`
224	19	jeremybenn	`long long instructions; /* Instructions executed */`
225			`long long reset_instructions;`
226
227			`int stalled;`
228	143	jeremybenn	`int halted; /* When library hits exit. */`
229	19	jeremybenn	`int hazardwait; /* how many cycles were wasted because of hazards */`
230			`int supercycles; /* Superscalar cycles */`
231			`} cpu;`
232
233			`struct`
234	235	jeremybenn	`{ /* Verification API, part of Adv Core Verif */`
235	19	jeremybenn	`int enabled; /* Whether is VAPI module enabled */`
236			`FILE vapi_file; / vapi file */`
237			`int server_port; /* A user specified port number for services */`
238			`} vapi;`
239
240			`/* CUC configuration parameters */`
241			`struct`
242			`{`
243			`int mdelay[4]; /* average memory delays in cycles`
244			`{read single, read burst, write single, write burst} */`
245			`double cycle_duration; /* in ns */`
246			`} cuc;`
247			`};`
248
249			`/! Union of all possible paramter values /`
250			`union param_val`
251			`{`
252			`char *str_val;`
253			`int int_val;`
254			`long long int longlong_val;`
255			`oraddr_t addr_val;`
256			`};`
257
258			`/! Enum of all possible paramter types /`
259			`enum param_t`
260			`{`
261	224	jeremybenn	`PARAMT_NONE = 0, /* No parameter */`
262			`PARAMT_STR, /* String parm enclosed in double quotes (") */`
263			`PARAMT_WORD, /* String parm NOT enclosed in double quotes */`
264			`PARAMT_INT, /* Integer parameter */`
265			`PARAMT_LONGLONG, /* Long long int parameter */`
266			`PARAMT_ADDR /* Address parameter */`
267	19	jeremybenn	`};`
268
269			`/* Generic structure for a configuration section */`
270			`struct config_section`
271			`{`
272			`char *name;`
273			`void (sec_start) (void);`
274			`void (sec_end) (void );`
275			`void *dat;`
276			`struct config_param *params;`
277			`struct config_section *next;`
278			`};`
279
280			`/* Externally visible data structures*/`
281			`extern struct config config;`
282			`extern struct runtime runtime;`
283			`extern struct config_section *cur_section;`
284			`extern int do_stats;`
285
286			`/* Prototypes for external use */`
287			`extern void set_config_command (int argc, char **argv);`
288			`extern void init_defconfig (void);`
289			`extern int parse_args (int argc, char *argv[]);`
290			`extern void print_config (void);`
291			`extern void reg_config_param (struct config_section *sec,`
292			`const char *param,`
293			`enum param_t type,`
294			`void (*param_cb) (union param_val,`
295			`void *));`
296			`extern struct config_section reg_config_sec (const char section,`
297			`void (sec_start) (void),`
298			`void (sec_end) (void ));`
299
300			`extern void reg_config_secs ();`
301
302			`#endif /* SIM_CONFIG_H */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.h] - Blame information for rev 850