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[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.h] - Blame information for rev 54

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/* sim-config.h -- Simulator configuration header file
 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2008 Embecosm Limited
 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */
 
 
#ifndef SIM_CONFIG_H
#define SIM_CONFIG_H
 
/* System includes */
#include <stdio.h>
 
/* Package includes */
#include "arch.h"
 
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
 
#define MAX_SBUF_LEN     256    /* Max. length of store buffer */
 
#define EXE_LOG_HARDWARE   0    /* Print out RTL states */
#define EXE_LOG_SIMPLE     1    /* Executed log prints out dissasembly */
#define EXE_LOG_SOFTWARE   2    /* Simple with some register output */
 
#define STR_SIZE         256
 
/* Number of cycles between checks to runtime.sim.iprompt */
#define CHECK_INT_TIME 100000
 
#define PRINTF(x...) fprintf (runtime.sim.fout, x)
 
/*! Data structure for configuration data */
struct config
{
  struct
  {                             /* External linkage for SystemC */
    void *class_ptr;
    unsigned long int (*read_up) (void *class_ptr,
                                  unsigned long int addr,
                                  unsigned long int mask);
    void (*write_up) (void *class_ptr,
                      unsigned long int addr,
                      unsigned long int mask, unsigned long int wdata);
  } ext;
 
  struct
  {
    int debug;                  /* Simulator debugging */
    int verbose;                /* Force verbose output */
 
    int profile;                /* Is profiler running */
    char *prof_fn;              /* Profiler filename */
 
    int mprofile;               /* Is memory profiler running */
    char *mprof_fn;             /* Memory profiler filename */
 
    int history;                /* instruction stream history analysis */
    int exe_log;                /* Print out RTL states? */
    int exe_log_type;           /* Type of log */
    long long int exe_log_start;        /* First instruction to log */
    long long int exe_log_end;  /* Last instr to log, -1 if continuous */
    int exe_log_marker;         /* If nonzero, place markers before */
    /* each exe_log_marker instructions */
    char *exe_log_fn;           /* RTL state comparison filename */
    long clkcycle_ps;           /* Clock duration in ps */
    int strict_npc;             /* JPB. NPC flushes pipeline when changed */
  } sim;
 
  struct
  {                             /* Verification API */
    int enabled;                /* Whether is VAPI module enabled */
    int server_port;            /* user specified port for services */
    int log_enabled;            /* Whether to log the vapi requests */
    int hide_device_id;         /* Whether to log dev ID each request */
    char *vapi_fn;              /* vapi log filename */
  } vapi;
 
  struct
  {
    char *timings_fn;           /* Filename of the timing table */
    int memory_order;           /* Memory access stricness */
    int calling_convention;     /* Do funcs follow std calling conv? */
    int enable_bursts;          /* Whether burst are enabled */
    int no_multicycle;          /* Generate no multicycle paths */
  } cuc;
 
  struct
  {
    int superscalar;            /* superscalara analysis */
    int hazards;                /* dependency hazards analysis */
    int dependstats;            /* dependency statistics */
    int sbuf_len;               /* length of store buffer, 0=disabled */
  } cpu;
 
  struct
  {
    int enabled;                /* Whether data cache is enabled */
    int nways;                  /* Number of DC ways */
    int nsets;                  /* Number of DC sets */
    int blocksize;              /* DC entry size */
    int ustates;                /* number of DC usage states */
    int store_missdelay;        /* cycles a store miss costs */
    int store_hitdelay;         /* cycles a store hit costs */
    int load_missdelay;         /* cycles a load miss costs */
    int load_hitdelay;          /* cycles a load hit costs */
  } dc;
 
  struct pic
  {
    int enabled;                /* Is interrupt controller enabled? */
    int edge_trigger;           /* Are interrupts edge triggered? */
  } pic;
 
  struct
  {
    int enabled;                /* Is power management operational? */
  } pm;
 
  struct
  {
    int enabled;                /* branch prediction buffer analysis */
    int sbp_bnf_fwd;            /* Static BP for l.bnf uses fwd predn */
    int sbp_bf_fwd;             /* Static BP for l.bf uses fwd predn */
    int btic;                   /* BP target insn cache analysis */
    int missdelay;              /* How much cycles does the miss cost */
    int hitdelay;               /* How much cycles does the hit cost */
  } bpb;
 
  struct
  {
    int enabled;                /* Is debug module enabled */
    int gdb_enabled;            /* Is legacy debugging with GDB possible */
    int rsp_enabled;            /* Is RSP debugging with GDB possible */
    int server_port;            /* Port for legacy GDB connection */
    int rsp_port;               /* Port for RSP GDB connection */
    unsigned long vapi_id;      /* "Fake" vapi dev id for JTAG proxy */
  } debug;
};
 
/*! Data structure for run time data */
struct runtime
{
  struct
  {
    FILE *fprof;                /* Profiler file */
    FILE *fmprof;               /* Memory profiler file */
    FILE *fexe_log;             /* RTL state comparison file */
    FILE *fout;                 /* file for standard output */
    char *filename;             /* Original Command Simulator file (CZ) */
    int iprompt;                /* Interactive prompt */
    int iprompt_run;            /* Interactive prompt is running */
    long long cycles;           /* Cycles counts fetch stages */
    long long int end_cycles;   /* JPB. Cycles to end of quantum */
    double time_point;          /* JPB. Time point in the simulation */
    unsigned long int ext_int_set;      /* JPB. External interrupts to set */
    unsigned long int ext_int_clr;      /* DXL. External interrupts ti clear */
 
    int mem_cycles;             /* Each cycle has counter of mem_cycles;
                                   this value is joined with cycles
                                   at the end of the cycle; no sim
                                   originated memory accesses should be
                                   performed inbetween. */
    int loadcycles;             /* Load and store stalls */
    int storecycles;
 
    long long reset_cycles;
 
    int  hush;                  /* Is simulator to do reg dumps */
  } sim;
 
  struct
  {
    long long instructions;     /* Instructions executed */
    long long reset_instructions;
 
    int stalled;
    int hazardwait;             /* how many cycles were wasted because of hazards */
    int supercycles;            /* Superscalar cycles */
  } cpu;
 
  struct
  {                             /* Verification API, part of Advanced Core Verification */
    int enabled;                /* Whether is VAPI module enabled */
    FILE *vapi_file;            /* vapi file */
    int server_port;            /* A user specified port number for services */
  } vapi;
 
/* CUC configuration parameters */
  struct
  {
    int mdelay[4];              /* average memory delays in cycles
                                   {read single, read burst, write single, write burst} */
    double cycle_duration;      /* in ns */
  } cuc;
};
 
/*! Union of all possible paramter values */
union param_val
{
  char          *str_val;
  int            int_val;
  long long int  longlong_val;
  oraddr_t       addr_val;
};
 
/*! Enum of all possible paramter types */
enum param_t
{
  paramt_none = 0,               /* No parameter */
  paramt_str,                   /* String parm enclosed in double quotes (") */
  paramt_word,                  /* String parm NOT enclosed in double quotes */
  paramt_int,                   /* Integer parameter */
  paramt_longlong,              /* Long long int parameter */
  paramt_addr                   /* Address parameter */
};
 
/* Generic structure for a configuration section */
struct config_section
{
  char *name;
  void *(*sec_start) (void);
  void (*sec_end) (void *);
  void *dat;
  struct config_param *params;
  struct config_section *next;
};
 
/* Externally visible data structures*/
extern struct config          config;
extern struct runtime         runtime;
extern struct config_section *cur_section;
extern int                    do_stats;
 
/* Prototypes for external use */
extern void  set_config_command (int argc, char **argv);
extern void  init_defconfig (void);
extern int   parse_args (int argc, char *argv[]);
extern void  print_config (void);
extern void  reg_config_param (struct config_section *sec,
                               const char            *param,
                               enum param_t           type,
                               void (*param_cb)  (union param_val,
                                                  void *));
extern struct config_section *reg_config_sec (const char *section,
                                              void *(*sec_start) (void),
                                              void  (*sec_end) (void *));
 
extern void  reg_config_secs ();
 
#endif /* SIM_CONFIG_H */

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.h] - Blame information for rev 54

Line No.	Rev	Author	Line
1	19	jeremybenn	`/* sim-config.h -- Simulator configuration header file`
2
3			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
4			`Copyright (C) 2008 Embecosm Limited`
5
6			`Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
7
8			`This file is part of OpenRISC 1000 Architectural Simulator.`
9
10			`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14
15			`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19
20			`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see <http://www.gnu.org/licenses/>. */`
22
23			`/* This program is commented throughout in a fashion suitable for processing`
24			`with Doxygen. */`
25
26
27			`#ifndef SIM_CONFIG_H`
28			`#define SIM_CONFIG_H`
29
30			`/* System includes */`
31			`#include <stdio.h>`
32
33			`/* Package includes */`
34			`#include "arch.h"`
35
36			`/* Simulator configuration macros. Eventually this one will be a lot bigger. */`
37
38			`#define MAX_SBUF_LEN 256 /* Max. length of store buffer */`
39
40			`#define EXE_LOG_HARDWARE 0 /* Print out RTL states */`
41			`#define EXE_LOG_SIMPLE 1 /* Executed log prints out dissasembly */`
42			`#define EXE_LOG_SOFTWARE 2 /* Simple with some register output */`
43
44			`#define STR_SIZE 256`
45
46			`/* Number of cycles between checks to runtime.sim.iprompt */`
47			`#define CHECK_INT_TIME 100000`
48
49			`#define PRINTF(x...) fprintf (runtime.sim.fout, x)`
50
51			`/! Data structure for configuration data /`
52			`struct config`
53			`{`
54			`struct`
55			`{ /* External linkage for SystemC */`
56			`void *class_ptr;`
57			`unsigned long int (read_up) (void class_ptr,`
58			`unsigned long int addr,`
59			`unsigned long int mask);`
60			`void (write_up) (void class_ptr,`
61			`unsigned long int addr,`
62			`unsigned long int mask, unsigned long int wdata);`
63			`} ext;`
64
65			`struct`
66			`{`
67			`int debug; /* Simulator debugging */`
68			`int verbose; /* Force verbose output */`
69
70			`int profile; /* Is profiler running */`
71			`char prof_fn; / Profiler filename */`
72
73			`int mprofile; /* Is memory profiler running */`
74			`char mprof_fn; / Memory profiler filename */`
75
76			`int history; /* instruction stream history analysis */`
77			`int exe_log; /* Print out RTL states? */`
78			`int exe_log_type; /* Type of log */`
79			`long long int exe_log_start; /* First instruction to log */`
80			`long long int exe_log_end; /* Last instr to log, -1 if continuous */`
81			`int exe_log_marker; /* If nonzero, place markers before */`
82			`/* each exe_log_marker instructions */`
83			`char exe_log_fn; / RTL state comparison filename */`
84			`long clkcycle_ps; /* Clock duration in ps */`
85			`int strict_npc; /* JPB. NPC flushes pipeline when changed */`
86			`} sim;`
87
88			`struct`
89			`{ /* Verification API */`
90			`int enabled; /* Whether is VAPI module enabled */`
91			`int server_port; /* user specified port for services */`
92			`int log_enabled; /* Whether to log the vapi requests */`
93			`int hide_device_id; /* Whether to log dev ID each request */`
94			`char vapi_fn; / vapi log filename */`
95			`} vapi;`
96
97			`struct`
98			`{`
99			`char timings_fn; / Filename of the timing table */`
100			`int memory_order; /* Memory access stricness */`
101			`int calling_convention; /* Do funcs follow std calling conv? */`
102			`int enable_bursts; /* Whether burst are enabled */`
103			`int no_multicycle; /* Generate no multicycle paths */`
104			`} cuc;`
105
106			`struct`
107			`{`
108			`int superscalar; /* superscalara analysis */`
109			`int hazards; /* dependency hazards analysis */`
110			`int dependstats; /* dependency statistics */`
111			`int sbuf_len; /* length of store buffer, 0=disabled */`
112			`} cpu;`
113
114			`struct`
115			`{`
116			`int enabled; /* Whether data cache is enabled */`
117			`int nways; /* Number of DC ways */`
118			`int nsets; /* Number of DC sets */`
119			`int blocksize; /* DC entry size */`
120			`int ustates; /* number of DC usage states */`
121			`int store_missdelay; /* cycles a store miss costs */`
122			`int store_hitdelay; /* cycles a store hit costs */`
123			`int load_missdelay; /* cycles a load miss costs */`
124			`int load_hitdelay; /* cycles a load hit costs */`
125			`} dc;`
126
127			`struct pic`
128			`{`
129			`int enabled; /* Is interrupt controller enabled? */`
130			`int edge_trigger; /* Are interrupts edge triggered? */`
131			`} pic;`
132
133			`struct`
134			`{`
135			`int enabled; /* Is power management operational? */`
136			`} pm;`
137
138			`struct`
139			`{`
140			`int enabled; /* branch prediction buffer analysis */`
141			`int sbp_bnf_fwd; /* Static BP for l.bnf uses fwd predn */`
142			`int sbp_bf_fwd; /* Static BP for l.bf uses fwd predn */`
143			`int btic; /* BP target insn cache analysis */`
144			`int missdelay; /* How much cycles does the miss cost */`
145			`int hitdelay; /* How much cycles does the hit cost */`
146			`} bpb;`
147
148			`struct`
149			`{`
150			`int enabled; /* Is debug module enabled */`
151			`int gdb_enabled; /* Is legacy debugging with GDB possible */`
152			`int rsp_enabled; /* Is RSP debugging with GDB possible */`
153			`int server_port; /* Port for legacy GDB connection */`
154			`int rsp_port; /* Port for RSP GDB connection */`
155			`unsigned long vapi_id; /* "Fake" vapi dev id for JTAG proxy */`
156			`} debug;`
157			`};`
158
159			`/! Data structure for run time data /`
160			`struct runtime`
161			`{`
162			`struct`
163			`{`
164			`FILE fprof; / Profiler file */`
165			`FILE fmprof; / Memory profiler file */`
166			`FILE fexe_log; / RTL state comparison file */`
167			`FILE fout; / file for standard output */`
168			`char filename; / Original Command Simulator file (CZ) */`
169			`int iprompt; /* Interactive prompt */`
170			`int iprompt_run; /* Interactive prompt is running */`
171			`long long cycles; /* Cycles counts fetch stages */`
172			`long long int end_cycles; /* JPB. Cycles to end of quantum */`
173			`double time_point; /* JPB. Time point in the simulation */`
174			`unsigned long int ext_int_set; /* JPB. External interrupts to set */`
175			`unsigned long int ext_int_clr; /* DXL. External interrupts ti clear */`
176
177			`int mem_cycles; /* Each cycle has counter of mem_cycles;`
178			`this value is joined with cycles`
179			`at the end of the cycle; no sim`
180			`originated memory accesses should be`
181			`performed inbetween. */`
182			`int loadcycles; /* Load and store stalls */`
183			`int storecycles;`
184
185			`long long reset_cycles;`
186
187			`int hush; /* Is simulator to do reg dumps */`
188			`} sim;`
189
190			`struct`
191			`{`
192			`long long instructions; /* Instructions executed */`
193			`long long reset_instructions;`
194
195			`int stalled;`
196			`int hazardwait; /* how many cycles were wasted because of hazards */`
197			`int supercycles; /* Superscalar cycles */`
198			`} cpu;`
199
200			`struct`
201			`{ /* Verification API, part of Advanced Core Verification */`
202			`int enabled; /* Whether is VAPI module enabled */`
203			`FILE vapi_file; / vapi file */`
204			`int server_port; /* A user specified port number for services */`
205			`} vapi;`
206
207			`/* CUC configuration parameters */`
208			`struct`
209			`{`
210			`int mdelay[4]; /* average memory delays in cycles`
211			`{read single, read burst, write single, write burst} */`
212			`double cycle_duration; /* in ns */`
213			`} cuc;`
214			`};`
215
216			`/! Union of all possible paramter values /`
217			`union param_val`
218			`{`
219			`char *str_val;`
220			`int int_val;`
221			`long long int longlong_val;`
222			`oraddr_t addr_val;`
223			`};`
224
225			`/! Enum of all possible paramter types /`
226			`enum param_t`
227			`{`
228			`paramt_none = 0, /* No parameter */`
229			`paramt_str, /* String parm enclosed in double quotes (") */`
230			`paramt_word, /* String parm NOT enclosed in double quotes */`
231			`paramt_int, /* Integer parameter */`
232			`paramt_longlong, /* Long long int parameter */`
233			`paramt_addr /* Address parameter */`
234			`};`
235
236			`/* Generic structure for a configuration section */`
237			`struct config_section`
238			`{`
239			`char *name;`
240			`void (sec_start) (void);`
241			`void (sec_end) (void );`
242			`void *dat;`
243			`struct config_param *params;`
244			`struct config_section *next;`
245			`};`
246
247			`/* Externally visible data structures*/`
248			`extern struct config config;`
249			`extern struct runtime runtime;`
250			`extern struct config_section *cur_section;`
251			`extern int do_stats;`
252
253			`/* Prototypes for external use */`
254			`extern void set_config_command (int argc, char **argv);`
255			`extern void init_defconfig (void);`
256			`extern int parse_args (int argc, char *argv[]);`
257			`extern void print_config (void);`
258			`extern void reg_config_param (struct config_section *sec,`
259			`const char *param,`
260			`enum param_t type,`
261			`void (*param_cb) (union param_val,`
262			`void *));`
263			`extern struct config_section reg_config_sec (const char section,`
264			`void (sec_start) (void),`
265			`void (sec_end) (void ));`
266
267			`extern void reg_config_secs ();`
268
269			`#endif /* SIM_CONFIG_H */`