URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [sim.cfg] - Blame information for rev 540

Go to most recent revision | Details | Compare with Previous | View Log


/* sim.cfg -- Simulator configuration script file
 
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
   Copyright (C) 2010, Embecosm Limited
 
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see . */
 
 
/* -------------------------------------------------------------------------- */
/* The Ork1sim has various parameters, that can be set in configuration files
   like this one. The user can specify a configuration file at startu[ with
   the -f  option.
 
   The user guide (see the 'doc' directory) gives full details on
   configuration files. This is a reference configuration, which may be used
   as a starting point for customization.
 
   A number of peripherals are mapped at standard addresses (above 0x80000000)
   in the Verilog RTL of ORPSoC standard sitribution. The same values should
   be used in Or1ksim section definitions to match the behavior of the Verilog
 
      0x90000000 UART
      0x91000000 GPIO
      0x92000000 Ethernet
      0x93000000 Memory controller
      0x94000000 PS2 keyboard
      0x97000000 Frame buffer
      0x97100000 VGA
      0x9a000000 DMA controller
      0x9e000000 ATA disc
 
   Section ordering matches that in the user guide. All optional peripherals
   and functionality is disabled. Comments only list the possible entries and
   values. Consult the user guide for their meaning.
 
   Unless otherwise indicated, the first named option is the default.         */
/* -------------------------------------------------------------------------- */
 
 
/* Simulator section
 
   verbose               = 0|1
   debug                 = 0-9
   profile               = 0|1
   prof_file             = "" (default: "sim.profile")
   mprofile              = 0|1
   mprof_file            = "" (default: "sim.mprofile")
   history               = 0|1
   exe_log               = 0|1
   exe_log_type          = hardware|simple|software|default
   exe_log_start         =  (default: 0)
   exe_log_end           =  (default: never end)
   exe_log_marker        =  (default: no markers)
   exe_log_file          = "" (default: "executed.log")
   exe_bin_insn_log      = 0|1
   exe_bin_insn_log_file = "" (default: "exe-insn.bin")
   clkcycle              = [ps|ns|us|ms]
*/
section sim
  clkcycle = 100ns
end
 
 
/* VAPI section
 
   enabled        = 0|1
   server_port    =  (default: 50000)
   log_enabled    = 0|1
   hide_device_id = 0|1
   vapi_log_file  = "" (default "vapi.log")
*/
section VAPI
  server_port = 50000
  log_enabled = 0
  vapi_log_file = "vapi.log"
end
 
 
/* CUC section
 
    memory_order       = none|weak|strong|exact (default: strong)
    calling_convention = 0|1
    enable_bursts      = 0|1
    no_multicycle      = 0|1
    timings_file       = "" (default: virtex.tim)
*/
section cuc
  memory_order       = weak
  calling_convention = 1
  enable_bursts      = 1
  no_multicycle      = 1
end
 
 
/* CPU section
 
   ver         =  (default: 0)
   cfg         =  (default: 0)
   rev         =  (default: 0)
   upr         =  (see user manual for default settings)
   cfgr        =  (default: 0x00000020)
   sr          =  (default: 0x00008001)
   superscalar = 0|1
   hazards     = 0|1
   dependstats = 0|1
   sbuf_len    =  (default: 0)
   hardfloat   = 0|1
*/
section cpu
  ver = 0x12
  cfg = 0x00
  rev = 0x0001
end
 
 
/* Memory section
 
   type        = unknown|random|unknown|pattern
   random_seed =  (default: -1)
   pattern     =  (default: 0)
   baseaddr    =  (default: 0)
   size        =  (default: 1024)
   name        = "" (default: "anonymous memory block")
   ce          =  (default: -1)
   mc          =  (default: 0)
   delayr      =  (default: 1)
   delayw      =  (default: 1)
   log         = "" (default: NULL)
*/
section memory
  name        = "RAM"
  type        = unknown
  baseaddr    = 0x00000000
  size        = 0x00800000
  delayr      = 1
  delayw      = 2
end
 
 
/* Data MMU section
 
   enabled   = 0|1
   nsets     =  (default: 1)
   nways     =  (default: 1)
   pagesize  =  (default: 8192)
   entrysize =  (default: 1)
   ustates   =  (default: 1)
   hitdelay  =  (default: 1)
   missdelay =  (default: 1)
*/
section dmmu
  enabled   = 0
  nsets     = 64
  nways     = 1
  pagesize  = 8192
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Instruction MMU section
 
   enabled   = 0|1
   nsets     =  (default: 1)
   nways     =  (default: 1)
   pagesize  =  (default: 8192)
   entrysize =  (default: 1)
   ustates   =  (default: 1)
   hitdelay  =  (default: 1)
   missdelay =  (default: 1)
*/
section immu
  enabled   = 0
  nsets     = 64
  nways     = 1
  pagesize  = 8192
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Data cache section
 
   enabled         = 0|1
   nsets           =  (default: 1)
   nways           =  (default: 1)
   blocksize       =  (default: 16)
   ustates         =  (default: 2)
   load_hitdelay   =  (default: 2)
   load_missdelay  =  (default: 2)
   store_hitdelay  =  (default: 0)
   store_missdelay =  (default: 0)
*/
 
section dc
  enabled         = 0
  nsets           = 256
  nways           = 1
  blocksize       = 16
  load_hitdelay   = 0
  load_missdelay  = 0
  store_hitdelay  = 0
  store_missdelay = 0
end
 
 
/* Instruction cache section
 
   enabled    = 0|1
   nsets      =  (default: 1)
   nways      =  (default: 1)
   blocksize  =  (default: 16)
   ustates    =  (default: 2)
   hitdelay   =  (default: 1)
   missdelay  =  (default: 1)
*/
section ic
  enabled   = 0
  nsets     = 256
  nways     = 1
  blocksize = 16
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Programmable interrupt controller section
 
  enabled      = 0|1
  edge_trigger = 0|1 (default: 1)
*/
 
section pic
  enabled = 0
end
 
 
/* Power management section
 
   enabled = 0|1
*/
 
section pm
  enabled = 0
end
 
 
/* Branch prediction section
 
   enabled     = 0|1
   btic        = 0|1
   sbp_bf_fwd  = 0|1
   sbp_bnf_fwd = 0|1
   hitdelay    =  (default: 0)
   missdelay   =  (default: 0)
*/
 
section bpb
  enabled = 0
end
 
 
/* Debug unit section
 
   enabled     = 0|1
   rsp_enabled = 0|1
   rsp_port    =  (default: 51000)
   vapi_id     =  (default: 0)
*/
section debug
  enabled = 0
end
 
 
/* Memory controller section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   POC      =  (default: 0)
   index    =  (default: 0)
*/
 
section mc
  enabled  = 0
  baseaddr = 0x93000000
  POC      = 0x0000000a                 /* 32 bit SSRAM */
  index    = 0
end
 
 
/* UART section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   channel  = "value>" (default: "xterm:")
   irq      =  (default: 0)
   16550    = 0|1
   jitter   =  (default: 0)
   vapi_id  =  (default: 0)
*/
 
section uart
  enabled  = 0
  baseaddr = 0x90000000
  irq      = 2
  16550    = 1
end
 
 
/* DMA section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   irq      =  (default: 0)
   vapi_id  =  (default: 0)
*/
section dma
  enabled  = 0
  baseaddr = 0x9a000000
  irq      = 11
end
 
 
/* Ethernet section
 
   enabled    = 0|1
   baseaddr   =  (default: 0)
   dma        =  (default: 0)
   irq        =  (default: 0)
   rtx_type   = 0|1
   rx_channel =  (default: 0)
   tx_channel =  (default: 0)
   rxfile     = "" (default: "eth_rx")
   txfile     = "" (default: "eth_rx")
   sockif     = "" (default: "or1ksim_eth")
   vapi_id    =  (default: 0)
*/
section ethernet
  enabled  = 0
  baseaddr = 0x92000000
  irq      = 4
  rtx_type = 0
end
 
 
/* GPIO section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   irq          =  (default: 0)
   base_vapi_id =  (default: 0)
*/
section gpio
  enabled      = 0
  baseaddr     = 0x91000000
  irq          = 3
  base_vapi_id = 0x0200
end
 
/* VGA section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   irq          =  (default: 0)
   refresh_rate =  (default: cycles equivalent to 50Hz)
   filename     = "" (default: "vga_out))
*/
section vga
  enabled      = 0
  baseaddr     = 0x97100000
  irq          = 8
end
 
 
/* Frame buffer section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   refresh_rate =  (default: cycles equivalent to 50Hz)
   filename     = "" (default: "fb_out))
*/
section fb
  enabled      = 0
  baseaddr     = 0x97000000
end
 
 
/* PS2 keyboard section
 
    This section configures the PS/2 compatible keyboard
 
    enabled  = 0|1
    baseaddr =  (default: 0)
    irq      =  (default: 0)
    rxfile   = "" (default: "kbd_in")
*/
section kbd
  enabled  = 1
  baseaddr = 0x94000000
  irq      = 5
end
 
 
/* ATA disc section
 
   enabled        = 0|1
   baseaddr       =  (default: 0)
   irq            =  (default: 0)
   dev_id         = 1|2|3
   rev            = 0-15 (default: 1)
   pio_mode0_t1   = 0-255 (default: 6)
   pio_mode0_t2   = 0-255 (default: 28)
   pio_mode0_t4   = 0-255 (default: 2)
   pio_mode0_teoc = 0-255 (default: 23)
   dma_mode0_tm   = 0-255 (default: 4)
   dma_mode0_td   = 0-255 (default: 21)
   dma_mode0_teoc = 0-255 (default: 21)
   device         = 0|1
 
   Device specific:
 
      type     = 0|1|2
      file     = "" (default: "ata_file")
      size     =  (default: 0)
      packet   = 0|1
      firmware = "" (default: "02207031")
      heads    =  (default: 7)
      sectors  =  (default: 32)
      mwdma    = 2|1|0|-1
      pio      = 4|3|2|1|0
*/
section ata
  enabled  = 0
  baseaddr = 0x9e000000
  irq      = 15
 
  device 0
    type = 1
    size = 1
  enddevice
end
 
 
/* Generic peripheral section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   size         =  (default: 0)
   name         = "" (default: "anonymous external peripheral")
   byte_enabled = 1|0
   hw_enabled   = 1|0
   word_enabled = 1|0
*/
section generic
  enabled  = 0
end

Line No.	Rev	Author	Line
1	19	jeremybenn	`/* sim.cfg -- Simulator configuration script file`
2	346	jeremybenn
3	19	jeremybenn	`Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org`
4	346	jeremybenn	`Copyright (C) 2010, Embecosm Limited`
5	19	jeremybenn
6	346	jeremybenn	`Contributor Jeremy Bennett`
7	19	jeremybenn
8	346	jeremybenn	`This file is part of OpenRISC 1000 Architectural Simulator.`
9
10			`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14
15			`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19
20			`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see . */`
22	19	jeremybenn
23
24	346	jeremybenn	`/* -------------------------------------------------------------------------- */`
25			`/* The Ork1sim has various parameters, that can be set in configuration files`
26			`like this one. The user can specify a configuration file at startu[ with`
27			`the -f option.`
28	19	jeremybenn
29	346	jeremybenn	`The user guide (see the 'doc' directory) gives full details on`
30			`configuration files. This is a reference configuration, which may be used`
31			`as a starting point for customization.`
32	19	jeremybenn
33	346	jeremybenn	`A number of peripherals are mapped at standard addresses (above 0x80000000)`
34			`in the Verilog RTL of ORPSoC standard sitribution. The same values should`
35			`be used in Or1ksim section definitions to match the behavior of the Verilog`
36	19	jeremybenn
37	346	jeremybenn	`0x90000000 UART`
38			`0x91000000 GPIO`
39			`0x92000000 Ethernet`
40			`0x93000000 Memory controller`
41			`0x94000000 PS2 keyboard`
42			`0x97000000 Frame buffer`
43			`0x97100000 VGA`
44			`0x9a000000 DMA controller`
45			`0x9e000000 ATA disc`
46	19	jeremybenn
47	346	jeremybenn	`Section ordering matches that in the user guide. All optional peripherals`
48			`and functionality is disabled. Comments only list the possible entries and`
49			`values. Consult the user guide for their meaning.`
50	19	jeremybenn
51	346	jeremybenn	`Unless otherwise indicated, the first named option is the default. */`
52			`/* -------------------------------------------------------------------------- */`
53	19	jeremybenn
54
55	346	jeremybenn	`/* Simulator section`
56	19	jeremybenn
57	346	jeremybenn	`verbose = 0\|1`
58			`debug = 0-9`
59			`profile = 0\|1`
60			`prof_file = "" (default: "sim.profile")`
61			`mprofile = 0\|1`
62			`mprof_file = "" (default: "sim.mprofile")`
63			`history = 0\|1`
64			`exe_log = 0\|1`
65			`exe_log_type = hardware\|simple\|software\|default`
66			`exe_log_start = (default: 0)`
67			`exe_log_end = (default: never end)`
68			`exe_log_marker = (default: no markers)`
69			`exe_log_file = "" (default: "executed.log")`
70			`exe_bin_insn_log = 0\|1`
71			`exe_bin_insn_log_file = "" (default: "exe-insn.bin")`
72			`clkcycle = [ps\|ns\|us\|ms]`
73	19	jeremybenn	`*/`
74	346	jeremybenn	`section sim`
75			`clkcycle = 100ns`
76			`end`
77	19	jeremybenn
78
79	346	jeremybenn	`/* VAPI section`
80	19	jeremybenn
81	346	jeremybenn	`enabled = 0\|1`
82			`server_port = (default: 50000)`
83			`log_enabled = 0\|1`
84			`hide_device_id = 0\|1`
85			`vapi_log_file = "" (default "vapi.log")`
86			`*/`
87			`section VAPI`
88			`server_port = 50000`
89			`log_enabled = 0`
90			`vapi_log_file = "vapi.log"`
91			`end`
92	19	jeremybenn
93
94	346	jeremybenn	`/* CUC section`
95	19	jeremybenn
96	346	jeremybenn	`memory_order = none\|weak\|strong\|exact (default: strong)`
97			`calling_convention = 0\|1`
98			`enable_bursts = 0\|1`
99			`no_multicycle = 0\|1`
100			`timings_file = "" (default: virtex.tim)`
101			`*/`
102			`section cuc`
103			`memory_order = weak`
104			`calling_convention = 1`
105			`enable_bursts = 1`
106			`no_multicycle = 1`
107			`end`
108	19	jeremybenn
109
110	346	jeremybenn	`/* CPU section`
111	19	jeremybenn
112	346	jeremybenn	`ver = (default: 0)`
113			`cfg = (default: 0)`
114			`rev = (default: 0)`
115			`upr = (see user manual for default settings)`
116			`cfgr = (default: 0x00000020)`
117			`sr = (default: 0x00008001)`
118			`superscalar = 0\|1`
119			`hazards = 0\|1`
120			`dependstats = 0\|1`
121			`sbuf_len = (default: 0)`
122			`hardfloat = 0\|1`
123			`*/`
124			`section cpu`
125			`ver = 0x12`
126			`cfg = 0x00`
127			`rev = 0x0001`
128			`end`
129	19	jeremybenn
130
131	346	jeremybenn	`/* Memory section`
132	19	jeremybenn
133	346	jeremybenn	`type = unknown\|random\|unknown\|pattern`
134			`random_seed = (default: -1)`
135			`pattern = (default: 0)`
136			`baseaddr = (default: 0)`
137			`size = (default: 1024)`
138			`name = "" (default: "anonymous memory block")`
139			`ce = (default: -1)`
140			`mc = (default: 0)`
141			`delayr = (default: 1)`
142			`delayw = (default: 1)`
143			`log = "" (default: NULL)`
144	19	jeremybenn	`*/`
145			`section memory`
146			`name = "RAM"`
147	346	jeremybenn	`type = unknown`
148	19	jeremybenn	`baseaddr = 0x00000000`
149	346	jeremybenn	`size = 0x00800000`
150	19	jeremybenn	`delayr = 1`
151			`delayw = 2`
152			`end`
153
154
155	346	jeremybenn	`/* Data MMU section`
156	19	jeremybenn
157	346	jeremybenn	`enabled = 0\|1`
158			`nsets = (default: 1)`
159			`nways = (default: 1)`
160			`pagesize = (default: 8192)`
161			`entrysize = (default: 1)`
162			`ustates = (default: 1)`
163			`hitdelay = (default: 1)`
164			`missdelay = (default: 1)`
165	19	jeremybenn	`*/`
166			`section dmmu`
167	346	jeremybenn	`enabled = 0`
168			`nsets = 64`
169			`nways = 1`
170			`pagesize = 8192`
171			`hitdelay = 0`
172	19	jeremybenn	`missdelay = 0`
173			`end`
174
175
176	346	jeremybenn	`/* Instruction MMU section`
177	19	jeremybenn
178	346	jeremybenn	`enabled = 0\|1`
179			`nsets = (default: 1)`
180			`nways = (default: 1)`
181			`pagesize = (default: 8192)`
182			`entrysize = (default: 1)`
183			`ustates = (default: 1)`
184			`hitdelay = (default: 1)`
185			`missdelay = (default: 1)`
186	19	jeremybenn	`*/`
187	346	jeremybenn	`section immu`
188			`enabled = 0`
189			`nsets = 64`
190			`nways = 1`
191			`pagesize = 8192`
192			`hitdelay = 0`
193	19	jeremybenn	`missdelay = 0`
194			`end`
195
196
197	346	jeremybenn	`/* Data cache section`
198	19	jeremybenn
199	346	jeremybenn	`enabled = 0\|1`
200			`nsets = (default: 1)`
201			`nways = (default: 1)`
202			`blocksize = (default: 16)`
203			`ustates = (default: 2)`
204			`load_hitdelay = (default: 2)`
205			`load_missdelay = (default: 2)`
206			`store_hitdelay = (default: 0)`
207			`store_missdelay = (default: 0)`
208	19	jeremybenn	`*/`
209
210			`section dc`
211	346	jeremybenn	`enabled = 0`
212			`nsets = 256`
213			`nways = 1`
214			`blocksize = 16`
215			`load_hitdelay = 0`
216			`load_missdelay = 0`
217			`store_hitdelay = 0`
218	19	jeremybenn	`store_missdelay = 0`
219			`end`
220
221
222	346	jeremybenn	`/* Instruction cache section`
223	19	jeremybenn
224	346	jeremybenn	`enabled = 0\|1`
225			`nsets = (default: 1)`
226			`nways = (default: 1)`
227			`blocksize = (default: 16)`
228			`ustates = (default: 2)`
229			`hitdelay = (default: 1)`
230			`missdelay = (default: 1)`
231	19	jeremybenn	`*/`
232	346	jeremybenn	`section ic`
233			`enabled = 0`
234			`nsets = 256`
235			`nways = 1`
236			`blocksize = 16`
237			`hitdelay = 0`
238			`missdelay = 0`
239	19	jeremybenn	`end`
240
241
242	346	jeremybenn	`/* Programmable interrupt controller section`
243	19	jeremybenn
244	346	jeremybenn	`enabled = 0\|1`
245			`edge_trigger = 0\|1 (default: 1)`
246	19	jeremybenn	`*/`
247
248	346	jeremybenn	`section pic`
249	19	jeremybenn	`enabled = 0`
250			`end`
251
252
253	346	jeremybenn	`/* Power management section`
254	19	jeremybenn
255	346	jeremybenn	`enabled = 0\|1`
256	19	jeremybenn	`*/`
257
258			`section pm`
259	346	jeremybenn	`enabled = 0`
260	19	jeremybenn	`end`
261
262
263	346	jeremybenn	`/* Branch prediction section`
264	19	jeremybenn
265	346	jeremybenn	`enabled = 0\|1`
266			`btic = 0\|1`
267			`sbp_bf_fwd = 0\|1`
268			`sbp_bnf_fwd = 0\|1`
269			`hitdelay = (default: 0)`
270			`missdelay = (default: 0)`
271	19	jeremybenn	`*/`
272
273			`section bpb`
274	346	jeremybenn	`enabled = 0`
275	19	jeremybenn	`end`
276
277
278	346	jeremybenn	`/* Debug unit section`
279	19	jeremybenn
280	346	jeremybenn	`enabled = 0\|1`
281			`rsp_enabled = 0\|1`
282			`rsp_port = (default: 51000)`
283			`vapi_id = (default: 0)`
284	19	jeremybenn	`*/`
285			`section debug`
286			`enabled = 0`
287			`end`
288
289
290	346	jeremybenn	`/* Memory controller section`
291	19	jeremybenn
292	346	jeremybenn	`enabled = 0\|1`
293			`baseaddr = (default: 0)`
294			`POC = (default: 0)`
295			`index = (default: 0)`
296	19	jeremybenn	`*/`
297
298			`section mc`
299	346	jeremybenn	`enabled = 0`
300	19	jeremybenn	`baseaddr = 0x93000000`
301	346	jeremybenn	`POC = 0x0000000a /* 32 bit SSRAM */`
302			`index = 0`
303	19	jeremybenn	`end`
304
305
306	346	jeremybenn	`/* UART section`
307	19	jeremybenn
308	346	jeremybenn	`enabled = 0\|1`
309			`baseaddr = (default: 0)`
310			`channel = "value>" (default: "xterm:")`
311			`irq = (default: 0)`
312			`16550 = 0\|1`
313			`jitter = (default: 0)`
314			`vapi_id = (default: 0)`
315	19	jeremybenn	`*/`
316
317			`section uart`
318	346	jeremybenn	`enabled = 0`
319	19	jeremybenn	`baseaddr = 0x90000000`
320	346	jeremybenn	`irq = 2`
321			`16550 = 1`
322	19	jeremybenn	`end`
323
324
325	346	jeremybenn	`/* DMA section`
326	19	jeremybenn
327	346	jeremybenn	`enabled = 0\|1`
328			`baseaddr = (default: 0)`
329			`irq = (default: 0)`
330			`vapi_id = (default: 0)`
331	19	jeremybenn	`*/`
332			`section dma`
333	346	jeremybenn	`enabled = 0`
334	19	jeremybenn	`baseaddr = 0x9a000000`
335	346	jeremybenn	`irq = 11`
336	19	jeremybenn	`end`
337
338
339	346	jeremybenn	`/* Ethernet section`
340	19	jeremybenn
341	346	jeremybenn	`enabled = 0\|1`
342			`baseaddr = (default: 0)`
343			`dma = (default: 0)`
344			`irq = (default: 0)`
345			`rtx_type = 0\|1`
346			`rx_channel = (default: 0)`
347			`tx_channel = (default: 0)`
348			`rxfile = "" (default: "eth_rx")`
349			`txfile = "" (default: "eth_rx")`
350			`sockif = "" (default: "or1ksim_eth")`
351			`vapi_id = (default: 0)`
352	19	jeremybenn	`*/`
353			`section ethernet`
354	346	jeremybenn	`enabled = 0`
355	19	jeremybenn	`baseaddr = 0x92000000`
356	346	jeremybenn	`irq = 4`
357	19	jeremybenn	`rtx_type = 0`
358			`end`
359
360
361	346	jeremybenn	`/* GPIO section`
362	19	jeremybenn
363	346	jeremybenn	`enabled = 0\|1`
364			`baseaddr = (default: 0)`
365			`irq = (default: 0)`
366			`base_vapi_id = (default: 0)`
367	19	jeremybenn	`*/`
368			`section gpio`
369	346	jeremybenn	`enabled = 0`
370			`baseaddr = 0x91000000`
371			`irq = 3`
372	19	jeremybenn	`base_vapi_id = 0x0200`
373			`end`
374
375	346	jeremybenn	`/* VGA section`
376	19	jeremybenn
377	346	jeremybenn	`enabled = 0\|1`
378			`baseaddr = (default: 0)`
379			`irq = (default: 0)`
380			`refresh_rate = (default: cycles equivalent to 50Hz)`
381			`filename = "" (default: "vga_out))`
382	19	jeremybenn	`*/`
383			`section vga`
384	346	jeremybenn	`enabled = 0`
385			`baseaddr = 0x97100000`
386			`irq = 8`
387	19	jeremybenn	`end`
388
389
390	346	jeremybenn	`/* Frame buffer section`
391	19	jeremybenn
392	346	jeremybenn	`enabled = 0\|1`
393			`baseaddr = (default: 0)`
394			`refresh_rate = (default: cycles equivalent to 50Hz)`
395			`filename = "" (default: "fb_out))`
396	19	jeremybenn	`*/`
397			`section fb`
398	346	jeremybenn	`enabled = 0`
399			`baseaddr = 0x97000000`
400	19	jeremybenn	`end`
401
402
403	346	jeremybenn	`/* PS2 keyboard section`
404	19	jeremybenn
405			`This section configures the PS/2 compatible keyboard`
406
407	346	jeremybenn	`enabled = 0\|1`
408			`baseaddr = (default: 0)`
409			`irq = (default: 0)`
410			`rxfile = "" (default: "kbd_in")`
411	19	jeremybenn	`*/`
412			`section kbd`
413	346	jeremybenn	`enabled = 1`
414	19	jeremybenn	`baseaddr = 0x94000000`
415	346	jeremybenn	`irq = 5`
416	19	jeremybenn	`end`
417
418
419	346	jeremybenn	`/* ATA disc section`
420	19	jeremybenn
421	346	jeremybenn	`enabled = 0\|1`
422			`baseaddr = (default: 0)`
423			`irq = (default: 0)`
424			`dev_id = 1\|2\|3`
425			`rev = 0-15 (default: 1)`
426			`pio_mode0_t1 = 0-255 (default: 6)`
427			`pio_mode0_t2 = 0-255 (default: 28)`
428			`pio_mode0_t4 = 0-255 (default: 2)`
429			`pio_mode0_teoc = 0-255 (default: 23)`
430			`dma_mode0_tm = 0-255 (default: 4)`
431			`dma_mode0_td = 0-255 (default: 21)`
432			`dma_mode0_teoc = 0-255 (default: 21)`
433			`device = 0\|1`
434	19	jeremybenn
435	346	jeremybenn	`Device specific:`
436	19	jeremybenn
437	346	jeremybenn	`type = 0\|1\|2`
438			`file = "" (default: "ata_file")`
439			`size = (default: 0)`
440			`packet = 0\|1`
441			`firmware = "" (default: "02207031")`
442			`heads = (default: 7)`
443			`sectors = (default: 32)`
444			`mwdma = 2\|1\|0\|-1`
445			`pio = 4\|3\|2\|1\|0`
446	19	jeremybenn	`*/`
447			`section ata`
448	346	jeremybenn	`enabled = 0`
449	19	jeremybenn	`baseaddr = 0x9e000000`
450	346	jeremybenn	`irq = 15`
451	19	jeremybenn
452			`device 0`
453	346	jeremybenn	`type = 1`
454			`size = 1`
455	19	jeremybenn	`enddevice`
456			`end`
457
458
459	346	jeremybenn	`/* Generic peripheral section`
460
461			`enabled = 0\|1`
462			`baseaddr = (default: 0)`
463			`size = (default: 0)`
464			`name = "" (default: "anonymous external peripheral")`
465			`byte_enabled = 1\|0`
466			`hw_enabled = 1\|0`
467			`word_enabled = 1\|0`
468	19	jeremybenn	`*/`
469	346	jeremybenn	`section generic`
470			`enabled = 0`
471	19	jeremybenn	`end`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [sim.cfg] - Blame information for rev 540