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1 19 jeremybenn
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
It contains the default configuration and help about configuring
6
the simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41
 
42
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44
 
45
   Some section have subsections. One example of such a subsection is:
46
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54
 
55
/* MEMORY SECTION
56
 
57
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59
 
60
   type = random/unknown/pattern
61
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67
 
68
   random_seed = 
69
      random seed for randomizer, used if type = 'random'.
70
 
71
   pattern = 
72
      pattern to fill memory, used if type = 'pattern'.
73
 
74
   baseaddr = 
75
      memory start address
76
 
77
   size = 
78
      memory size
79
 
80
   name = ""
81
      memory block name
82
 
83
   ce = 
84
      chip enable index of the memory instance
85
 
86
   mc = 
87
      memory controller this memory is connected to
88
 
89
   delayr = 
90
      cycles, required for read access, -1 if instance does not support reading
91
 
92
   delayw = 
93
      cycles, required for write access, -1 if instance does not support
94
      writing
95
 
96
   log = ""
97
      filename, where to log memory accesses to. If log command is not
98
      specified, accesses are not logged.
99
*/
100
 
101
 
102
section memory
103
  name        = "RAM"
104
  random_seed = 12345
105
  type        = random
106
  ce          = 0
107
  mc          = 0
108
  baseaddr    = 0x00000000
109
  size        = 0x00400000
110
  delayr      = 1
111
  delayw      = 2
112
end
113
 
114
/* IMMU SECTION
115
 
116
    This section configures the Instruction Memory Manangement Unit
117
 
118
    enabled = 0/1
119
       '0': disabled
120
       '1': enabled
121
       (NOTE: UPR bit is set)
122
 
123
    nsets = 
124
       number of ITLB sets; must be power of two
125
 
126
    nways = 
127
       number of ITLB ways
128
 
129
    pagesize = 
130
       instruction page size; must be power of two
131
 
132
    entrysize = 
133
       instruction entry size in bytes
134
 
135
    ustates = 
136
       number of ITLB usage states (2, 3, 4 etc., max is 4)
137
 
138
    hitdelay = 
139
       number of cycles immu hit costs
140
 
141
    missdelay = 
142
       number of cycles immu miss costs
143
*/
144
 
145
section immu
146
  enabled = 1
147
  nsets = 64
148
  nways = 1
149
  pagesize = 8192
150
  hitdelay = 0
151
  missdelay = 0
152
end
153
 
154
 
155
/* DMMU SECTION
156
 
157
    This section configures the Data Memory Manangement Unit
158
 
159
    enabled = 0/1
160
       '0': disabled
161
       '1': enabled
162
       (NOTE: UPR bit is set)
163
 
164
    nsets = 
165
       number of DTLB sets; must be power of two
166
 
167
    nways = 
168
       number of DTLB ways
169
 
170
    pagesize = 
171
       data page size; must be power of two
172
 
173
    entrysize = 
174
       data entry size in bytes
175
 
176
    ustates = 
177
       number of DTLB usage states (2, 3, 4 etc., max is 4)
178
 
179
    hitdelay = 
180
       number of cycles dmmu hit costs
181
 
182
    missdelay = 
183
       number of cycles dmmu miss costs
184
*/
185
 
186
section dmmu
187
  enabled = 1
188
  nsets = 64
189
  nways = 1
190
  pagesize = 8192
191
  hitdelay = 0
192
  missdelay = 0
193
end
194
 
195
 
196
/* IC SECTION
197
 
198
   This section configures the Instruction Cache
199
 
200
   enabled = 0/1
201
       '0': disabled
202
       '1': enabled
203
      (NOTE: UPR bit is set)
204
 
205
   nsets = 
206
      number of IC sets; must be power of two
207
 
208
   nways = 
209
      number of IC ways
210
 
211
   blocksize = 
212
      IC block size in bytes; must be power of two
213
 
214
   ustates = 
215
      number of IC usage states (2, 3, 4 etc., max is 4)
216
 
217
   hitdelay = 
218
      number of cycles ic hit costs
219
 
220
    missdelay = 
221
      number of cycles ic miss costs
222
*/
223
 
224
section ic
225
  enabled = 1
226
  nsets = 256
227
  nways = 1
228
  blocksize = 16
229
  hitdelay = 0
230
  missdelay = 0
231
end
232
 
233
 
234
/* DC SECTION
235
 
236
   This section configures the Data Cache
237
 
238
   enabled = 0/1
239
       '0': disabled
240
       '1': enabled
241
      (NOTE: UPR bit is set)
242
 
243
   nsets = 
244
      number of DC sets; must be power of two
245
 
246
   nways = 
247
      number of DC ways
248
 
249
   blocksize = 
250
      DC block size in bytes; must be power of two
251
 
252
   ustates = 
253
      number of DC usage states (2, 3, 4 etc., max is 4)
254
 
255
   load_hitdelay = 
256
      number of cycles dc load hit costs
257
 
258
   load_missdelay = 
259
      number of cycles dc load miss costs
260
 
261
   store_hitdelay = 
262
      number of cycles dc store hit costs
263
 
264
   store_missdelay = 
265
      number of cycles dc store miss costs
266
*/
267
 
268
section dc
269
  enabled = 1
270
  nsets = 256
271
  nways = 1
272
  blocksize = 16
273
  load_hitdelay = 0
274
  load_missdelay = 0
275
  store_hitdelay = 0
276
  store_missdelay = 0
277
end
278
 
279
 
280
/* PIC SECTION
281
 
282
  This section specifies how the pic should behave
283
 
284
  enabled = 0/1
285
      '0': PIC is disabled
286
      '1': PIC is enabled
287
 
288
  edge_trigger = 0/1
289
      '0': Level triggered PIC
290
      '1': Edge triggered PIC
291
*/
292
 
293
section pic
294
  enabled = 1
295
  edge_trigger = 1
296
end
297
 
298
 
299
/* SIM SECTION
300
 
301
  This section specifies how or1ksim should behave.
302
 
303
  verbose = 0/1
304
       '0': don't print extra messages
305
       '1': print extra messages
306
 
307
  debug = 0-9
308
 
309
      1-9: debug message level.
310
           higher numbers produce more messages
311
 
312
  profile = 0/1
313
      '0': don't generate profiling file 'sim.profile'
314
      '1': don't generate profiling file 'sim.profile'
315
 
316
  prof_file = ""
317
      optional filename for the profiling file.
318
      valid only if 'profile' is set
319
 
320
  mprofile = 0/1
321
      '0': don't generate memory profiling file 'sim.mprofile'
322
      '1': generate memory profiling file 'sim.mprofile'
323
 
324
  mprof_file = ""
325
      optional filename for the memory profiling file.
326
      valid only if 'mprofile' is set
327
 
328
  history = 0/1
329
      '0': don't track execution flow
330
      '1': track execution flow
331
      Execution flow can be tracked for the simulator's
332
      'hist' command. Useful for back-trace debugging.
333
 
334
  iprompt = 0/1
335
     '0': start in  (so what do we start in ???)
336
     '1': start in interactive prompt.
337
 
338
  exe_log = 0/1
339
      '0': don't generate execution log.
340
      '1': generate execution log.
341
 
342
  exe_log_type = default/hardware/simple/software
343
      type of execution log, default is used when not specified
344
 
345
  exe_log_start = 
346
      index of first instruction to start logging, default = 0
347
 
348
  exe_log_end = 
349
      index of last instruction to end logging; not limited, if omitted
350
 
351
  exe_log_marker = 
352
       specifies number of instructions before horizontal marker is
353
      printed; if zero, markers are disabled (default)
354
 
355
  exe_log_file = ""
356
      filename for the exection log file.
357
      valid only if 'exe_log' is set
358
 
359
  clkcycle = [ps|ns|us|ms]
360
      specifies time measurement for one cycle
361
*/
362
 
363
section sim
364
  /* verbose = 1 */
365
  debug = 0
366
  profile = 0
367
  prof_file = "sim.profile"
368
 
369
  history = 0
370
  /* iprompt = 0 */
371
  exe_log = 0
372
  exe_log_type = software
373
  exe_log_start = 0
374
/*  exe_log_end = 20000000*/
375
  exe_log_marker = 10000
376
  exe_log_file = "executed.log"
377
 
378
  clkcycle = 100ns
379
end
380
 
381
 
382
/* SECTION VAPI
383
 
384
    This section configures the Verification API, used for Advanced
385
    Core Verification.
386
 
387
    enabled = 0/1
388
        '0': disbable VAPI server
389
        '1': enable/start VAPI server
390
 
391
    server_port = 
392
        TCP/IP port to start VAPI server on
393
 
394
    log_enabled = 0/1
395
       '0': disable VAPI requests logging
396
       '1': enable VAPI requests logging
397
 
398
    hide_device_id = 0/1
399
       '1': don't log device id (for compatability with old version)
400
       '0': log device id
401
 
402
 
403
    vapi_log_file = 
404
       filename for the log file.
405
       valid only if log_enabled is set
406
*/
407
 
408
section VAPI
409
  enabled = 0
410
  server_port = 50000
411
  log_enabled = 0
412
  vapi_log_file = "vapi.log"
413
end
414
 
415
 
416
/* CPU SECTION
417
 
418
   This section specifies various CPU parameters.
419
 
420
   ver = 
421
   cfg = 
422
   rev = 
423
      specifies version, configuration and revision fields of the CPU version
424
      register.
425
 
426
   upr = 
427
      changes the upr register
428
 
429
   cfgr = 
430
      changes the CPU configuration register
431
 
432
   sr = 
433
      sets the initial Supervision Register value
434
 
435
   superscalar = 0/1
436
      '0': CPU is scalar
437
      '1': CPU is superscalar
438
      (modify cpu/or32/execute.c to tune superscalar model)
439
 
440
   hazards = 0/1
441
      '0': don't track data hazards in superscalar CPU
442
      '1': track data hazards in superscalar CPU
443
      If tracked, data hazards can be displayed using the
444
      simulator's 'r' command.
445
 
446
   dependstats = 0/1
447
      '0': don't calculate inter-instruction dependencies.
448
      '1': calculate inter-instruction dependencies.
449
      If calculated, inter-instruction dependencies can be
450
      displayed using the simulator's 'stat' command.
451
 
452
   sbuf_len = 
453
      length of store buffer (<= 256), 0 = disabled
454
*/
455
 
456
section cpu
457
  ver = 0x12
458
  cfg = 0x00
459
  rev = 0x0001
460
  superscalar = 0
461
  hazards = 0
462
  dependstats = 0
463
  sbuf_len = 0
464
end
465
 
466
 
467
/* PM SECTION
468
 
469
   This section specifies Power Management parameters
470
 
471
   enabled = 0/1
472
      '0': disable power management
473
      '1': enable power management
474
*/
475
 
476
section pm
477
  enabled = 1
478
end
479
 
480
 
481
/* BPB SECTION
482
 
483
   This section specifies how branch prediction should behave.
484
 
485
   enabled = 0/1
486
     '0': disable branch prediction
487
     '1': enable branch prediction
488
 
489
   btic = 0/1
490
     '0': disable branch target instruction cache model
491
     '1': enable branch target instruction cache model
492
 
493
   sbp_bf_fwd = 0/1
494
     Static branch prediction for 'l.bf'
495
     '0': don't use forward prediction
496
     '1': use forward prediction
497
 
498
   sbp_bnf_fwd = 0/1
499
     Static branch prediction for 'l.bnf'
500
     '0': don't use forward prediction
501
     '1': use forward prediction
502
 
503
   hitdelay = 
504
       number of cycles bpb hit costs
505
 
506
   missdelay = 
507
       number of cycles bpb miss costs
508
*/
509
 
510
section bpb
511
  enabled = 1
512
  btic = 0
513
  sbp_bf_fwd = 0
514
  sbp_bnf_fwd = 0
515
  hitdelay = 0
516
  missdelay = 0
517
end
518
 
519
 
520
/* DEBUG SECTION
521
 
522
   This sections specifies how the debug unit should behave.
523
 
524
   enabled = 0/1
525
      '0': disable debug unit
526
      '1': enable debug unit
527
 
528
   gdb_enabled = 0/1
529
      '0': don't start gdb server
530
      '1': start gdb server at port 'server_port'
531
 
532
   server_port = 
533
      TCP/IP port to start gdb server on
534
      valid only if gdb_enabled is set
535
 
536
   vapi_id = 
537
      Used to create "fake" vapi log file containing the JTAG proxy messages.
538
*/
539
 
540
section debug
541
  enabled = 0
542
  gdb_enabled = 0
543
  server_port = 51000
544
end
545
 
546
 
547
/* MC SECTION
548
 
549
   This section configures the memory controller
550
 
551
   enabled = 0/1
552
     '0': disable memory controller
553
     '1': enable memory controller
554
 
555
   baseaddr = 
556
      address of first MC register
557
 
558
   POC = 
559
      Power On Configuration register
560
 
561
   index = 
562
      Index of this memory controller amongst all the memory controllers
563
*/
564
 
565
section mc
566
  enabled = 1
567
  baseaddr = 0x93000000
568
  POC = 0x0000000a                 /* 32 bit SSRAM */
569
  index = 0
570
end
571
 
572
 
573
/* UART SECTION
574
 
575
   This section configures the UARTs
576
 
577
     enabled = <0|1>
578
        Enable/disable the peripheral.  By default if it is enabled.
579
 
580
     baseaddr = 
581
        address of first UART register for this device
582
 
583
 
584
     channel = :
585
 
586
        The channel parameter indicates the source of received UART characters
587
        and the sink for transmitted UART characters.
588
 
589
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
590
        (without quotes).
591
 
592
          A) To send/receive characters from a pair of files, use a file
593
             channel:
594
 
595
               channel=file:,
596
 
597
          B) To create an interactive terminal window, use an xterm channel:
598
 
599
               channel=xterm:[]*
600
 
601
          C) To create a bidirectional tcp socket which one could, for example,
602
             access via telnet, use a tcp channel:
603
 
604
               channel=tcp:
605
 
606
          D) To cause the UART to read/write from existing numeric file
607
             descriptors, use an fd channel:
608
 
609
               channel=fd:,
610
 
611
          E) To connect the UART to a physical serial port, create a tty
612
             channel:
613
 
614
               channel=tty:device=/dev/ttyS0,baud=9600
615
 
616
     irq = 
617
        irq number for this device
618
 
619
     16550 = 0/1
620
        '0': this device is a UART16450
621
        '1': this device is a UART16550
622
 
623
     jitter = 
624
        in msecs... time to block, -1 to disable it
625
 
626
     vapi_id = 
627
        VAPI id of this instance
628
*/
629
 
630
section uart
631
  enabled = 1
632
  baseaddr = 0x90000000
633
  irq = 2
634
  channel = "file:uart0.rx,uart0.tx"
635
  jitter = -1                     /* async behaviour */
636
  16550 = 1
637
end
638
 
639
 
640
/* DMA SECTION
641
 
642
   This section configures the DMAs
643
 
644
     enabled = <0|1>
645
        Enable/disable the peripheral.  By default if it is enabled.
646
 
647
     baseaddr = 
648
        address of first DMA register for this device
649
 
650
     irq = 
651
        irq number for this device
652
 
653
     vapi_id = 
654
        VAPI id of this instance
655
*/
656
 
657
section dma
658
  enabled = 1
659
  baseaddr = 0x9a000000
660
  irq = 11
661
end
662
 
663
 
664
/* ETHERNET SECTION
665
 
666
   This section configures the ETHERNETs
667
 
668
     enabled = <0|1>
669
        Enable/disable the peripheral.  By default if it is enabled.
670
 
671
     baseaddr = 
672
        address of first ethernet register for this device
673
 
674
     dma = 
675
        which controller is this ethernet "connected" to
676
 
677
     irq = 
678
        ethernet mac IRQ level
679
 
680
     rtx_type = 
681
        use 0 - file interface, 1 - socket interface. Note the socket
682
        interface must be configured at build time.
683
 
684
     rx_channel = 
685
        DMA channel used for RX
686
 
687
     tx_channel = 
688
        DMA channel used for TX
689
 
690
     rxfile = ""
691
        filename, where to read data from
692
 
693
     txfile = ""
694
        filename, where to write data to
695
 
696
     sockif = ""
697
        interface name of ethernet socket
698
 
699
     vapi_id = 
700
        VAPI id of this instance
701
*/
702
 
703
section ethernet
704
  enabled = 1
705
  baseaddr = 0x92000000
706
  irq = 4
707
  rtx_type = 0
708
  rxfile = "eth0.rx"
709
  txfile = "eth0.tx"
710
  sockif = "eth0"
711
end
712
 
713
 
714
/* GPIO SECTION
715
 
716
   This section configures the GPIOs
717
 
718
     enabled = <0|1>
719
        Enable/disable the peripheral.  By default if it is enabled.
720
 
721
     baseaddr = 
722
        address of first GPIO register for this device
723
 
724
     irq = 
725
        irq number for this device
726
 
727
     base_vapi_id = 
728
        first VAPI id of this instance
729
        GPIO uses 8 consecutive VAPI IDs
730
*/
731
 
732
section gpio
733
  enabled = 1
734
  baseaddr = 0x91000000
735
  irq = 3
736
  base_vapi_id = 0x0200
737
end
738
 
739
/* VGA SECTION
740
 
741
    This section configures the VGA/LCD controller
742
 
743
      enabled = <0|1>
744
        Enable/disable the peripheral.  By default if it is enabled.
745
 
746
      baseaddr = 
747
        address of first VGA register
748
 
749
      irq = 
750
        irq number for this device
751
 
752
      refresh_rate = 
753
        number of cycles between screen dumps
754
 
755
      filename = ""
756
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
757
*/
758
 
759
section vga
760
  enabled = 1
761
  baseaddr = 0x97100000
762
  irq = 8
763
  refresh_rate = 100000
764
  filename = "primary"
765
end
766
 
767
 
768
/* FB SECTION
769
 
770
    This section configures the frame buffer
771
 
772
    enabled = <0|1>
773
      Enable/disable the peripheral.  By default if it is enabled.
774
 
775
    baseaddr = 
776
      base address of frame buffer
777
 
778
    refresh_rate = 
779
      number of cycles between screen dumps
780
 
781
    filename = ""
782
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
783
*/
784
 
785
section fb
786
  enabled = 1
787
  baseaddr = 0x97000000
788
  refresh_rate = 1000000
789
  filename = "primary"
790
end
791
 
792
 
793
/* KBD SECTION
794
 
795
    This section configures the PS/2 compatible keyboard
796
 
797
    enabled = <0|1>
798
      Enable/disable the peripheral.  By default if it is enabled.
799
 
800
    baseaddr = 
801
      base address of the keyboard device
802
 
803
    irq = 
804
      irq number for this device
805
 
806
    rxfile = ""
807
      filename, where to read data from
808
*/
809
 
810
section kbd
811
  enabled = 1
812
  baseaddr = 0x94000000
813
  irq = 5
814
  rxfile = "kbd.rx"
815
end
816
 
817
 
818
/* ATA SECTION
819
 
820
    This section configures the ATA/ATAPI host controller
821
 
822
      enabled = <0|1>
823
        Enable/disable the peripheral.  By default it is enabled.
824
 
825
      baseaddr = 
826
        address of first ATA register
827
 
828
      irq = 
829
        irq number for this device
830
 
831
      dev_id = 1/2/3
832
        Which OCIDEC version to imitate
833
 
834
      rev = 
835
        Revision of OCIDEC
836
 
837
      pio_mode0_t1 = <0-255>
838
        PIO T1 reset value
839
 
840
      pio_mode0_t2 = <0-255>
841
        PIO T2 reset value
842
 
843
      pio_mode0_t4 = <0-255>
844
        PIO T4 reset value
845
 
846
      pio_mode0_teoc = <0-255>
847
        PIO Teoc reset value
848
 
849
      dma_mode0_tm = <0-255>
850
        DMA Tm reset value
851
 
852
      dma_mode0_td = <0-255>
853
        DMA Td reset value
854
 
855
      dma_mode0_teoc = <0-255>
856
        DMA Teoc reset value
857
 
858
      Device specific
859
 
860
        type = 
861
          ata device 0 type
862
          0: NO_CONNECT: none (not connected)
863
          1: FILE      : simulated harddisk
864
          2: LOCAL     : local system harddisk
865
 
866
        file = ""
867
          filename for simulated ATA device
868
          valid only if dev_type0 == 1
869
 
870
        size = 
871
          size of simulated hard-disk (in MBytes)
872
          valid only if dev_type0 == 1
873
 
874
        packet = 
875
          0: simulated ATA device does NOT implement PACKET command feature set
876
          1: simulated ATA device does implement PACKET command feature set
877
 
878
        firmware = 
879
          Firmware to report in `Identify device command'
880
 
881
        heads = 
882
          Number of default heads (-1)
883
 
884
        sectors = 
885
          Number of default sectors per track
886
 
887
        mwdma = 
888
          The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
889
 
890
        pio = 
891
          The highest supported pio mode; 4, 3, 2, 1, 0
892
 
893
   FIXME: irq number
894
*/
895
 
896
section ata
897
  enabled = 1
898
  baseaddr = 0x9e000000
899
  irq = 15
900
  dev_id = 1
901
  rev = 0
902
 
903
  pio_mode0_t1 = 6
904
  pio_mode0_t2 = 28
905
  pio_mode0_t4 = 2
906
  pio_mode0_teoc = 23
907
 
908
  dma_mode0_tm = 4
909
  dma_mode0_td = 21
910
  dma_mode0_teoc = 21
911
 
912
  device 0
913
    type   = 1
914
    file   = "/tmp/sim_atadev0"
915
    size   = 1
916
    packet = 0
917
 
918
    heads  = 7
919
    sectors = 32
920
 
921
    firmware = "02207031"
922
    mwdma = 2
923
    pio = 4
924
  enddevice
925
 
926
  device 1
927
    type   = 0
928
    file   = ""
929
    size   = 0
930
    packet = 0
931
  enddevice
932
end
933
 
934
 
935
/* CUC SECTION
936
 
937
    This section configures the OpenRISC Custom Unit Compiler
938
 
939
    memory_order = none/weak/strong/exact
940
      none   different memory ordering, even if there are dependencies,
941
             burst can be made, width can change
942
      weak   different memory ordering, if there cannot be dependencies
943
             burst can be made, width can change
944
      strong same memory ordering, burst can be made, width can change
945
      exact  exacltly the same memory ordering and widths
946
 
947
    calling_convention = 0/1
948
      whether programs follow OpenRISC calling conventions
949
 
950
    enable_bursts = 0/1
951
      whether burst are detected
952
 
953
    no_multicycle = 0/1
954
      if selected no multicycle logic paths will be generated
955
 
956
    timings_fn = ""
957
*/
958
 
959
section cuc
960
  memory_order = weak
961
  calling_convention = 1
962
  enable_bursts = 1
963
  no_multicycle = 1
964
  timings_fn = "virtex.tim"
965
end
966
 

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