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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [default.cfg] - Blame information for rev 582

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Line No. Rev Author Line
1 90 jeremybenn
/* default.cfg -- Or1ksim default configuration script file
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   Copyright (C) 2001, Marko Mlinar 
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   Copyright (C) 2010 Embecosm Limited
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   Contributor Marko Mlinar 
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   Contributor Jeremy Bennett 
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see .  */
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section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  name = "RAM"
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  ce = 1
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  mc = 0
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  baseaddr = 0x00000000
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  size = 0x00200000
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  delayr = 2
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  delayw = 4
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end
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39 98 jeremybenn
/* High memory for testing */
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section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  name = "RAM"
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  ce = 2
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  mc = 0
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  baseaddr = 0xffe00000
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  size = 0x00200000
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  delayr = 2
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  delayw = 4
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end
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section immu
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  enabled = 1
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  nsets = 64
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  nways = 1
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  ustates = 2
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  pagesize = 8192
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end
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section dmmu
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  enabled = 1
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  nsets = 64
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  nways = 1
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  ustates = 2
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  pagesize = 8192
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end
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section ic
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  enabled = 1
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  nsets = 256
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  nways = 1
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  ustates = 2
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  blocksize = 16
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end
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section dc
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  enabled = 1
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  nsets = 256
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  nways = 1
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  ustates = 2
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  blocksize = 16
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end
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87 98 jeremybenn
/* Set the CPU to take vectors at 0xf0000000 */
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section cpu
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  ver =   0x12
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  rev = 0x0001
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  /* upr = */
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  sr = 0x8001
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  superscalar = 0
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  hazards = 0
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  dependstats = 0
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end
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section bpb
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  enabled = 0
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  btic = 0
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end
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section debug
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/*  enabled = 1
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  rsp_enabled = 1
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  rsp_port = 51000*/
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end
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section sim
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  debug = 0
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  profile = 0
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  prof_fn = "sim.profile"
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  exe_log = 0
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  exe_log_type = software
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  exe_log_fn = "executed.log"
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end

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