OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [default.cfg] - Blame information for rev 588

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* default.cfg -- Or1ksim default configuration script file
2
 
3
   Copyright (C) 2001, Marko Mlinar 
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Marko Mlinar 
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
section memory
25
  /*random_seed = 12345
26
  type = random*/
27
  pattern = 0x00
28
  type = unknown /* Fastest */
29
 
30
  name = "RAM"
31
  ce = 1
32
  mc = 0
33
  baseaddr = 0x00000000
34
  size = 0x00200000
35
  delayr = 2
36
  delayw = 4
37
end
38
 
39 98 jeremybenn
/* High memory for testing */
40
section memory
41
  /*random_seed = 12345
42
  type = random*/
43
  pattern = 0x00
44
  type = unknown /* Fastest */
45
 
46
  name = "RAM"
47
  ce = 2
48
  mc = 0
49
  baseaddr = 0xffe00000
50
  size = 0x00200000
51
  delayr = 2
52
  delayw = 4
53
end
54
 
55 90 jeremybenn
section immu
56
  enabled = 1
57
  nsets = 64
58
  nways = 1
59
  ustates = 2
60
  pagesize = 8192
61
end
62
 
63
section dmmu
64
  enabled = 1
65
  nsets = 64
66
  nways = 1
67
  ustates = 2
68
  pagesize = 8192
69
end
70
 
71
section ic
72
  enabled = 1
73
  nsets = 256
74
  nways = 1
75
  ustates = 2
76
  blocksize = 16
77
end
78
 
79
section dc
80
  enabled = 1
81
  nsets = 256
82
  nways = 1
83
  ustates = 2
84
  blocksize = 16
85
end
86
 
87 98 jeremybenn
/* Set the CPU to take vectors at 0xf0000000 */
88 90 jeremybenn
section cpu
89
  ver =   0x12
90
  rev = 0x0001
91
  /* upr = */
92 458 julius
  sr = 0x8001
93 90 jeremybenn
  superscalar = 0
94
  hazards = 0
95
  dependstats = 0
96
end
97
 
98
section bpb
99
  enabled = 0
100
  btic = 0
101
end
102
 
103
section debug
104
/*  enabled = 1
105
  rsp_enabled = 1
106
  rsp_port = 51000*/
107
end
108
 
109
section sim
110
  debug = 0
111
  profile = 0
112
  prof_fn = "sim.profile"
113
 
114
  exe_log = 0
115
  exe_log_type = software
116
  exe_log_fn = "executed.log"
117
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.