OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-edge.cfg] - Blame information for rev 576

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 93 jeremybenn
/* int-edge.cfg -- Or1ksim configuration script file for edge triggered PIC
2
 
3
   Copyright (C) 2001, Marko Mlinar 
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Marko Mlinar 
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
section memory
25
  /*random_seed = 12345
26
  type = random*/
27
  pattern = 0x00
28
  type = unknown /* Fastest */
29
 
30
  name = "FLASH"
31
  ce = 0
32
  mc = 0
33
  baseaddr = 0xf0000000
34
  size = 0x00200000
35
  delayr = 10
36
  delayw = -1
37
end
38
 
39
section memory
40
  /*random_seed = 12345
41
  type = random*/
42
  pattern = 0x00
43
  type = unknown /* Fastest */
44
 
45
  name = "RAM"
46
  ce = 1
47
  mc = 0
48
  baseaddr = 0x00000000
49
  size = 0x00200000
50
  delayr = 2
51
  delayw = 4
52
end
53
 
54
section immu
55
  enabled = 1
56
  nsets = 64
57
  nways = 1
58
  ustates = 2
59
  pagesize = 8192
60
end
61
 
62
section dmmu
63
  enabled = 1
64
  nsets = 64
65
  nways = 1
66
  ustates = 2
67
  pagesize = 8192
68
end
69
 
70
section ic
71
  enabled = 1
72
  nsets = 256
73
  nways = 1
74
  ustates = 2
75
  blocksize = 16
76
end
77
 
78
section dc
79
  enabled = 1
80
  nsets = 256
81
  nways = 1
82
  ustates = 2
83
  blocksize = 16
84
end
85
 
86
section cpu
87
  ver =   0x12
88
  rev = 0x0001
89
  /* upr = */
90
  superscalar = 0
91
  hazards = 0
92
  dependstats = 0
93
end
94
 
95
section bpb
96
  enabled = 0
97
  btic = 0
98
end
99
 
100
section debug
101
/*  enabled = 1
102
  rsp_enabled = 1
103
  rsp_port = 51000*/
104
end
105
 
106
section sim
107
  debug = 0
108
  profile = 0
109
  prof_fn = "sim.profile"
110
 
111
  exe_log = 0
112
  exe_log_type = software
113
  exe_log_fn = "executed.log"
114
end
115
 
116
section dma
117
  baseaddr = 0xB8000000
118
  irq = 4
119
end
120
 
121
section ethernet
122
  enabled = 0
123
  baseaddr = 0x92000000
124
  irq = 4
125 434 jeremybenn
  rtx_type = "file"
126 93 jeremybenn
end
127
 
128
section VAPI
129
  enabled = 0
130
  server_port = 9998
131
end
132
 
133
section fb
134
  enabled = 1
135
  baseaddr = 0x97000000
136
  refresh_rate = 10000
137
  filename = "primary"
138
end
139
 
140
section kbd
141
  enabled = 0
142
end
143
 
144
section pic
145
  enabled = 1
146
  edge_trigger = 1
147
end
148
 
149
section generic
150
  enabled = 1
151
  baseaddr = 0x98000000
152
  size = 8
153
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.