OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-edge.exp] - Blame information for rev 588

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 93 jeremybenn
# int-edge.exp. Test of the library edge triggered interrupt functions
2
 
3
# Copyright (C) 2010 Embecosm Limited
4
 
5
# Contributor Jeremy Bennett 
6
 
7
# This file is part of OpenRISC 1000 Architectural Simulator.
8
 
9
# This program is free software; you can redistribute it and/or modify it
10
# under the terms of the GNU General Public License as published by the Free
11
# Software Foundation; either version 3 of the License, or (at your option)
12
# any later version.
13
 
14
# This program is distributed in the hope that it will be useful, but WITHOUT
15
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
# more details.
18
 
19
# You should have received a copy of the GNU General Public License along
20
# with this program.  If not, see .  */
21
 
22
# -----------------------------------------------------------------------------
23
# This code is commented throughout for use with Doxygen.
24
# -----------------------------------------------------------------------------
25
 
26
 
27
# Run the library edge triggered interrupts in a number of ways.
28
 
29
# Sequence of independent interrupts
30 432 jeremybenn
run_libsim "int-edge simple 1"               \
31
    [list "Initalization succeeded."         \
32
          "Starting interrupt handler"       \
33
          "Enabling interrupts."             \
34
          "Triggering interrupt 2"           \
35
          "PICSR = 0x00000004"               \
36
          "Clearing interrupt 2"             \
37
          "Cleared PICSR is 0x00000000"      \
38
          "Triggering interrupt 2"           \
39
          "PICSR = 0x00000004"               \
40
          "Clearing interrupt 2"             \
41
          "Cleared PICSR is 0x00000000"      \
42
          "Triggering interrupt 3"           \
43
          "PICSR = 0x00000008"               \
44
          "Clearing interrupt 3"             \
45
          "Cleared PICSR is 0x00000000"      \
46
          "Test completed successfully."]    \
47
    "lib-inttest/lib-inttest" "int-edge.cfg" \
48
    "int-logger/int-logger" "-e" "2" "2" "3"
49 93 jeremybenn
 
50 432 jeremybenn
run_libsim "int-edge simple 2"                     \
51
    [list "Initalization succeeded."               \
52
          "Starting interrupt handler"             \
53
          "Enabling interrupts."                   \
54
          "Triggering interrupt 2"                 \
55
          "PICSR = 0x00000004"                     \
56
          "Clearing interrupt 2"                   \
57
          "Cleared PICSR is 0x00000000"            \
58
          "Triggering interrupt 7"                 \
59
          "PICSR = 0x00000080"                     \
60
          "Clearing interrupt 7"                   \
61
          "Cleared PICSR is 0x00000000"            \
62
          "Triggering interrupt 17"                \
63
          "PICSR = 0x00020000"                     \
64
          "Clearing interrupt 17"                   \
65
          "Cleared PICSR is 0x00000000"            \
66
          "Triggering interrupt 31"                \
67
          "PICSR = 0x80000000"                     \
68
          "Clearing interrupt 31"                   \
69
          "Cleared PICSR is 0x00000000"            \
70
          "Test completed successfully."]          \
71
    "lib-inttest/lib-inttest" "int-edge.cfg"       \
72
    "int-logger/int-logger" "-e" "2" "7" "17" "31"
73 93 jeremybenn
 
74
# Duplicated interrupts
75 432 jeremybenn
run_libsim "int-edge duplicated 1"               \
76
    [list "Initalization succeeded."             \
77
          "Starting interrupt handler"           \
78
          "Enabling interrupts."                 \
79
          "Triggering interrupt 2"               \
80
          "PICSR = 0x00000004"                   \
81
          "Clearing interrupt 2"                 \
82
          "Cleared PICSR is 0x00000000"          \
83
          "Triggering interrupt 2"               \
84
          "PICSR = 0x00000004"                   \
85
          "Clearing interrupt 2"                 \
86
          "Cleared PICSR is 0x00000000"          \
87
          "Triggering interrupt 4"               \
88
          "PICSR = 0x00000010"                   \
89
          "Clearing interrupt 4"                 \
90
          "Cleared PICSR is 0x00000000"          \
91
          "Triggering interrupt 2"               \
92
          "PICSR = 0x00000004"                   \
93
          "Clearing interrupt 2"                 \
94
          "Cleared PICSR is 0x00000000"          \
95
          "Test completed successfully."]        \
96
    "lib-inttest/lib-inttest" "int-edge.cfg"     \
97
    "int-logger/int-logger" "-e" "2" "2" "4" "2"
98 93 jeremybenn
 
99 432 jeremybenn
run_libsim "int-edge duplicated 2"                                   \
100
    [list "Initalization succeeded."                                 \
101
          "Starting interrupt handler"                               \
102
          "Enabling interrupts."                                     \
103
          "Triggering interrupt 2"                                   \
104
          "PICSR = 0x00000004"                                       \
105
          "Clearing interrupt 2"                                     \
106
          "Cleared PICSR is 0x00000000"                              \
107
          "Triggering interrupt 2"                                   \
108
          "PICSR = 0x00000004"                                       \
109
          "Clearing interrupt 2"                                     \
110
          "Cleared PICSR is 0x00000000"                              \
111
          "Triggering interrupt 2"                                   \
112
          "PICSR = 0x00000004"                                       \
113
          "Clearing interrupt 2"                                     \
114
          "Cleared PICSR is 0x00000000"                              \
115
          "Triggering interrupt 2"                                   \
116
          "PICSR = 0x00000004"                                       \
117
          "Clearing interrupt 2"                                     \
118
          "Cleared PICSR is 0x00000000"                              \
119
          "Triggering interrupt 2"                                   \
120
          "PICSR = 0x00000004"                                       \
121
          "Clearing interrupt 2"                                     \
122
          "Cleared PICSR is 0x00000000"                              \
123
          "Triggering interrupt 2"                                   \
124
          "PICSR = 0x00000004"                                       \
125
          "Clearing interrupt 2"                                     \
126
          "Cleared PICSR is 0x00000000"                              \
127
          "Triggering interrupt 2"                                   \
128
          "PICSR = 0x00000004"                                       \
129
          "Clearing interrupt 2"                                     \
130
          "Cleared PICSR is 0x00000000"                              \
131
          "Triggering interrupt 2"                                   \
132
          "PICSR = 0x00000004"                                       \
133
          "Clearing interrupt 2"                                     \
134
          "Cleared PICSR is 0x00000000"                              \
135
          "Triggering interrupt 2"                                   \
136
          "PICSR = 0x00000004"                                       \
137
          "Clearing interrupt 2"                                     \
138
          "Cleared PICSR is 0x00000000"                              \
139
          "Test completed successfully."]                            \
140
    "lib-inttest/lib-inttest" "int-edge.cfg"                         \
141
    "int-logger/int-logger" "-e" "2" "2" "2" "2" "2" "2" "2" "2" "2"
142 93 jeremybenn
 
143
# All from upcalls
144 432 jeremybenn
run_libsim "int-edge all upcall"                    \
145
    [list "Initalization succeeded."                \
146
          "Starting interrupt handler"              \
147
          "Enabling interrupts."                    \
148
          "Triggering interrupt 20"                 \
149
          "PICSR = 0x00100000"                      \
150
          "Clearing interrupt 2"                    \
151
          "Cleared PICSR is 0x00000000"             \
152
          "Triggering interrupt 7"                  \
153
          "PICSR = 0x00000080"                      \
154
          "Clearing interrupt 7"                    \
155
          "Cleared PICSR is 0x00000000"             \
156
          "Triggering interrupt 17"                 \
157
          "PICSR = 0x00020000"                      \
158
          "Clearing interrupt 17"                   \
159
          "Cleared PICSR is 0x00000000"             \
160
          "Triggering interrupt 31"                 \
161
          "PICSR = 0x80000000"                      \
162
          "Clearing interrupt 31"                   \
163
          "Cleared PICSR is 0x00000000"             \
164
          "Test completed successfully."]           \
165
    "lib-inttest/lib-inttest" "int-edge.cfg"        \
166
    "int-logger/int-logger" "-e" "20" "7" "17" "31"
167 93 jeremybenn
 
168
# Check the boundaries of acceptable interrupt numbers
169 432 jeremybenn
run_libsim "int-edge check boundaries"                               \
170
    [list "Warning: Invalid interrupt # 0 to raise: Exiting."]       \
171
    "lib-inttest/lib-inttest" "int-edge.cfg"                         \
172
    "int-logger/int-logger" "-e" "10" "0" "1" "31" "32" "31" "1" "0"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.