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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-level.cfg] - Blame information for rev 362

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/* int-level.cfg -- Or1ksim configuration script file for level triggered PIC
 
   Copyright (C) 2001, Marko Mlinar 
   Copyright (C) 2010 Embecosm Limited
 
   Contributor Marko Mlinar 
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
 
  name = "FLASH"
  ce = 0
  mc = 0
  baseaddr = 0xf0000000
  size = 0x00200000
  delayr = 10
  delayw = -1
end
 
section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
 
  name = "RAM"
  ce = 1
  mc = 0
  baseaddr = 0x00000000
  size = 0x00200000
  delayr = 2
  delayw = 4
end
 
section immu
  enabled = 1
  nsets = 64
  nways = 1
  ustates = 2
  pagesize = 8192
end
 
section dmmu
  enabled = 1
  nsets = 64
  nways = 1
  ustates = 2
  pagesize = 8192
end
 
section ic
  enabled = 1
  nsets = 256
  nways = 1
  ustates = 2
  blocksize = 16
end
 
section dc
  enabled = 1
  nsets = 256
  nways = 1
  ustates = 2
  blocksize = 16
end
 
section cpu
  ver =   0x12
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  dependstats = 0
end
 
section bpb
  enabled = 0
  btic = 0
end
 
section debug
/*  enabled = 1
  rsp_enabled = 1
  rsp_port = 51000*/
end
 
section sim
  debug = 0
  profile = 0
  prof_fn = "sim.profile"
 
  exe_log = 0
  exe_log_type = software
  exe_log_fn = "executed.log"
end
 
section mc
  enabled = 1
  baseaddr = 0x93000000
  POC = 0x00000008                 /* Power on configuration register */
  index = 0
end
 
section dma
  baseaddr = 0xB8000000
  irq = 4
end
 
section ethernet
  enabled = 0
  baseaddr = 0x92000000
  irq = 4
  rtx_type = 0
end
 
section VAPI
  enabled = 0
  server_port = 9998
end
 
section fb
  enabled = 1
  baseaddr = 0x97000000
  refresh_rate = 10000
  filename = "primary"
end
 
section kbd
  enabled = 0
end
 
section pic
  enabled = 1
  edge_trigger = 0              /* Level triggered */
end
 
section generic
  enabled = 1
  baseaddr = 0x98000000
  size = 8
end

Line No.	Rev	Author	Line
1	93	jeremybenn	`/* int-level.cfg -- Or1ksim configuration script file for level triggered PIC`
2
3			`Copyright (C) 2001, Marko Mlinar`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributor Marko Mlinar`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`section memory`
25			`/*random_seed = 12345`
26			`type = random*/`
27			`pattern = 0x00`
28			`type = unknown /* Fastest */`
29
30			`name = "FLASH"`
31			`ce = 0`
32			`mc = 0`
33			`baseaddr = 0xf0000000`
34			`size = 0x00200000`
35			`delayr = 10`
36			`delayw = -1`
37			`end`
38
39			`section memory`
40			`/*random_seed = 12345`
41			`type = random*/`
42			`pattern = 0x00`
43			`type = unknown /* Fastest */`
44
45			`name = "RAM"`
46			`ce = 1`
47			`mc = 0`
48			`baseaddr = 0x00000000`
49			`size = 0x00200000`
50			`delayr = 2`
51			`delayw = 4`
52			`end`
53
54			`section immu`
55			`enabled = 1`
56			`nsets = 64`
57			`nways = 1`
58			`ustates = 2`
59			`pagesize = 8192`
60			`end`
61
62			`section dmmu`
63			`enabled = 1`
64			`nsets = 64`
65			`nways = 1`
66			`ustates = 2`
67			`pagesize = 8192`
68			`end`
69
70			`section ic`
71			`enabled = 1`
72			`nsets = 256`
73			`nways = 1`
74			`ustates = 2`
75			`blocksize = 16`
76			`end`
77
78			`section dc`
79			`enabled = 1`
80			`nsets = 256`
81			`nways = 1`
82			`ustates = 2`
83			`blocksize = 16`
84			`end`
85
86			`section cpu`
87			`ver = 0x12`
88			`rev = 0x0001`
89			`/* upr = */`
90			`superscalar = 0`
91			`hazards = 0`
92			`dependstats = 0`
93			`end`
94
95			`section bpb`
96			`enabled = 0`
97			`btic = 0`
98			`end`
99
100			`section debug`
101			`/* enabled = 1`
102			`rsp_enabled = 1`
103			`rsp_port = 51000*/`
104			`end`
105
106			`section sim`
107			`debug = 0`
108			`profile = 0`
109			`prof_fn = "sim.profile"`
110
111			`exe_log = 0`
112			`exe_log_type = software`
113			`exe_log_fn = "executed.log"`
114			`end`
115
116			`section mc`
117			`enabled = 1`
118			`baseaddr = 0x93000000`
119			`POC = 0x00000008 /* Power on configuration register */`
120			`index = 0`
121			`end`
122
123			`section dma`
124			`baseaddr = 0xB8000000`
125			`irq = 4`
126			`end`
127
128			`section ethernet`
129			`enabled = 0`
130			`baseaddr = 0x92000000`
131			`irq = 4`
132			`rtx_type = 0`
133			`end`
134
135			`section VAPI`
136			`enabled = 0`
137			`server_port = 9998`
138			`end`
139
140			`section fb`
141			`enabled = 1`
142			`baseaddr = 0x97000000`
143			`refresh_rate = 10000`
144			`filename = "primary"`
145			`end`
146
147			`section kbd`
148			`enabled = 0`
149			`end`
150
151			`section pic`
152			`enabled = 1`
153			`edge_trigger = 0 /* Level triggered */`
154			`end`
155
156			`section generic`
157			`enabled = 1`
158			`baseaddr = 0x98000000`
159			`size = 8`
160			`end`

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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-level.cfg] - Blame information for rev 362