OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-level.exp] - Blame information for rev 569

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 93 jeremybenn
# int-level.exp. Test of the library level triggered interrupt functions
2
 
3
# Copyright (C) 2010 Embecosm Limited
4
 
5
# Contributor Jeremy Bennett 
6
 
7
# This file is part of OpenRISC 1000 Architectural Simulator.
8
 
9
# This program is free software; you can redistribute it and/or modify it
10
# under the terms of the GNU General Public License as published by the Free
11
# Software Foundation; either version 3 of the License, or (at your option)
12
# any later version.
13
 
14
# This program is distributed in the hope that it will be useful, but WITHOUT
15
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
# more details.
18
 
19
# You should have received a copy of the GNU General Public License along
20
# with this program.  If not, see .  */
21
 
22
# -----------------------------------------------------------------------------
23
# This code is commented throughout for use with Doxygen.
24
# -----------------------------------------------------------------------------
25
 
26
 
27
# Run the library level triggered interrupts in a number of ways.
28
 
29
# Sequence of independent interrupts
30
run_libsim "int-level simple 1"                     \
31
    [list "Initalization succeeded."                \
32
          "Starting interrupt handler"              \
33
          "Enabling interrupts."                    \
34 432 jeremybenn
          "Triggering interrupt 1"                  \
35 93 jeremybenn
          "PICSR = 0x00000002"                      \
36
          "Clearing interrupt 1"                    \
37
          "Test completed successfully."]           \
38 432 jeremybenn
    "lib-inttest/lib-inttest" "int-level.cfg"       \
39
    "int-logger/int-logger" "-l" "1"
40 93 jeremybenn
 
41
run_libsim "int-level simple 2"                     \
42
    [list "Initalization succeeded."                \
43
          "Starting interrupt handler"              \
44
          "Enabling interrupts."                    \
45 432 jeremybenn
          "Triggering interrupt 7"                  \
46 93 jeremybenn
          "PICSR = 0x00000080"                      \
47
          "Clearing interrupt 7"                    \
48 432 jeremybenn
          "Triggering interrupt 17"                 \
49 93 jeremybenn
          "PICSR = 0x00020000"                      \
50
          "Clearing interrupt 17"                   \
51 432 jeremybenn
          "Triggering interrupt 31"                 \
52 93 jeremybenn
          "PICSR = 0x80000000"                      \
53
          "Clearing interrupt 31"                   \
54
          "Test completed successfully."]           \
55 432 jeremybenn
    "lib-inttest/lib-inttest" "int-level.cfg"       \
56
    "int-logger/int-logger" "-l" "7" "17" "31"
57 93 jeremybenn
 
58
# Check the boundaries of acceptable interrupt numbers
59
run_libsim "int-level check boundaries"               \
60 432 jeremybenn
    [list "Warning: Invalid interrupt # 0 to raise: Exiting."]  \
61
    "lib-inttest/lib-inttest" "int-level.cfg"                   \
62
    "int-logger/int-logger" "-l" "0" "1" "31" "32" "31" "1" "0"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.