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jeremybenn |
# jtag-read-control.exp. Tests of the library JTAG READ_CONTROL command
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# Copyright (C) 2010 Embecosm Limited
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# Contributor Jeremy Bennett
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# This file is part of OpenRISC 1000 Architectural Simulator.
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 3 of the License, or (at your option)
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# any later version.
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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# You should have received a copy of the GNU General Public License along
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# with this program. If not, see . */
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# -----------------------------------------------------------------------------
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# This code is commented throughout for use with Doxygen.
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# -----------------------------------------------------------------------------
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# These tests check all the behavior associated with the JTAG READ_CONTROL
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# command.
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# NOTE. All these tests return timing information, but we ignore it, since in
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# general it will not be repeatable.
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# Tests of the READ_CONTROL for reading from different modules. This should
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# work fine for CPU0, but provoke a warning for Wishbone and CPU1 and a
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# different warning for all other modules. Test no module, Wishbone, CPU0,
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# CPU1 and module 6.
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# READ_CONTROL with no module selected.
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run_libsim "JTAG READ_CONTROL no module" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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"ERROR: JTAG READ_CONTROL with no module selected." \
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" shifted out: 0x0c526410200000000000000000000000" \
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" reset: disabled" \
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" stall: unstalled" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "READ_CONTROL"
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# READ_CONTROL with only WishBone module selected.
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run_libsim "JTAG READ_CONTROL WB module" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x0000000000174841bc61" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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"ERROR: JTAG READ_CONTROL of WishBone not supported." \
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" shifted out: 0x0c526410200000000000000000000000" \
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" reset: disabled" \
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" stall: unstalled" \
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" time taken:" \
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "0" "READ_CONTROL"
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# READ_CONTROL with only invalid module selected.
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run_libsim "JTAG READ_CONTROL invalid module" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000001993c98e69" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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"ERROR: JTAG READ_CONTROL of CPU1 not supported." \
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" shifted out: 0x0c526410200000000000000000000000" \
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" reset: disabled" \
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" stall: unstalled" \
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" time taken:" \
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "2" "READ_CONTROL"
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# READ_CONTROL with invalid module selected after valid module
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run_libsim "JTAG READ_CONTROL invalid after valid module" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000000aff51d871" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000001efe0d976d" \
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" shifted out: 0x01893c98e68000000000" \
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" status: 0x2" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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"ERROR: JTAG READ_CONTROL with no module selected." \
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" shifted out: 0x0c526410200000000000000000000000" \
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" reset: disabled" \
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" stall: unstalled" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "1" "SELECT_MODULE" "6" "READ_CONTROL"
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# READ_CONTROL with valid module selected after invalid module
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run_libsim "JTAG READ_CONTROL valid after invalid module" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000001efe0d976d" \
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" shifted out: 0x01893c98e68000000000" \
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" status: 0x2" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000000aff51d871" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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" shifted out: 0x0c526410200000000000000000000000" \
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" reset: disabled" \
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" stall: unstalled" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "6" "SELECT_MODULE" "1" "READ_CONTROL"
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# Verify that reading works correctly from the valid module, CPU0.
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# READ_CONTROL for CPU0.
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run_libsim "JTAG READ_CONTROL CPU0" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000000aff51d871" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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" shifted out: 0x0c526410200000000000000000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "1" "READ_CONTROL"
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# The only flag that we can sensible read back is the stall flag. In practice
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# the reset flag is only set during the reset sequence, during which we may
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# not get back any data. All we can test (simply) is that if we set the stall
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# flag it reads back correctly. We leave it to the test of WRITE_CONTROL to
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# determine that the stall actually happens!
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# Write the stall bit for CPU and read it back.
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run_libsim "JTAG READ_CONTROL CPU0 read stall bit set" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000000aff51d871" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing WRITE_CONTROL." \
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" shifting in: 0x000000000109a677aa00000000000044" \
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" shifted out: 0x164841bc600000000000000000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed with breakpoint." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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" shifted out: 0x1ea18635000000000000004000000000" \
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" reset: disabled" \
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" stall: stalled" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed with breakpoint." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "1" "READ_CONTROL"
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# Clear the stall bit for CPU and read it back.
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run_libsim "JTAG READ_CONTROL CPU0 read stall bit clear" \
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[list "Initalization succeeded." \
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"Execution step completed OK." \
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"Resetting JTAG." \
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"Execution step completed OK." \
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"Shifting instruction." \
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" shifting in: 0x01" \
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" shifted out: 0x01" \
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" time taken:" \
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"Execution step completed OK." \
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"Selecting module." \
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" shifting in: 0x00000000000aff51d871" \
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" shifted out: 0x0164841bc60000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing WRITE_CONTROL." \
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" shifting in: 0x000000000096dc049200000000000004" \
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" shifted out: 0x164841bc600000000000000000000000" \
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" status: 0x0" \
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" time taken:" \
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"Execution step completed OK." \
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"Processing READ_CONTROL." \
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" shifting in: 0x000000000000000000000005ffa8ec38" \
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" shifted out: 0x0c526410200000000000000000000000" \
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" reset: disabled" \
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" stall: unstalled" \
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" status: 0x0" \
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| 290 |
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" time taken:" \
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| 291 |
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"Execution step completed OK." \
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"Test completed successfully."] \
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"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \
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"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "0" "READ_CONTROL"
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