OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [acv-gpio.cfg] - Blame information for rev 251

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 82 jeremybenn
section memory
2
  /*random_seed = 12345
3
  type = random*/
4
  pattern = 0x00
5
  type = unknown /* Fastest */
6
 
7
  name = "RAM"
8
  ce = 1
9
  baseaddr = 0x00000000
10
  size = 0x00200000
11
  delayr = 1
12
  delayw = 1
13
end
14
 
15
section memory
16
  /*random_seed = 12345
17
  type = random*/
18
  pattern = 0x00
19
  type = unknown /* Fastest */
20
 
21
  name = "FLASH"
22
  ce = 0
23
  baseaddr = 0xf0000000
24
  size = 0x00200000
25
  delayr = 1
26
  delayw = -1
27
end
28
 
29
section mc
30
  enabled = 1
31
  baseaddr = 0x93000000
32
  POC = 0x00000008                 /* Power on configuration register */
33
end
34
 
35
section cpu
36
  ver = 0x12
37
  rev = 0x0001
38
  /* upr = */
39
  superscalar = 0
40
  hazards = 0
41
  dependstats = 0
42
end
43
 
44
section sim
45
  debug = 3
46
  verbose = 1
47
  exe_log = 1
48
  exe_log_fn = "executed.log"
49
end
50
 
51
section gpio
52
  baseaddr = 0xB0000000
53
  irq = 23
54
  base_vapi_id = 0x0200 /* GPIO uses 8 VAPI IDs */
55
end
56
 
57
section VAPI
58
  enabled = 1
59
  log_enabled = 1
60
  hide_device_id = 1
61
  vapi_log_fn = "vapi.log"
62
  server_port = 9100
63
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.