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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [acv-uart.cfg] - Blame information for rev 132

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Line No. Rev Author Line
1 82 jeremybenn
section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  name = "FLASH"
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  ce = 0
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  baseaddr = 0xf0000000
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  size = 0x00200000
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  delayr = 1
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  delayw = -1
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end
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section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  name = "RAM"
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  ce = 1
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  baseaddr = 0x00000000
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  size = 0x00200000
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  delayr = 1
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  delayw = 1
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end
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section mc
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  enabled = 1
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  baseaddr = 0x93000000
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  POC = 0x00000008                 /* Power on configuration register */
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end
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section cpu
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  ver = 0x12
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  rev = 0x0001
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  /* upr = */
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  superscalar = 0
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  hazards = 0
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  dependstats = 0
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end
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section sim
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  debug = 4
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  verbose = 1
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  exe_log = 1
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  exe_log_fn = "executed.log"
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end
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section uart
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  baseaddr = 0x9c000000
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  jitter = -1                     /* async behaviour */
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  16550 =  1
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  irq = 19
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  vapi_id = 0x100
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end
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section VAPI
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  enabled = 1
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  log_enabled = 1
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  hide_device_id = 1
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  vapi_log_fn = "vapi.log"
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  server_port = 9100
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end

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