OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [fp.cfg] - Blame information for rev 509

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 104 jeremybenn
/* fp.cfg -- Or1ksim configuration script file when using FP instructions.
2
 
3
   Copyright (C) 2001, Marko Mlinar 
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Marko Mlinar 
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
section memory
25
  /*random_seed = 12345
26
  type = random*/
27
  pattern = 0x00
28
  type = unknown /* Fastest */
29
 
30
  name = "FLASH"
31
  ce = 0
32
  mc = 0
33
  baseaddr = 0xf0000000
34
  size = 0x00200000
35
  delayr = 10
36
  delayw = -1
37
end
38
 
39
section memory
40
  /*random_seed = 12345
41
  type = random*/
42
  pattern = 0x00
43
  type = unknown /* Fastest */
44
 
45
  name = "RAM"
46
  ce = 1
47
  mc = 0
48
  baseaddr = 0x00000000
49
  size = 0x00200000
50 233 julius
  delayr = 1
51
  delayw = 1
52 104 jeremybenn
end
53
 
54
section immu
55
  enabled = 1
56
  nsets = 64
57
  nways = 1
58
  ustates = 2
59
  pagesize = 8192
60
end
61
 
62
section dmmu
63
  enabled = 1
64
  nsets = 64
65
  nways = 1
66
  ustates = 2
67
  pagesize = 8192
68
end
69
 
70
section ic
71
  enabled = 1
72
  nsets = 256
73
  nways = 1
74
  ustates = 2
75
  blocksize = 16
76
end
77
 
78
section dc
79
  enabled = 1
80
  nsets = 256
81
  nways = 1
82
  ustates = 2
83
  blocksize = 16
84
end
85
 
86
section cpu
87
  ver =   0x12
88
  rev = 0x0001
89
  /* upr = */
90
  superscalar = 0
91
  hazards = 0
92
  dependstats = 0
93
  hardfloat = 1
94
end
95
 
96
section bpb
97
  enabled = 0
98
  btic = 0
99
end
100
 
101
section debug
102
/*  enabled = 1
103
  rsp_enabled = 1
104
  rsp_port = 51000 */
105
end
106
 
107
section sim
108
  debug = 0
109
  profile = 0
110
  prof_fn = "sim.profile"
111
 
112
  exe_log = 0
113
  exe_log_type = software
114
  exe_log_fn = "executed.log"
115
end
116
 
117
section dma
118
  baseaddr = 0xB8000000
119
  irq = 4
120
end
121
 
122
section ethernet
123
  enabled = 0
124
  baseaddr = 0x92000000
125
  irq = 4
126 434 jeremybenn
  rtx_type = "file"
127 104 jeremybenn
end
128
 
129
section VAPI
130
  enabled = 0
131
  server_port = 9998
132
end
133
 
134
section fb
135
  enabled = 1
136
  baseaddr = 0x97000000
137
  refresh_rate = 10000
138
  filename = "primary"
139
end
140
 
141
section kbd
142
  enabled = 0
143
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.