OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [inst-set-test.exp] - Blame information for rev 107

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 107 jeremybenn
# inst-set-test.exp. Tests of ORBIS32 instruction set
2
 
3
# Copyright (C) 2010 Embecosm Limited
4
 
5
# Contributor Jeremy Bennett 
6
 
7
# This file is part of OpenRISC 1000 Architectural Simulator.
8
 
9
# This program is free software; you can redistribute it and/or modify it
10
# under the terms of the GNU General Public License as published by the Free
11
# Software Foundation; either version 3 of the License, or (at your option)
12
# any later version.
13
 
14
# This program is distributed in the hope that it will be useful, but WITHOUT
15
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
# more details.
18
 
19
# You should have received a copy of the GNU General Public License along
20
# with this program.  If not, see .  */
21
 
22
# -----------------------------------------------------------------------------
23
# This code is commented throughout for use with Doxygen.
24
# -----------------------------------------------------------------------------
25
 
26
 
27
# Run the l.lws test
28
run_or1ksim "lws-test"                            \
29
    [list "!l.lws"                                \
30
          "   l.lws r4,0(r5): r4=0xdeadbeef:  OK" \
31
          "   l.lws r4,0(r5): r4=0x00000000:  OK" \
32
          "   l.lws r4,0(r5): r4=0x7fffffff:  OK" \
33
          "   l.lws r4,0(r5): r4=0x80000000:  OK" \
34
          "   l.lws r4,0(r5): r4=0xffffffff:  OK" \
35
          "   l.lws r4,0(r5): r4=0x00000000:  OK" \
36
          "   l.lws r4,0(r5): r4=0x7fffffff:  OK" \
37
          "   l.lws r4,0(r5): r4=0x80000000:  OK" \
38
          "   l.lws r4,0(r5): r4=0xffffffff:  OK" \
39
          "   l.lws r4,0(r5): r4=0xdeadbeef:  OK" \
40
          "   l.lws r4,0(r5): r4=0x00000000:  OK" \
41
          "   l.lws r4,0(r5): r4=0x7fffffff:  OK" \
42
          "   l.lws r4,0(r5): r4=0x80000000:  OK" \
43
          "!Test completed"                       \
44
          "!report(0xdeaddead);"                  \
45
          "!exit(0)"]                             \
46
    "inst-set-test.cfg" "inst-set-test/is-lws-test"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.