OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [mmu.exp] - Blame information for rev 566

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 82 jeremybenn
# MMU test using DejaGNU under automake
2
 
3
# Copyright (C) 2010 Embecosm Limited
4
 
5
# Contributor Jeremy Bennett 
6
 
7
# This file is part of OpenRISC 1000 Architectural Simulator.
8
 
9
# This program is free software; you can redistribute it and/or modify it
10
# under the terms of the GNU General Public License as published by the Free
11
# Software Foundation; either version 3 of the License, or (at your option)
12
# any later version.
13
 
14
# This program is distributed in the hope that it will be useful, but WITHOUT
15
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
# more details.
18
 
19
# You should have received a copy of the GNU General Public License along
20
# with this program.  If not, see .  */
21
 
22
# -----------------------------------------------------------------------------
23
# This code is commented throughout for use with Doxygen.
24
# -----------------------------------------------------------------------------
25
 
26 556 julius
# Allow up to 30 seconds to run this
27
set old_timeout $timeout
28
set timeout 30
29 82 jeremybenn
 
30 556 julius
 
31 458 julius
# Run the MMU test
32 82 jeremybenn
run_or1ksim "mmu"                                \
33 458 julius
    [list "DTLB translation tests OK" \
34
         "DTLB match tests OK" \
35
         "DTLB valid bit tests OK" \
36
         "DTLB permission bit tests OK" \
37
         "ITLB translation tests OK" \
38
         "ITLB match tests OK" \
39
         "ITLB valid bit tests OK" \
40
         "ITLB permission tests OK" \
41
         "Tests completed" \
42
         "report(0xdeaddead);" \
43
         "report(0x8000000d);" \
44
         "exit(0)"] \
45 82 jeremybenn
    "mmu.cfg" "mmu/mmu"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.