OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [acv-gpio/] [acv-gpio.c] - Blame information for rev 582

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* acv-gpio.c. GPIO test for Or1ksim
2
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* GPIO test */
29
 
30
#include "spr-defs.h"
31
#include "support.h"
32
#include "int.h"
33
 
34
/* Relative Register Addresses */
35
#define RGPIO_IN        0x00
36
#define RGPIO_OUT       0x04
37
#define RGPIO_OE        0x08
38
#define RGPIO_INTE      0x0C
39
#define RGPIO_PTRIG     0x10
40
#define RGPIO_AUX       0x14
41
#define RGPIO_CTRL      0x18
42
#define RGPIO_INTS      0x1C
43
 
44
/* Fields inside RGPIO_CTRL */
45
#define RGPIO_CTRL_ECLK      0x00000001
46
#define RGPIO_CTRL_NEC       0x00000002
47
#define RGPIO_CTRL_INTE      0x00000004
48
#define RGPIO_CTRL_INTS      0x00000008
49
 
50
#define GPIO_BASE 0xB0000000LU
51
 
52
#define GPIO_INT_LINE 23 /* To which interrupt is GPIO connected */
53
 
54
typedef volatile unsigned long *GPIO_REG;
55
 
56
GPIO_REG rgpio_in = (unsigned long *)(GPIO_BASE + RGPIO_IN),
57
  rgpio_out = (unsigned long *)(GPIO_BASE + RGPIO_OUT),
58
  rgpio_oe = (unsigned long *)(GPIO_BASE + RGPIO_OE),
59
  rgpio_inte = (unsigned long *)(GPIO_BASE + RGPIO_INTE),
60
  rgpio_ptrig = (unsigned long *)(GPIO_BASE + RGPIO_PTRIG),
61
  rgpio_aux = (unsigned long *)(GPIO_BASE + RGPIO_AUX),
62
  rgpio_ctrl = (unsigned long *)(GPIO_BASE + RGPIO_CTRL),
63
  rgpio_ints = (unsigned long *)(GPIO_BASE + RGPIO_INTS);
64
 
65
/* fails if x is false */
66
#define ASSERT(x) ((x)?1: fail (__FILE__, __LINE__))
67
 
68
static void fail (char *file, int line)
69
{
70
  printf( "Test failed in %s:%i\n", file, line );
71
  report( 0xeeeeeeee );
72
  exit( 1 );
73
}
74
 
75
 
76
static void wait_input( unsigned long value )
77
{
78
  unsigned long first = *rgpio_in;
79
  if ( first == value )
80
    return;
81
  while ( 1 ) {
82
    unsigned long curr = *rgpio_in;
83
    if ( curr == value )
84
      return;
85
    if ( curr != first ) {
86
      printf( "While waiting for 0x%08lX, input changed from 0x%08lX to 0x%08lX\n", value, first, curr );
87
      ASSERT( 0 );
88
    }
89
  }
90
}
91
 
92
static volatile unsigned int_count = 0;
93
 
94
 
95
static void gpio_interrupt( void *arg )
96
{
97
  ++ int_count;
98
}
99
 
100
static void init_interrupts( void )
101
{
102
  int_init();
103
  int_add( GPIO_INT_LINE, gpio_interrupt, 0);
104
 
105
  /* Enable interrupts */
106
  mtspr( SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE );
107
}
108
 
109
 
110
 
111
static void test_registers( void )
112
{
113
  printf( "Testing initial values of all registers\n" );
114
  ASSERT( *rgpio_oe == 0 );
115
  ASSERT( *rgpio_inte == 0 );
116
  ASSERT( *rgpio_ptrig == 0 );
117
  ASSERT( *rgpio_ctrl == 0 );
118
  ASSERT( *rgpio_ints == 0 );
119
 
120
  printf( "Verifying that RGPIO_IN is read-only\n" );
121
  {
122
    unsigned long value = *rgpio_in;
123
    unsigned i;
124
    *rgpio_in = ~value;
125
    ASSERT( *rgpio_in == value );
126
 
127
    for ( i = 0; i < 32; ++ i ) {
128
      *rgpio_in = 1LU << i;
129
      ASSERT( *rgpio_in == value );
130
    }
131
  }
132
}
133
 
134
 
135
static void test_simple_io( void )
136
{
137
  unsigned i;
138
  unsigned long oe;
139
 
140
  printf( "Testing simple I/O\n" );
141
  for ( i = 1, oe = 1; i < 31; ++ i, oe = (oe << 1) | 1 ) {
142
    *rgpio_oe = oe;
143
 
144
    *rgpio_out = 0xFFFFFFFF;
145
    wait_input( 0xFFFFFFFF );
146
 
147
    *rgpio_out = 0x00000000;
148
    wait_input( 0x00000000 );
149
  }
150
}
151
 
152
 
153
static void clear_interrupt_status( void )
154
{
155
  *rgpio_ctrl &= ~RGPIO_CTRL_INTS;
156
  *rgpio_ints = 0;
157
}
158
 
159
static void assert_good_interrupt( unsigned expected_count, unsigned long expected_mask )
160
{
161
  ASSERT( int_count == expected_count );
162
  ASSERT( (*rgpio_ctrl & RGPIO_CTRL_INTS) == RGPIO_CTRL_INTS );
163
  ASSERT( (*rgpio_in & ~*rgpio_oe) == expected_mask );
164
  ASSERT( (*rgpio_ints & ~*rgpio_oe) == expected_mask );
165
}
166
 
167
static void test_interrupts( void )
168
{
169
  unsigned i;
170
 
171
  printf( "Testing interrupts\n" );
172
 
173
  *rgpio_oe = 0x80000000;
174
  int_count = 0;
175
  *rgpio_inte = 0x7fffffff;
176
  *rgpio_ptrig = 0x7fffffff;
177
  *rgpio_ctrl = RGPIO_CTRL_INTE;
178
 
179
  *rgpio_out = 0x80000000;
180
  for ( i = 0; i < 31; ++ i ) {
181
    /* Wait for interrupt */
182
    while ( int_count <= i );
183
    assert_good_interrupt( i + 1, 1LU << i );
184
    clear_interrupt_status();
185
    *rgpio_out = (i % 2) ? 0x80000000 : 0;
186
  }
187
 
188
  /* Return things to normal */
189
  *rgpio_ctrl = 0;
190
}
191
 
192
static void test_external_clock( void )
193
{
194
  unsigned i;
195
  printf( "Testing external clock\n" );
196
 
197
  *rgpio_oe = 0x80000000;
198
  *rgpio_inte = 0x7fffffff;
199
  *rgpio_ptrig = 0x7fffffff;
200
 
201
  /* Test positive edge */
202
  int_count = 0;
203
  *rgpio_ctrl = RGPIO_CTRL_INTE;
204
  *rgpio_out = 0x80000000;
205
  for ( i = 0; i < 31; ++ i ) {
206
    while ( int_count <= i );
207
    assert_good_interrupt( i + 1, 1LU << i );
208
    clear_interrupt_status();
209
    *rgpio_out = (i % 2) ? 0x80000000 : 0;
210
  }
211
 
212
  /* Test negative edge */
213
  int_count = 0;
214
  *rgpio_ctrl = RGPIO_CTRL_INTE | RGPIO_CTRL_NEC;
215
  *rgpio_out = 0x80000000;
216
  for ( i = 0; i < 31; ++ i ) {
217
    while ( int_count <= i );
218
    assert_good_interrupt( i + 1, 1LU << i );
219
    clear_interrupt_status();
220
    *rgpio_out = (i % 2) ? 0x80000000 : 0;
221
  }
222
 
223
  /* Return things to normal */
224
  *rgpio_ctrl = 0;
225
}
226
 
227
 
228
static void endshake( void )
229
{
230
  printf( "Finishing simulation\n" );
231
  *rgpio_oe = 0xffff0000;
232
  *rgpio_out = 0x12340000;
233
  wait_input( 0x12345678 );
234
  *rgpio_oe = 0xffffffff;
235
  *rgpio_out = 0xDeadDead;
236
}
237
 
238
 
239
int main()
240
{
241
  printf( "Starting GPIO test\n" );
242
 
243
  init_interrupts();
244
 
245
  test_registers();
246
  test_simple_io();
247
  test_interrupts();
248
  test_external_clock();
249
  endshake();
250
 
251
  printf( "Ending GPIO test\n" );
252
 
253
  report (0xdeaddead);
254
  return 0;
255
}
256
 
257
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.