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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [acv-uart/] [acv-uart.c] - Blame information for rev 534

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Line No. Rev Author Line
1 90 jeremybenn
/* acv-uart.c. UART test for Or1ksim
2
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* UART test using ACV */
29
 
30
#include "spr-defs.h"
31
#include "support.h"
32
 
33
/* use this macro to comment out nonworking parts */
34
#define COMPLETE    0
35
 
36
/* Whether to do test in more detail */
37
#define DETAILED    0
38
 
39
#define UART_ADDR   (0x9c000000)
40
#define UART_RBR    (UART_ADDR + 0)
41
#define UART_THR    (UART_ADDR + 0)
42
#define UART_IER    (UART_ADDR + 1)
43
#define UART_IIR    (UART_ADDR + 2)
44
#define UART_FCR    (UART_ADDR + 2)
45
#define UART_LCR    (UART_ADDR + 3)
46
#define UART_MCR    (UART_ADDR + 4)
47
#define UART_LSR    (UART_ADDR + 5)
48
#define UART_MSR    (UART_ADDR + 6)
49
#define UART_SCR    (UART_ADDR + 7)
50
 
51
#define UART_DLL    (UART_ADDR + 0)
52
#define UART_DLH    (UART_ADDR + 1)
53
 
54
#define LCR_DIVL    (0x80)
55
#define LCR_BREAK   (0x40)
56
#define LCR_STICK   (0x20)
57
#define LCR_EVENP   (0x10)
58
#define LCR_PAREN   (0x08)
59
#define LCR_NSTOP   (0x04)
60
#define LCR_NBITS   (0x03)
61
 
62
#define LSR_DR      (0x01)
63
#define LSR_OE      (0x02)
64
#define LSR_PE      (0x04)
65
#define LSR_FE      (0x08)
66
#define LSR_BREAK   (0x10)
67
#define LSR_TXFE    (0x20)
68
#define LSR_TXE     (0x40)
69
#define LSR_ERR     (0x80)
70
 
71
#define UART_INT_LINE 19 /* To which interrupt is uart connected */
72
 
73
/* fails if x is false */
74
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
75
/* Waits a few cycles that uart can prepare its data */
76
#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
77
/* fails if there is an error */
78
#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
79
printf ("LSR7 (0x%02x) ERR @ %i\n", x, __LINE__); ASSERT(!(x & LSR_ERR) && ((x & 0x60) != 0x40));}
80
#define MARK() printf ("Passed line %i\n", __LINE__)
81
 
82
#ifndef __LINE__
83
#define __LINE__  0
84
#endif
85
 
86
void fail (char *func, int line)
87
{
88
#ifndef __FUNCTION__
89
#define __FUNCTION__ "?"
90
#endif
91
  printf ("Test failed in %s:%i\n", func, line);
92
  report(0xeeeeeeee);
93
  exit (1);
94
}
95
 
96
inline void setreg (unsigned long addr, unsigned char value)
97
{
98
  *((volatile unsigned char *)addr) = value;
99
}
100
 
101
inline unsigned long getreg (unsigned long addr)
102
{
103
  return *((volatile unsigned char *)addr);
104
}
105
 
106
static volatile int int_cnt;
107
static volatile unsigned int_iir;
108
static volatile unsigned int_lsr;
109
static int int_rbr;
110
 
111
void interrupt_handler ()
112
{
113
  unsigned x;
114
  printf ("Int\n");
115
  report(0xdeaddead);
116
  report(int_iir = getreg (UART_IIR));
117
  report(int_lsr = getreg (UART_LSR));
118
  int_cnt++;
119
  ASSERT (int_iir != 1);
120
  switch (int_iir & 0xf) {
121
    case 0x6: printf ("Receiver LS int.\n"); break;
122
    case 0x4: printf ("Received Data available. Expecting %02x, received %02x\n",
123
                        int_rbr, x = getreg(UART_RBR));
124
              ASSERT (x == int_rbr);
125
              report (x);
126
              report (int_rbr);
127
              break;
128
    case 0xc: printf ("Character timeout. Expecting %02x, received %02x\n",
129
                        int_rbr, x = getreg(UART_RBR));
130
              ASSERT (x == int_rbr);
131
              report (x);
132
              report (int_rbr);
133
              break;
134
    case 0x2: printf ("THR empty.\n"); break;
135
    case 0x0: printf ("Modem Status.\n"); break;
136
    default:
137
      printf ("Invalid iir %x @ %i\n", int_iir, __LINE__);
138
      exit (1);
139
  }
140
  mtspr(SPR_PICSR, 0);
141
}
142
 
143
/* Receives a char and checks for errors */
144
 
145
void recv_char (int ch)
146
{
147
  unsigned x;
148
  char r;
149
  report (ch);
150
  /* Wait for rx fifo to be  */
151
  while (!((x = getreg (UART_LSR)) & LSR_DR));
152
  if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) printf ("LSR7 (0x%02x) ERR @ recv_char\n", x);
153
  ASSERT(!(x & LSR_ERR));
154
 
155
  printf ("expected %02x, read %02x\n", ch, r = getreg (UART_RBR));
156
  ASSERT (r == ch); /* compare character */
157
}
158
 
159
/* Sends a char and checks for errors */
160
 
161
void send_char_no_wait (int ch)
162
{
163
  report (ch);
164
  setreg (UART_THR, ch); /* send character */
165
}
166
 
167
void send_char (int ch)
168
{
169
  report (ch);
170
  while (!(getreg (UART_LSR) & LSR_TXFE));
171
  NO_ERROR();
172
  setreg (UART_THR, ch); /* send character */
173
  NO_ERROR();
174
}
175
 
176
void init_8n1 ()
177
{
178
  setreg (UART_IER, 0x00); /* disable interrupts */
179
  WAIT();
180
  ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
181
  setreg (UART_FCR, 0x07);      /* clear RX and TX FIFOs */
182
  setreg (UART_LCR, LCR_DIVL);
183
  setreg (UART_DLH, 2 >> 8);
184
  setreg (UART_DLL, 2 & 0xff);
185
  setreg (UART_LCR, 0x03);    /* 8N1 @ 2 */
186
  ASSERT(getreg (UART_LCR) == 0x03);
187
  ASSERT (!(getreg (UART_LSR) & 0x1f));
188
}
189
 
190
/* Test reset values and r/w properties of some registers */
191
 
192
void register_test ()
193
{
194
  printf ("register test\n");
195
  MARK();
196
  { /* test reset values */
197
    ASSERT(getreg (UART_RBR) == 0x00); //0
198
    ASSERT(getreg (UART_IER) == 0x00); //1
199
    ASSERT(getreg (UART_IIR) == 0xc1); //2
200
    ASSERT(getreg (UART_LCR) == 0x03); //3
201
    ASSERT(getreg (UART_MCR) == 0x00); //4
202
    ASSERT(getreg (UART_LSR) == 0x60); //5
203
    ASSERT(getreg (UART_MSR) == 0x00); //6
204
    ASSERT(getreg (UART_SCR) == 0x00); //7
205
 
206
    setreg(UART_LCR, LCR_DIVL); //enable latches
207
    ASSERT(getreg (UART_DLL) == 0x00); //0
208
    ASSERT(getreg (UART_DLH) == 0x00); //1
209
    setreg(UART_LCR, 0x00); //disable latches
210
  }
211
    setreg(UART_LCR, 0x00); //disable latches igor
212
    setreg(UART_LCR, 0x00); //disable latches
213
    setreg(UART_LCR, 0x00); //disable latches
214
    setreg(UART_LCR, 0x00); //disable latches
215
    setreg(UART_LCR, 0x00); //disable latches
216
 
217
  MARK();
218
  { /* test if status registers are read only */
219
    unsigned long tmp;
220
    int i;
221
    tmp = getreg (UART_LSR);
222
    setreg (UART_LSR, ~tmp);
223
    ASSERT(getreg (UART_LSR) == tmp);
224
 
225
    for (i = 0; i < 9; i++) {
226
      setreg (UART_LSR, 1 << i);
227
      ASSERT(getreg (UART_LSR) == tmp);
228
    }
229
 
230
    tmp = getreg (UART_MSR);
231
    setreg (UART_MSR, ~tmp);
232
    ASSERT(getreg (UART_MSR) == tmp);
233
 
234
    for (i = 0; i < 9; i++) {
235
      setreg (UART_MSR, 1 << i);
236
      ASSERT(getreg (UART_MSR) == tmp);
237
    }
238
  }
239
 
240
  MARK();
241
  { /* test whether MCR is write only, be careful not to set the loopback bit */
242
    ASSERT(getreg (UART_MCR) == 0x00);
243
    setreg (UART_MCR, 0x45);
244
    ASSERT(getreg (UART_MCR) == 0x00);
245
    setreg (UART_MCR, 0xaa);
246
    ASSERT(getreg (UART_MCR) == 0x00);
247
  }
248
  ASSERT (!(getreg (UART_LSR) & 0x1f));
249
  MARK();
250
  { /* Test if Divisor latch byte holds the data */
251
    int i;
252
    setreg(UART_LCR, LCR_DIVL); //enable latches
253
    ASSERT(getreg (UART_LCR) == LCR_DIVL);
254
    for (i = 0; i < 16; i++) {
255
      unsigned short tmp = 0xdead << i;
256
      setreg (UART_DLH, tmp >> 8);
257
      setreg (UART_DLL, tmp & 0xff);
258
      ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
259
      ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
260
    }
261
      setreg (UART_DLH, 0xa1); //igor
262
      setreg (UART_DLH, 0xa1); //igor
263
      setreg (UART_DLH, 0xa1); //igor
264
      setreg (UART_DLH, 0xa1); //igor
265
      setreg (UART_DLH, 0xa1); //igor
266
 
267
    ASSERT (!(getreg (UART_LSR) & 0x1f));
268
    for (i = 0; i < 16; i++) {
269
      unsigned short tmp = 0xdead << i;
270
      setreg (UART_DLL, tmp >> 8);
271
      setreg (UART_DLH, tmp & 0xff);
272
      ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
273
      ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
274
    }
275
      setreg (UART_DLH, 0xa2); //igor
276
      setreg (UART_DLH, 0xa2); //igor
277
      setreg (UART_DLH, 0xa2); //igor
278
      setreg (UART_DLH, 0xa2); //igor
279
      setreg (UART_DLH, 0xa2); //igor
280
 
281
    setreg(UART_LCR, 0x00); //disable latches
282
    ASSERT(getreg (UART_LCR) == 0x00);
283
    ASSERT (!(getreg (UART_LSR) & 0x1f));
284
  }
285
  MARK();
286
  { /* Test LCR, if it holds our data */
287
    int i;
288
    for (i = 0; i < 6; i++) {
289
      unsigned short tmp = (0xde << i) & 0x3f;
290
      setreg (UART_LCR, tmp);
291
      ASSERT(getreg (UART_LCR) == tmp);
292
    }
293
    ASSERT (!(getreg (UART_LSR) & 0x1f));
294
  }
295
      setreg (UART_LCR, 0xa3); //igor
296
      setreg (UART_LCR, 0xa3); //igor
297
      setreg (UART_LCR, 0xa3); //igor
298
      setreg (UART_LCR, 0xa3); //igor
299
      setreg (UART_LCR, 0xa3); //igor
300
 
301
  MARK ();
302
 
303
  { /* SCR Test :))) */
304
    int i;
305
    setreg (UART_SCR, 0);
306
    ASSERT (getreg (UART_SCR) == 0);
307
    setreg (UART_SCR, 0xff);
308
    ASSERT (getreg (UART_SCR) == 0xff);
309
    for (i = 0; i < 16; i++) {
310
      unsigned char tmp = 0xdead << i;
311
      setreg (UART_SCR, tmp);
312
      ASSERT (getreg (UART_SCR) == tmp);
313
    }
314
  }
315
      setreg (UART_SCR, 0xa5);//igor
316
      setreg (UART_SCR, 0xa5);//igor
317
      setreg (UART_SCR, 0xa5);//igor
318
      setreg (UART_SCR, 0xa5);//igor
319
      setreg (UART_SCR, 0xa5);//igor
320
 
321
  MARK();
322
  /* Other registers will be tested later, if they function correctly,
323
     since we cannot test them now, without destroying anything.  */
324
}
325
 
326
/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
327
 
328
void send_recv_test ()
329
{
330
  char *s;
331
  printf ("send_recv_test\n");
332
  /* Init */
333
  MARK();
334
 
335
  //printf ("basic\n");
336
  ASSERT (!(getreg (UART_LSR) & LSR_DR));
337
  MARK();
338
 
339
  /* Send a string */
340
  s = "send_";
341
  while (*s) {
342
    /* Wait for tx fifo to be empty */
343
    send_char (*s);
344
    report((unsigned long)*s);
345
    s++;
346
  }
347
  ASSERT (!(getreg (UART_LSR) & LSR_DR));
348
  s = "test_";
349
  while (*s) {
350
    /* Wait for tx fifo and tx to be empty */
351
    while (!(getreg (UART_LSR) & LSR_TXE));
352
    NO_ERROR();
353
    setreg (UART_THR, *s); /* send character */
354
    NO_ERROR();
355
    s++;
356
  }
357
  ASSERT (!(getreg (UART_LSR) & LSR_DR));
358
  MARK();
359
 
360
  /* Send characters with delay inbetween */
361
  s = "is_running";
362
  while (*s) {
363
    int i;
364
    send_char (*s);
365
// igor   for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
366
    for (i = 0; i < 16; i++) /* wait at few chars before sending next one */
367
      asm volatile ("l.nop");
368
    s++;
369
  }
370
 
371
  send_char (0); /* send terminate char */
372
  MARK();
373
 
374
  /* Receives and compares the string */
375
  s = "recv";
376
  while (*s) recv_char (*s++);
377
  MARK();
378
  printf ("OK\n");
379
}
380
 
381
/* sends break in both directions */
382
 
383
void break_test ()
384
{
385
  unsigned x;
386
  char *s;
387
  printf ("break_test\n");
388
 
389
  MARK();
390
  /* Send a break */
391
  NO_ERROR();
392
  MARK();
393
  setreg (UART_LCR, 0x03 | LCR_BREAK); /* 8N1 */
394
  MARK();
395
  send_char ('b'); /* make sure it is recognised as a break */
396
  MARK();
397
  recv_char ('*');
398
  setreg (UART_LCR, 0x03); /* deleting break bit, 8N1 */
399
  MARK();
400
 
401
  /* Receive a break */
402
  send_char ('!');
403
  MARK();
404
  while (!((x = getreg (UART_LSR)) & LSR_DR));
405
  /* we should receive zero character with broken frame and break bit should be set */
406
  printf("[%x]\n", (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
407
  ASSERT (x == (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE));
408
  ASSERT (getreg (UART_RBR) == 0);
409
  MARK();
410
 
411
  /* Send a # to release break */
412
  setreg (UART_THR, '#');
413
  while (!(getreg (UART_LSR) & LSR_DR));
414
  NO_ERROR(); /* BREAK bit should be cleared now  */
415
  ASSERT (getreg (UART_RBR) == '$');
416
  MARK();
417
 
418
  /* Break while sending characters */
419
  s = "ns";
420
  while (*s) send_char (*s++);
421
  ASSERT (!(getreg (UART_LSR) & LSR_DR));
422
  while (!(getreg (UART_LSR) & LSR_TXE)); /* Wait till we send everything */
423
  /* this should break the * char, so it should not be received */
424
  setreg (UART_THR, '*');
425
  setreg (UART_LCR, 0x3 | LCR_BREAK);
426
  MARK();
427
 
428
  /* Drop the break, when we get acknowledge */
429
  recv_char ('?');
430
  setreg (UART_LCR, 0x3);
431
  NO_ERROR();
432
  MARK();
433
 
434
  /* Receive a break */
435
  send_char ('#');
436
  while (!((x = getreg (UART_LSR)) & LSR_DR));
437
  /* we should receive zero character with broken frame and break bit
438
     should not be set, because we cleared it */
439
  printf("[%x:%x]\n", x, (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
440
  ASSERT (x == (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE));
441
  ASSERT (getreg (UART_RBR) == 0);
442
  MARK();
443
  send_char ('?');
444
  MARK();
445
  while (!(getreg (UART_LSR) & LSR_DR));
446
  recv_char ('!');
447
  printf ("OK\n");
448
}
449
 
450
/* Tries to send data in different modes in both directions */
451
 
452
/* Utility function, that tests current configuration */
453
void test_mode (int nbits)
454
{
455
  unsigned mask = (1 << nbits) - 1;
456
  send_char (0x55);
457
#if DETAILED
458
  send_char (0x55);
459
  recv_char (0x55 & mask);
460
#endif
461
  recv_char (0x55 & mask);
462
  send_char ('a');                  // 0x61
463
#if DETAILED
464
  send_char ('a');                  // 0x61
465
  recv_char ('a' & mask);
466
#endif
467
  recv_char ('a' & mask);
468
}
469
 
470
void different_modes_test ()
471
{
472
  int speed, parity, length;
473
  printf ("different modes test\n");
474
  init_8n1();
475
 
476
  /* Init */
477
  MARK();
478
  ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
479
  MARK();
480
 
481
  /* Test different speeds */
482
  for (speed = 1; speed < 5; speed++) {
483
    setreg (UART_LCR, LCR_DIVL);
484
    setreg (UART_DLH, speed >> 8);
485
    setreg (UART_DLL, speed & 0xff);
486
    setreg (UART_LCR, 0x03);    /* 8N1 @ 10 => 160 instructions for one cycle */
487
    test_mode (8);
488
    MARK();
489
  }
490
  MARK();
491
 
492
  setreg (UART_LCR, LCR_DIVL);
493
  setreg (UART_DLH, 1 >> 8);
494
  setreg (UART_DLL, 1 & 0xff);
495
  MARK();
496
 
497
  /* Test all parity modes with different char lengths */
498
  for (parity = 0; parity < 8; parity++)
499
    for (length = 0; length < 4; length++) {
500
      setreg (UART_LCR, length | (0 << 2) | (parity << 3));
501
      test_mode (5 + length);
502
      MARK();
503
    }
504
  MARK();
505
 
506
  /* Test configuration, if we have >1 stop bits */
507
  for (length = 0; length < 4; length++) {
508
    setreg (UART_LCR, length | (1 << 2) | (0 << 3));
509
    test_mode (5 + length);
510
    MARK();
511
  }
512
  MARK();
513
 
514
  /* Restore normal mode */
515
  send_char ('T');
516
  while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
517
  setreg (UART_LCR, LCR_DIVL);
518
  setreg (UART_DLH, 2 >> 8);
519
  setreg (UART_DLL, 2 & 0xff);
520
  setreg (UART_LCR, 0x03);    /* 8N1 @ 2 */
521
  MARK();
522
  while (!(getreg (UART_LSR) & 1));  /* Receive 'x' char */
523
  getreg (UART_RBR);
524
  MARK();
525
 
526
  send_char ('T');
527
  while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
528
  MARK();
529
  printf ("OK\n");
530
}
531
 
532
/* Test various FIFO levels, break and framing error interrupt, etc */
533
 
534
void interrupt_test ()
535
{
536
  int i;
537
  printf ("interrupt_test\n");
538
  /* Configure UART for interrupt mode */
539
  ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
540
  setreg (UART_LCR, LCR_DIVL);
541
  setreg (UART_DLH, 12 >> 8);            /* Set relatively slow speed, so we can hanlde interrupts properly */
542
  setreg (UART_DLL, 6 & 0xff);
543
  setreg (UART_LCR, 0x03);    /* 8N1 @ 6 */
544
 
545
  ASSERT (int_cnt == 0);   /* We should not have got any interrupts before this test */
546
  setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
547
  setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
548
 
549
  while (!int_cnt); /* Clear previous THR interrupt */
550
  ASSERT (--int_cnt == 0);
551
  ASSERT (int_iir == 0xc2);
552
  ASSERT ((int_lsr & 0xbe) == 0x20);
553
  MARK();
554
 
555
  /* I am configured - start interrupt test */
556
  send_char ('I');
557
  while (!int_cnt); /* Wait for THR to be empty */
558
  ASSERT (--int_cnt == 0);
559
  ASSERT (int_iir == 0xc2);
560
  ASSERT ((int_lsr & 0xbe) == 0x20);
561
  MARK();
562
 
563
  int_rbr = '0';
564
  while (!int_cnt); /* Wait for DR */
565
  ASSERT (--int_cnt == 0);
566
  ASSERT (int_iir == 0xc4);
567
  ASSERT (int_lsr == 0x61);
568
  ASSERT (int_cnt == 0); /* no interrupts should be pending */
569
  MARK();
570
 
571
  setreg (UART_FCR, 0x41); /* Set trigger level = 4 chars, fifo should not be reset */
572
 
573
  /* Everything ok here, send me 4 more */
574
  send_char ('I');
575
  while (!int_cnt); /* Wait for THR to be empty */
576
  ASSERT (--int_cnt == 0);
577
  ASSERT (int_iir == 0xc2);
578
  ASSERT ((int_lsr & 0xbe) == 0x20);
579
  MARK();
580
 
581
  int_rbr = '1';
582
  while (!int_cnt); /* Wait for DR */
583
  ASSERT (--int_cnt == 0);
584
  ASSERT (int_iir == 0xc4);
585
  ASSERT (int_lsr == 0x61);
586
  MARK();
587
 
588
  setreg (UART_FCR, 0x81); /* Set trigger level = 8 chars, fifo should not be reset */
589
 
590
  /* Everything ok here, send me 5 more */
591
  send_char ('I');
592
  while (!int_cnt); /* Wait for THR to be empty */
593
  ASSERT (--int_cnt == 0);
594
  ASSERT (int_iir == 0xc2);
595
  ASSERT ((int_lsr & 0xbe) == 0x20);
596
  MARK();
597
 
598
  int_rbr = '2';
599
  while (!int_cnt); /* Wait for DR */
600
  ASSERT (--int_cnt == 0);
601
  ASSERT (int_iir == 0xc4);
602
  ASSERT (int_lsr == 0x61);
603
  MARK();
604
 
605
  setreg (UART_FCR, 0xc1); /* Set trigger level = 14 chars, fifo should not be reset */
606
 
607
  /* Everything ok here, send me 7 more */
608
  send_char ('I');
609
  while (!int_cnt); /* Wait for THR to be empty */
610
  ASSERT (--int_cnt == 0);
611
  ASSERT (int_iir == 0xc2);
612
  ASSERT ((int_lsr & 0xbe) == 0x20);
613
  MARK();
614
 
615
  int_rbr = '3';
616
  while (!int_cnt); /* Wait for DR */
617
  ASSERT (--int_cnt == 0);
618
  ASSERT (int_iir == 0xc4);
619
  ASSERT (int_lsr == 0x61);
620
  MARK();
621
 
622
  /* Everything ok here, send me 4 more - fifo should be full OE should occur */
623
  setreg (UART_IER, 0x06); /* Enable interrupts: line status, THR empty */
624
  send_char ('I');
625
  while (!int_cnt); /* Wait for THR to be empty */
626
  ASSERT (--int_cnt == 0);
627
  ASSERT (int_iir == 0xc2);
628
  ASSERT ((int_lsr & 0xbe) == 0x20);
629
  MARK();
630
 
631
  while (!int_cnt); /* Wait for OE */
632
  ASSERT (--int_cnt == 0);
633
  ASSERT (int_iir == 0xc6);
634
  ASSERT (int_lsr == 0xe3);           /* OE flag should be set */
635
  ASSERT (getreg (UART_LSR) == 0x61); /* LSR should be cleared by previous read */
636
  ASSERT (getreg (UART_IIR) == 0xc1); /* No interrupts should be pending */
637
  MARK();
638
 
639
  /* Check if we got everything */
640
  ASSERT (int_cnt == 0); /* no interrupts should be pending */
641
  for (i = 0; i < 3; i++) {
642
    recv_char ("456"[i]);   /* WARNING: read should not cause interrupt even if we step over trigger */
643
    MARK ();
644
  }
645
  /* It is now safe to enable data ready interrupt */
646
  setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
647
 
648
  /* Check if we got everything */
649
  for (i = 0; i < 13; i++) {
650
    recv_char ("789abcdefghij"[i]);   /* WARNING: read should not cause interrupt even if we step over trigger */
651
    MARK ();
652
  }
653
 
654
  ASSERT (int_cnt == 0); /* no interrupts should be pending */
655
  ASSERT (getreg (UART_LSR) == 0x60); /* FIFO should be empty */
656
 
657
  getreg (UART_RBR);      /* check for FIFO counter overflow - fifo must still be empty */
658
  ASSERT (getreg (UART_LSR) == 0x60); /* FIFO should be empty */
659
 
660
  /* check for break interrupt */
661
  send_char ('I');
662
  while (!int_cnt); /* Wait for THR to be empty */
663
  ASSERT (--int_cnt == 0);
664
  ASSERT (int_iir == 0xc2);
665
  ASSERT ((int_lsr & 0xbe) == 0x20);
666
  MARK();
667
 
668
  while (!int_cnt); /* Wait for break interrupt */
669
  ASSERT (--int_cnt == 0);
670
  ASSERT (int_iir == 0xc6);
671
  ASSERT (int_lsr == 0xf1); /* BE flag should be set */
672
  ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
673
  MARK();
674
  recv_char (0);
675
  MARK();
676
 
677
  send_char ('B');  /* Release break */
678
  while (!int_cnt); /* Wait for THR to be empty */
679
  ASSERT (--int_cnt == 0);
680
  ASSERT (int_iir == 0xc2);
681
  ASSERT ((int_lsr & 0xbe) == 0x20);
682
  MARK();
683
  /* Wait for acknowledge */
684
  int_rbr = '$';
685
  while (!int_cnt); /* Wait for timeout */
686
  ASSERT (--int_cnt == 0);
687
  ASSERT (int_iir == 0xcc);
688
  ASSERT (int_lsr == 0x61);
689
  MARK();
690
 
691
  /* TODO: Check for parity error */
692
  /* TODO: Check for frame error */
693
 
694
  /* Check for timeout */
695
  send_char ('I');
696
  while (!int_cnt); /* Wait for THR to be empty */
697
  ASSERT (--int_cnt == 0);
698
  ASSERT (int_iir == 0xc2);
699
  ASSERT ((int_lsr & 0xbe) == 0x20);
700
  MARK();
701
 
702
  int_rbr = 'T';
703
  while (!int_cnt); /* Wait for timeout */
704
  ASSERT (--int_cnt == 0);
705
  ASSERT (int_iir == 0xcc);  /* timeout interrupt occured */
706
  ASSERT (int_lsr == 0x61); /* DR flag should be set */
707
  ASSERT (getreg (UART_LSR) == 0x60); /* DR flag should be cleared - timeout occurred */
708
  MARK();
709
 
710
  send_char ('T');
711
  while (!int_cnt); /* Wait for THR to be empty */
712
  ASSERT (--int_cnt == 0);
713
  ASSERT (int_iir == 0xc2);
714
  ASSERT ((int_lsr & 0xbe) == 0x20);
715
  MARK();
716
 
717
  setreg (UART_IER, 0x00); /* Disable interrupts */
718
  ASSERT (int_cnt == 0); /* no interrupts should be pending */
719
  NO_ERROR ();
720
 
721
  while (getreg (UART_LSR) != 0x60);  /* wait till we sent everynthing and then change mode */
722
  setreg (UART_LCR, LCR_DIVL);
723
  setreg (UART_DLH, 2 >> 8);            /* Set relatively slow speed, so we can hanlde interrupts properly */
724
  setreg (UART_DLL, 2 & 0xff);
725
  setreg (UART_LCR, 0x03);    /* 8N1 @ 2 */
726
  send_char ('T');
727
 
728
  MARK ();
729
  printf ("OK\n");
730
}
731
 
732
/* Test if all control bits are set correctly.  Lot of this was already tested
733
   elsewhere and tests are not duplicated.  */
734
 
735
void control_register_test ()
736
{
737
  /* RBR already tested in send_recv_test() */
738
  /* THR already tested in send_recv_test() */
739
  /* IER already tested in interrupt_test() */
740
  /* IIR already tested in interrupt_test() */
741
  /* FCR0 - uart 16450 specific, not tested */
742
 
743
  /* FCR1 - reset rx FIFO */
744
  send_char ('*');
745
  NO_ERROR ();
746
  while (!(getreg (UART_LSR) & 0x01)); /* Wait for data ready */
747
  setreg (UART_FCR, 2); /* Clears rx fifo */
748
  ASSERT (getreg (UART_LSR) == 0x60);  /* nothing happening */
749
  send_char ('!');
750
  recv_char ('!');
751
  MARK ();
752
 
753
  /* Make sure the TX fifo and the TX serial reg. are empty */
754
  ASSERT (getreg (UART_LSR) & LSR_TXFE);
755
  ASSERT (getreg (UART_LSR) & LSR_TXE);
756
 
757
  /* FCR2 - reset tx FIFO */
758
send_char_no_wait ('1');
759
send_char_no_wait ('2');
760
//  send_char ('1');
761
//  send_char ('2');
762
  setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
763
  ASSERT (getreg (UART_LSR) == 0x20);  /* we should still be sending '1' */
764
  NO_ERROR();
765
  send_char ('*');
766
  recv_char ('*');
767
  MARK ();
768
 
769
  /* LCR already tested in different_modes_test () */
770
  /* TODO: MSR */
771
  /* LSR already tested in different_modes_test () and interrupt_test() */
772
  /* SCR already tested in register_test () */
773
 
774
  MARK ();
775
  printf ("OK\n");
776
}
777
 
778
/* Tests parity error and frame error behaviour */
779
 
780
void line_error_test ()
781
{
782
  printf ("line_error_test\n");
783
 
784
  /* Test framing error if we change speed */
785
  setreg (UART_LCR, LCR_DIVL);
786
  setreg (UART_DLH, 12 >> 8);
787
  setreg (UART_DLL, 12 & 0xff);
788
  setreg (UART_LCR, 0x03);    /* 8N1 @ 3 */
789
  MARK();
790
 
791
  send_char ('c');
792
  ASSERT (int_cnt == 0);
793
  setreg (UART_IER, 0x04); /* Enable interrupts: line status */
794
  while (!int_cnt); /* Wait for THR to be empty */
795
  ASSERT (--int_cnt == 0);
796
  ASSERT (int_iir == 0xc6);
797
  ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
798
  getreg (UART_RBR);        /* Ignore the data */
799
  MARK ();
800
  recv_char ('b');
801
  MARK ();
802
 
803
#if COMPLETE  
804
  /* Test framing error if we change stop bits */
805
  send_char ('*');
806
  while (getreg (UART_LSR));  /* wait till we sent everynthing and then change mode */
807
  setreg (UART_LCR, 0x07); /* 8N2 */
808
  send_char ('*');
809
  MARK ();
810
 
811
  ASSERT (int_cnt == 0);
812
  setreg (UART_IER, 0x04); /* Enable interrupts: line status */
813
  while (!int_cnt); /* Wait for THR to be empty */
814
  ASSERT (--int_cnt == 0);
815
  ASSERT (int_iir == 0xc6);
816
  ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
817
  getreg (UART_RBR);        /* Ignore the data */
818
  recv_char ('b');
819
  MARK();
820
#endif
821
 
822
  MARK ();
823
  printf ("OK\n");
824
}
825
 
826
int main ()
827
{
828
  /* Use our low priority interrupt handler */
829
  excpt_int = (unsigned long)interrupt_handler;
830
 
831
  /* Enable interrupts */
832
  mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
833
  mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
834
 
835
  int_cnt = 0;
836
  int_iir = 0;
837
  int_lsr = 0;
838
  int_rbr = 0;
839
 
840
  register_test ();
841
  init_8n1 ();
842
  send_recv_test ();
843
  break_test ();
844
  different_modes_test ();
845
  interrupt_test ();
846
  control_register_test ();
847
  line_error_test ();
848
 
849
  /* loopback_test ();
850
  modem_test ();
851
  modem_error_test ();*/
852
  recv_char ('@');
853
  printf ("ALL TESTS PASSED\n");
854
  return 0;
855
}

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