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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [basic/] [basic.S] - Blame information for rev 721

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Line No. Rev Author Line
1 90 jeremybenn 
/* basic.S. Basic instruction set test of Or1ksim
2 
 
3 
   Copyright (C) 1999-2006 OpenCores
4 
   Copyright (C) 2010 Embecosm Limited
5 
 
6 
   Contributors various OpenCores participants
7 
   Contributor Jeremy Bennett
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see .  */
23 
 
24 
/* ----------------------------------------------------------------------------
25 
   This code is commented throughout for use with Doxygen.
26 
   --------------------------------------------------------------------------*/
27 
 
28 
#include "spr-defs.h"
29 
#include "board.h"
30 
 
31 
#define MEM_RAM 0x00000000
32 
 
33 
        .section .text
34 458 julius 
        .global main
35 
main:
36 90 jeremybenn 
        l.nop
37 
 
38 
_regs:
39 
        l.addi  r1,r0,0x1
40 
        l.addi  r2,r1,0x2
41 
        l.addi  r3,r2,0x4
42 
        l.addi  r4,r3,0x8
43 
        l.addi  r5,r4,0x10
44 
        l.addi  r6,r5,0x20
45 
        l.addi  r7,r6,0x40
46 
        l.addi  r8,r7,0x80
47 
        l.addi  r9,r8,0x100
48 
        l.addi  r10,r9,0x200
49 
        l.addi  r11,r10,0x400
50 
        l.addi  r12,r11,0x800
51 
        l.addi  r13,r12,0x1000
52 
        l.addi  r14,r13,0x2000
53 
        l.addi  r15,r14,0x4000
54 
        l.addi  r16,r15,0x8000
55 
 
56 
        l.sub   r31,r0,r1
57 
        l.sub   r30,r31,r2
58 
        l.sub   r29,r30,r3
59 
        l.sub   r28,r29,r4
60 
        l.sub   r27,r28,r5
61 
        l.sub   r26,r27,r6
62 
        l.sub   r25,r26,r7
63 
        l.sub   r24,r25,r8
64 
        l.sub   r23,r24,r9
65 
        l.sub   r22,r23,r10
66 
        l.sub   r21,r22,r11
67 
        l.sub   r20,r21,r12
68 
        l.sub   r19,r20,r13
69 
        l.sub   r18,r19,r14
70 
        l.sub   r17,r18,r15
71 
        l.sub   r16,r17,r16
72 
 
73 
        l.or  r3,r0,r16
74 
        l.nop NOP_REPORT        /* Should be 0xffff0012 */
75 
 
76 
        l.movhi r31, hi(MEM_RAM)
77 
        l.ori  r31,r31, lo(MEM_RAM)
78 
        l.sw    0(r31),r16
79 
 
80 
_mem:   l.movhi r3,0x1234
81 
        l.ori   r3,r3,0x5678
82 
 
83 
        l.sw    4(r31),r3
84 
 
85 
        l.lbz   r4,4(r31)
86 
        l.add   r8,r8,r4
87 
        l.sb    11(r31),r4
88 
        l.lbz   r4,5(r31)
89 
        l.add   r8,r8,r4
90 
        l.sb    10(r31),r4
91 
        l.lbz   r4,6(r31)
92 
        l.add   r8,r8,r4
93 
        l.sb    9(r31),r4
94 
        l.lbz   r4,7(r31)
95 
        l.add   r8,r8,r4
96 
        l.sb    8(r31),r4
97 
 
98 
        l.lbs   r4,8(r31)
99 
        l.add   r8,r8,r4
100 
        l.sb    7(r31),r4
101 
        l.lbs   r4,9(r31)
102 
        l.add   r8,r8,r4
103 
        l.sb    6(r31),r4
104 
        l.lbs   r4,10(r31)
105 
        l.add   r8,r8,r4
106 
        l.sb    5(r31),r4
107 
        l.lbs   r4,11(r31)
108 
        l.add   r8,r8,r4
109 
        l.sb    4(r31),r4
110 
 
111 
        l.lhz   r4,4(r31)
112 
        l.add   r8,r8,r4
113 
        l.sh    10(r31),r4
114 
        l.lhz   r4,6(r31)
115 
        l.add   r8,r8,r4
116 
        l.sh    8(r31),r4
117 
 
118 
        l.lhs   r4,8(r31)
119 
        l.add   r8,r8,r4
120 
        l.sh    6(r31),r4
121 
        l.lhs   r4,10(r31)
122 
        l.add   r8,r8,r4
123 
        l.sh    4(r31),r4
124 
 
125 
        l.lwz   r4,4(r31)
126 
        l.add   r8,r8,r4
127 
 
128 
        l.or  r3,r0,r8
129 
        l.nop NOP_REPORT        /* Should be 0x12352af7 */
130 
 
131 
        l.lwz   r9,0(r31)
132 
        l.add   r8,r9,r8
133 
        l.sw    0(r31),r8
134 
 
135 
_arith:
136 
        l.addi  r3,r0,1
137 
        l.addi  r4,r0,2
138 
        l.addi  r5,r0,-1
139 
        l.addi  r6,r0,-1
140 
        l.addi  r8,r0,0
141 
 
142 
        l.sub   r7,r5,r3
143 
        l.sub   r8,r3,r5
144 
        l.add   r8,r8,r7
145 
 
146 
        l.div   r7,r7,r4
147 
        l.add   r9,r3,r4
148 
        l.mul   r7,r9,r7
149 
        l.divu  r7,r7,r4
150 
        l.add   r8,r8,r7
151 
 
152 
        l.or  r3,r0,r8
153 
        l.nop NOP_REPORT        /* Should be 0x7ffffffe */
154 
 
155 
        l.lwz   r9,0(r31)
156 
        l.add   r8,r9,r8
157 
        l.sw    0(r31),r8
158 
 
159 
_log:
160 
        l.addi  r3,r0,1
161 
        l.addi  r4,r0,2
162 
        l.addi  r5,r0,-1
163 
        l.addi  r6,r0,-1
164 
        l.addi  r8,r0,0
165 
 
166 
        l.andi  r8,r8,1
167 
        l.and   r8,r8,r3
168 
 
169 
        l.xori  r8,r5,0xa5a5
170 
        l.xor   r8,r8,r5
171 
 
172 
        l.ori   r8,r8,2
173 
        l.or    r8,r8,r4
174 
 
175 
        l.or  r3,r0,r8
176 
        l.nop NOP_REPORT        /* Should be 0xffffa5a7 */
177 
 
178 
        l.lwz   r9,0(r31)
179 
        l.add   r8,r9,r8
180 
        l.sw    0(r31),r8
181 
 
182 
_shift:
183 
        l.addi  r3,r0,1
184 
        l.addi  r4,r0,2
185 
        l.addi  r5,r0,-1
186 
        l.addi  r6,r0,-1
187 
        l.addi  r8,r0,0
188 
 
189 
        l.slli  r8,r5,6
190 
        l.sll   r8,r8,r4
191 
 
192 
        l.srli  r8,r8,6
193 
        l.srl   r8,r8,r4
194 
 
195 
        l.srai  r8,r8,2
196 
        l.sra   r8,r8,r4
197 
 
198 
        l.or  r3,r0,r8
199 
        l.nop NOP_REPORT        /* Should be 0x000fffff */
200 
 
201 
        l.lwz   r9,0(r31)
202 
        l.add   r8,r9,r8
203 
        l.sw    0(r31),r8
204 
 
205 
_flag:
206 
        l.addi  r3,r0,1
207 
        l.addi  r4,r0,-2
208 
        l.addi  r8,r0,0
209 
 
210 
        l.sfeq  r3,r3
211 
        l.mfspr r5,r0,17
212 
        l.andi  r4,r5,0x200
213 
        l.add   r8,r8,r4
214 
 
215 
        l.sfeq  r3,r4
216 
        l.mfspr r5,r0,17
217 
        l.andi  r4,r5,0x200
218 
        l.add   r8,r8,r4
219 
 
220 
        l.sfeqi r3,1
221 
        l.mfspr r5,r0,17
222 
        l.andi  r4,r5,0x200
223 
        l.add   r8,r8,r4
224 
 
225 
        l.sfeqi r3,-2
226 
        l.mfspr r5,r0,17
227 
        l.andi  r4,r5,0x200
228 
        l.add   r8,r8,r4
229 
 
230 
        l.sfne  r3,r3
231 
        l.mfspr r5,r0,17
232 
        l.andi  r4,r5,0x200
233 
        l.add   r8,r8,r4
234 
 
235 
        l.sfne  r3,r4
236 
        l.mfspr r5,r0,17
237 
        l.andi  r4,r5,0x200
238 
        l.add   r8,r8,r4
239 
 
240 
        l.sfnei r3,1
241 
        l.mfspr r5,r0,17
242 
        l.andi  r4,r5,0x200
243 
        l.add   r8,r8,r4
244 
 
245 
        l.sfnei r3,-2
246 
        l.mfspr r5,r0,17
247 
        l.andi  r4,r5,0x200
248 
        l.add   r8,r8,r4
249 
 
250 
        l.sfgtu r3,r3
251 
        l.mfspr r5,r0,17
252 
        l.andi  r4,r5,0x200
253 
        l.add   r8,r8,r4
254 
 
255 
        l.sfgtu r3,r4
256 
        l.mfspr r5,r0,17
257 
        l.andi  r4,r5,0x200
258 
        l.add   r8,r8,r4
259 
 
260 
        l.sfgtui        r3,1
261 
        l.mfspr r5,r0,17
262 
        l.andi  r4,r5,0x200
263 
        l.add   r8,r8,r4
264 
 
265 
        l.sfgtui        r3,-2
266 
        l.mfspr r5,r0,17
267 
        l.andi  r4,r5,0x200
268 
        l.add   r8,r8,r4
269 
 
270 
        l.sfgeu r3,r3
271 
        l.mfspr r5,r0,17
272 
        l.andi  r4,r5,0x200
273 
        l.add   r8,r8,r4
274 
 
275 
        l.sfgeu r3,r4
276 
        l.mfspr r5,r0,17
277 
        l.andi  r4,r5,0x200
278 
        l.add   r8,r8,r4
279 
 
280 
        l.sfgeui        r3,1
281 
        l.mfspr r5,r0,17
282 
        l.andi  r4,r5,0x200
283 
        l.add   r8,r8,r4
284 
 
285 
        l.sfgeui        r3,-2
286 
        l.mfspr r5,r0,17
287 
        l.andi  r4,r5,0x200
288 
        l.add   r8,r8,r4
289 
 
290 
        l.sfltu r3,r3
291 
        l.mfspr r5,r0,17
292 
        l.andi  r4,r5,0x200
293 
        l.add   r8,r8,r4
294 
 
295 
        l.sfltu r3,r4
296 
        l.mfspr r5,r0,17
297 
        l.andi  r4,r5,0x200
298 
        l.add   r8,r8,r4
299 
 
300 
        l.sfltui        r3,1
301 
        l.mfspr r5,r0,17
302 
        l.andi  r4,r5,0x200
303 
        l.add   r8,r8,r4
304 
 
305 
        l.sfltui        r3,-2
306 
        l.mfspr r5,r0,17
307 
        l.andi  r4,r5,0x200
308 
        l.add   r8,r8,r4
309 
 
310 
        l.sfleu r3,r3
311 
        l.mfspr r5,r0,17
312 
        l.andi  r4,r5,0x200
313 
        l.add   r8,r8,r4
314 
 
315 
        l.sfleu r3,r4
316 
        l.mfspr r5,r0,17
317 
        l.andi  r4,r5,0x200
318 
        l.add   r8,r8,r4
319 
 
320 
        l.sfleui        r3,1
321 
        l.mfspr r5,r0,17
322 
        l.andi  r4,r5,0x200
323 
        l.add   r8,r8,r4
324 
 
325 
        l.sfleui        r3,-2
326 
        l.mfspr r5,r0,17
327 
        l.andi  r4,r5,0x200
328 
        l.add   r8,r8,r4
329 
 
330 
        l.sfgts r3,r3
331 
        l.mfspr r5,r0,17
332 
        l.andi  r4,r5,0x200
333 
        l.add   r8,r8,r4
334 
 
335 
        l.sfgts r3,r4
336 
        l.mfspr r5,r0,17
337 
        l.andi  r4,r5,0x200
338 
        l.add   r8,r8,r4
339 
 
340 
        l.sfgtsi        r3,1
341 
        l.mfspr r5,r0,17
342 
        l.andi  r4,r5,0x200
343 
        l.add   r8,r8,r4
344 
 
345 
        l.sfgtsi        r3,-2
346 
        l.mfspr r5,r0,17
347 
        l.andi  r4,r5,0x200
348 
        l.add   r8,r8,r4
349 
 
350 
        l.sfges r3,r3
351 
        l.mfspr r5,r0,17
352 
        l.andi  r4,r5,0x200
353 
        l.add   r8,r8,r4
354 
 
355 
        l.sfges r3,r4
356 
        l.mfspr r5,r0,17
357 
        l.andi  r4,r5,0x200
358 
        l.add   r8,r8,r4
359 
 
360 
        l.sfgesi        r3,1
361 
        l.mfspr r5,r0,17
362 
        l.andi  r4,r5,0x200
363 
        l.add   r8,r8,r4
364 
 
365 
        l.sfgesi        r3,-2
366 
        l.mfspr r5,r0,17
367 
        l.andi  r4,r5,0x200
368 
        l.add   r8,r8,r4
369 
 
370 
        l.sflts r3,r3
371 
        l.mfspr r5,r0,17
372 
        l.andi  r4,r5,0x200
373 
        l.add   r8,r8,r4
374 
 
375 
        l.sflts r3,r4
376 
        l.mfspr r5,r0,17
377 
        l.andi  r4,r5,0x200
378 
        l.add   r8,r8,r4
379 
 
380 
        l.sfltsi        r3,1
381 
        l.mfspr r5,r0,17
382 
        l.andi  r4,r5,0x200
383 
        l.add   r8,r8,r4
384 
 
385 
        l.sfltsi        r3,-2
386 
        l.mfspr r5,r0,17
387 
        l.andi  r4,r5,0x200
388 
        l.add   r8,r8,r4
389 
 
390 
        l.sfles r3,r3
391 
        l.mfspr r5,r0,17
392 
        l.andi  r4,r5,0x200
393 
        l.add   r8,r8,r4
394 
 
395 
        l.sfles r3,r4
396 
        l.mfspr r5,r0,17
397 
        l.andi  r4,r5,0x200
398 
        l.add   r8,r8,r4
399 
 
400 
        l.sflesi        r3,1
401 
        l.mfspr r5,r0,17
402 
        l.andi  r4,r5,0x200
403 
        l.add   r8,r8,r4
404 
 
405 
        l.sflesi        r3,-2
406 
        l.mfspr r5,r0,17
407 
        l.andi  r4,r5,0x200
408 
        l.add   r8,r8,r4
409 
 
410 
        l.or  r3,r0,r8
411 
        l.nop NOP_REPORT        /* Should be 0x00002800 */
412 
 
413 
        l.lwz   r9,0(r31)
414 
        l.add   r8,r9,r8
415 
        l.sw    0(r31),r8
416 
 
417 
_jump:
418 
        l.addi  r8,r0,0
419 
 
420 
        l.j     _T1
421 
        l.addi  r8,r8,1
422 
 
423 
_T2:    l.jr    r9
424 
        l.addi  r8,r8,1
425 
 
426 
_T1:    l.jal   _T2
427 
        l.addi  r8,r8,1
428 
 
429 
        l.sfeqi r0,0
430 
        l.bf    _T3
431 
        l.addi  r8,r8,1
432 
 
433 
_T3:    l.sfeqi r0,1
434 
        l.bf    _T4
435 
        l.addi  r8,r8,1
436 
 
437 
        l.addi  r8,r8,1
438 
 
439 
_T4:    l.sfeqi r0,0
440 
        l.bnf    _T5
441 
        l.addi  r8,r8,1
442 
 
443 
        l.addi  r8,r8,1
444 
 
445 
_T5:    l.sfeqi r0,1
446 
        l.bnf    _T6
447 
        l.addi  r8,r8,1
448 
 
449 
        l.addi  r8,r8,1
450 
 
451 
_T6:    l.movhi r3,hi(_T7)
452 
        l.ori  r3,r3,lo(_T7)
453 
        l.mtspr r0,r3,32
454 
        l.mfspr r5,r0,17
455 
        l.mtspr r0,r5,64
456 
        l.rfe
457 
        l.addi  r8,r8,1         /* l.rfe should not have a delay slot */
458 
 
459 
        l.addi  r8,r8,1
460 
 
461 
_T7:    l.or  r3,r0,r8
462 
        l.nop NOP_REPORT        /* Should be 0x000000009 */
463 
 
464 
        l.lwz   r9,0(r31)
465 
        l.add   r8,r9,r8
466 
        l.sw    0(r31),r8
467 
 
468 
        l.lwz   r9,0(r31)
469 
        l.movhi r3,0x4c69
470 
        l.ori   r3,r3,0xe5f7
471 
        l.add   r8,r8,r3
472 
 
473 
        l.or  r3,r0,r8
474 
        l.nop NOP_REPORT        /* Should be 0xdeaddead */
475 
 
476 
        l.addi  r3,r0,0
477 
        l.nop NOP_EXIT
478 
 

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