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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [basic/] [basic.S] - Blame information for rev 214

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Line No. Rev Author Line
1 90 jeremybenn
/* basic.S. Basic instruction set test of Or1ksim
2
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
#include "spr-defs.h"
29
#include "board.h"
30
 
31
#define MEM_RAM 0x00000000
32
 
33
#define MC_CSR          (0x00)
34
#define MC_POC          (0x04)
35
#define MC_BA_MASK      (0x08)
36
#define MC_CSC(i)       (0x10 + (i) * 8)
37
#define MC_TMS(i)       (0x14 + (i) * 8)
38
 
39
        .section .except, "ax"
40
        l.addi    r1,r0,0
41
 
42
        .section .text
43
 
44
        .org 0x100
45
_reset:
46
        l.movhi r1,hi(_init_mc)
47
        l.ori   r1,r1,lo(_init_mc)
48
        l.jr    r1
49
        l.nop
50
 
51
 
52
_init_mc:
53
 
54
        l.movhi r3,hi(MC_BASE_ADDR)
55
        l.ori   r3,r3,lo(MC_BASE_ADDR)
56
 
57
        l.addi  r4,r3,MC_CSC(0)
58
        l.movhi r5,hi(FLASH_BASE_ADDR)
59
        l.srai  r5,r5,6
60
        l.ori   r5,r5,0x0025
61
        l.sw    0(r4),r5
62
 
63
        l.addi  r4,r3,MC_TMS(0)
64
        l.movhi r5,hi(FLASH_TMS_VAL)
65
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
66
        l.sw    0(r4),r5
67
 
68
        l.addi  r4,r3,MC_BA_MASK
69
        l.addi  r5,r0,MC_MASK_VAL
70
        l.sw    0(r4),r5
71
 
72
        l.addi  r4,r3,MC_CSR
73
        l.movhi r5,hi(MC_CSR_VAL)
74
        l.ori   r5,r5,lo(MC_CSR_VAL)
75
        l.sw    0(r4),r5
76
 
77
        l.addi  r4,r3,MC_TMS(1)
78
        l.movhi r5,hi(SDRAM_TMS_VAL)
79
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
80
        l.sw    0(r4),r5
81
 
82
        l.addi  r4,r3,MC_CSC(1)
83
        l.movhi r5,hi(SDRAM_BASE_ADDR)
84
        l.srai  r5,r5,6
85
        l.ori   r5,r5,0x0411
86
        l.sw    0(r4),r5
87
 
88
 
89
_regs:
90
        l.addi  r1,r0,0x1
91
        l.addi  r2,r1,0x2
92
        l.addi  r3,r2,0x4
93
        l.addi  r4,r3,0x8
94
        l.addi  r5,r4,0x10
95
        l.addi  r6,r5,0x20
96
        l.addi  r7,r6,0x40
97
        l.addi  r8,r7,0x80
98
        l.addi  r9,r8,0x100
99
        l.addi  r10,r9,0x200
100
        l.addi  r11,r10,0x400
101
        l.addi  r12,r11,0x800
102
        l.addi  r13,r12,0x1000
103
        l.addi  r14,r13,0x2000
104
        l.addi  r15,r14,0x4000
105
        l.addi  r16,r15,0x8000
106
 
107
        l.sub   r31,r0,r1
108
        l.sub   r30,r31,r2
109
        l.sub   r29,r30,r3
110
        l.sub   r28,r29,r4
111
        l.sub   r27,r28,r5
112
        l.sub   r26,r27,r6
113
        l.sub   r25,r26,r7
114
        l.sub   r24,r25,r8
115
        l.sub   r23,r24,r9
116
        l.sub   r22,r23,r10
117
        l.sub   r21,r22,r11
118
        l.sub   r20,r21,r12
119
        l.sub   r19,r20,r13
120
        l.sub   r18,r19,r14
121
        l.sub   r17,r18,r15
122
        l.sub   r16,r17,r16
123
 
124
        l.or  r3,r0,r16
125
        l.nop NOP_REPORT        /* Should be 0xffff0012 */
126
 
127
        l.movhi r31, hi(MEM_RAM)
128
        l.ori  r31,r31, lo(MEM_RAM)
129
        l.sw    0(r31),r16
130
 
131
_mem:   l.movhi r3,0x1234
132
        l.ori   r3,r3,0x5678
133
 
134
        l.sw    4(r31),r3
135
 
136
        l.lbz   r4,4(r31)
137
        l.add   r8,r8,r4
138
        l.sb    11(r31),r4
139
        l.lbz   r4,5(r31)
140
        l.add   r8,r8,r4
141
        l.sb    10(r31),r4
142
        l.lbz   r4,6(r31)
143
        l.add   r8,r8,r4
144
        l.sb    9(r31),r4
145
        l.lbz   r4,7(r31)
146
        l.add   r8,r8,r4
147
        l.sb    8(r31),r4
148
 
149
        l.lbs   r4,8(r31)
150
        l.add   r8,r8,r4
151
        l.sb    7(r31),r4
152
        l.lbs   r4,9(r31)
153
        l.add   r8,r8,r4
154
        l.sb    6(r31),r4
155
        l.lbs   r4,10(r31)
156
        l.add   r8,r8,r4
157
        l.sb    5(r31),r4
158
        l.lbs   r4,11(r31)
159
        l.add   r8,r8,r4
160
        l.sb    4(r31),r4
161
 
162
        l.lhz   r4,4(r31)
163
        l.add   r8,r8,r4
164
        l.sh    10(r31),r4
165
        l.lhz   r4,6(r31)
166
        l.add   r8,r8,r4
167
        l.sh    8(r31),r4
168
 
169
        l.lhs   r4,8(r31)
170
        l.add   r8,r8,r4
171
        l.sh    6(r31),r4
172
        l.lhs   r4,10(r31)
173
        l.add   r8,r8,r4
174
        l.sh    4(r31),r4
175
 
176
        l.lwz   r4,4(r31)
177
        l.add   r8,r8,r4
178
 
179
        l.or  r3,r0,r8
180
        l.nop NOP_REPORT        /* Should be 0x12352af7 */
181
 
182
        l.lwz   r9,0(r31)
183
        l.add   r8,r9,r8
184
        l.sw    0(r31),r8
185
 
186
_arith:
187
        l.addi  r3,r0,1
188
        l.addi  r4,r0,2
189
        l.addi  r5,r0,-1
190
        l.addi  r6,r0,-1
191
        l.addi  r8,r0,0
192
 
193
        l.sub   r7,r5,r3
194
        l.sub   r8,r3,r5
195
        l.add   r8,r8,r7
196
 
197
        l.div   r7,r7,r4
198
        l.add   r9,r3,r4
199
        l.mul   r7,r9,r7
200
        l.divu  r7,r7,r4
201
        l.add   r8,r8,r7
202
 
203
        l.or  r3,r0,r8
204
        l.nop NOP_REPORT        /* Should be 0x7ffffffe */
205
 
206
        l.lwz   r9,0(r31)
207
        l.add   r8,r9,r8
208
        l.sw    0(r31),r8
209
 
210
_log:
211
        l.addi  r3,r0,1
212
        l.addi  r4,r0,2
213
        l.addi  r5,r0,-1
214
        l.addi  r6,r0,-1
215
        l.addi  r8,r0,0
216
 
217
        l.andi  r8,r8,1
218
        l.and   r8,r8,r3
219
 
220
        l.xori  r8,r5,0xa5a5
221
        l.xor   r8,r8,r5
222
 
223
        l.ori   r8,r8,2
224
        l.or    r8,r8,r4
225
 
226
        l.or  r3,r0,r8
227
        l.nop NOP_REPORT        /* Should be 0xffffa5a7 */
228
 
229
        l.lwz   r9,0(r31)
230
        l.add   r8,r9,r8
231
        l.sw    0(r31),r8
232
 
233
_shift:
234
        l.addi  r3,r0,1
235
        l.addi  r4,r0,2
236
        l.addi  r5,r0,-1
237
        l.addi  r6,r0,-1
238
        l.addi  r8,r0,0
239
 
240
        l.slli  r8,r5,6
241
        l.sll   r8,r8,r4
242
 
243
        l.srli  r8,r8,6
244
        l.srl   r8,r8,r4
245
 
246
        l.srai  r8,r8,2
247
        l.sra   r8,r8,r4
248
 
249
        l.or  r3,r0,r8
250
        l.nop NOP_REPORT        /* Should be 0x000fffff */
251
 
252
        l.lwz   r9,0(r31)
253
        l.add   r8,r9,r8
254
        l.sw    0(r31),r8
255
 
256
_flag:
257
        l.addi  r3,r0,1
258
        l.addi  r4,r0,-2
259
        l.addi  r8,r0,0
260
 
261
        l.sfeq  r3,r3
262
        l.mfspr r5,r0,17
263
        l.andi  r4,r5,0x200
264
        l.add   r8,r8,r4
265
 
266
        l.sfeq  r3,r4
267
        l.mfspr r5,r0,17
268
        l.andi  r4,r5,0x200
269
        l.add   r8,r8,r4
270
 
271
        l.sfeqi r3,1
272
        l.mfspr r5,r0,17
273
        l.andi  r4,r5,0x200
274
        l.add   r8,r8,r4
275
 
276
        l.sfeqi r3,-2
277
        l.mfspr r5,r0,17
278
        l.andi  r4,r5,0x200
279
        l.add   r8,r8,r4
280
 
281
        l.sfne  r3,r3
282
        l.mfspr r5,r0,17
283
        l.andi  r4,r5,0x200
284
        l.add   r8,r8,r4
285
 
286
        l.sfne  r3,r4
287
        l.mfspr r5,r0,17
288
        l.andi  r4,r5,0x200
289
        l.add   r8,r8,r4
290
 
291
        l.sfnei r3,1
292
        l.mfspr r5,r0,17
293
        l.andi  r4,r5,0x200
294
        l.add   r8,r8,r4
295
 
296
        l.sfnei r3,-2
297
        l.mfspr r5,r0,17
298
        l.andi  r4,r5,0x200
299
        l.add   r8,r8,r4
300
 
301
        l.sfgtu r3,r3
302
        l.mfspr r5,r0,17
303
        l.andi  r4,r5,0x200
304
        l.add   r8,r8,r4
305
 
306
        l.sfgtu r3,r4
307
        l.mfspr r5,r0,17
308
        l.andi  r4,r5,0x200
309
        l.add   r8,r8,r4
310
 
311
        l.sfgtui        r3,1
312
        l.mfspr r5,r0,17
313
        l.andi  r4,r5,0x200
314
        l.add   r8,r8,r4
315
 
316
        l.sfgtui        r3,-2
317
        l.mfspr r5,r0,17
318
        l.andi  r4,r5,0x200
319
        l.add   r8,r8,r4
320
 
321
        l.sfgeu r3,r3
322
        l.mfspr r5,r0,17
323
        l.andi  r4,r5,0x200
324
        l.add   r8,r8,r4
325
 
326
        l.sfgeu r3,r4
327
        l.mfspr r5,r0,17
328
        l.andi  r4,r5,0x200
329
        l.add   r8,r8,r4
330
 
331
        l.sfgeui        r3,1
332
        l.mfspr r5,r0,17
333
        l.andi  r4,r5,0x200
334
        l.add   r8,r8,r4
335
 
336
        l.sfgeui        r3,-2
337
        l.mfspr r5,r0,17
338
        l.andi  r4,r5,0x200
339
        l.add   r8,r8,r4
340
 
341
        l.sfltu r3,r3
342
        l.mfspr r5,r0,17
343
        l.andi  r4,r5,0x200
344
        l.add   r8,r8,r4
345
 
346
        l.sfltu r3,r4
347
        l.mfspr r5,r0,17
348
        l.andi  r4,r5,0x200
349
        l.add   r8,r8,r4
350
 
351
        l.sfltui        r3,1
352
        l.mfspr r5,r0,17
353
        l.andi  r4,r5,0x200
354
        l.add   r8,r8,r4
355
 
356
        l.sfltui        r3,-2
357
        l.mfspr r5,r0,17
358
        l.andi  r4,r5,0x200
359
        l.add   r8,r8,r4
360
 
361
        l.sfleu r3,r3
362
        l.mfspr r5,r0,17
363
        l.andi  r4,r5,0x200
364
        l.add   r8,r8,r4
365
 
366
        l.sfleu r3,r4
367
        l.mfspr r5,r0,17
368
        l.andi  r4,r5,0x200
369
        l.add   r8,r8,r4
370
 
371
        l.sfleui        r3,1
372
        l.mfspr r5,r0,17
373
        l.andi  r4,r5,0x200
374
        l.add   r8,r8,r4
375
 
376
        l.sfleui        r3,-2
377
        l.mfspr r5,r0,17
378
        l.andi  r4,r5,0x200
379
        l.add   r8,r8,r4
380
 
381
        l.sfgts r3,r3
382
        l.mfspr r5,r0,17
383
        l.andi  r4,r5,0x200
384
        l.add   r8,r8,r4
385
 
386
        l.sfgts r3,r4
387
        l.mfspr r5,r0,17
388
        l.andi  r4,r5,0x200
389
        l.add   r8,r8,r4
390
 
391
        l.sfgtsi        r3,1
392
        l.mfspr r5,r0,17
393
        l.andi  r4,r5,0x200
394
        l.add   r8,r8,r4
395
 
396
        l.sfgtsi        r3,-2
397
        l.mfspr r5,r0,17
398
        l.andi  r4,r5,0x200
399
        l.add   r8,r8,r4
400
 
401
        l.sfges r3,r3
402
        l.mfspr r5,r0,17
403
        l.andi  r4,r5,0x200
404
        l.add   r8,r8,r4
405
 
406
        l.sfges r3,r4
407
        l.mfspr r5,r0,17
408
        l.andi  r4,r5,0x200
409
        l.add   r8,r8,r4
410
 
411
        l.sfgesi        r3,1
412
        l.mfspr r5,r0,17
413
        l.andi  r4,r5,0x200
414
        l.add   r8,r8,r4
415
 
416
        l.sfgesi        r3,-2
417
        l.mfspr r5,r0,17
418
        l.andi  r4,r5,0x200
419
        l.add   r8,r8,r4
420
 
421
        l.sflts r3,r3
422
        l.mfspr r5,r0,17
423
        l.andi  r4,r5,0x200
424
        l.add   r8,r8,r4
425
 
426
        l.sflts r3,r4
427
        l.mfspr r5,r0,17
428
        l.andi  r4,r5,0x200
429
        l.add   r8,r8,r4
430
 
431
        l.sfltsi        r3,1
432
        l.mfspr r5,r0,17
433
        l.andi  r4,r5,0x200
434
        l.add   r8,r8,r4
435
 
436
        l.sfltsi        r3,-2
437
        l.mfspr r5,r0,17
438
        l.andi  r4,r5,0x200
439
        l.add   r8,r8,r4
440
 
441
        l.sfles r3,r3
442
        l.mfspr r5,r0,17
443
        l.andi  r4,r5,0x200
444
        l.add   r8,r8,r4
445
 
446
        l.sfles r3,r4
447
        l.mfspr r5,r0,17
448
        l.andi  r4,r5,0x200
449
        l.add   r8,r8,r4
450
 
451
        l.sflesi        r3,1
452
        l.mfspr r5,r0,17
453
        l.andi  r4,r5,0x200
454
        l.add   r8,r8,r4
455
 
456
        l.sflesi        r3,-2
457
        l.mfspr r5,r0,17
458
        l.andi  r4,r5,0x200
459
        l.add   r8,r8,r4
460
 
461
        l.or  r3,r0,r8
462
        l.nop NOP_REPORT        /* Should be 0x00002800 */
463
 
464
        l.lwz   r9,0(r31)
465
        l.add   r8,r9,r8
466
        l.sw    0(r31),r8
467
 
468
_jump:
469
        l.addi  r8,r0,0
470
 
471
        l.j     _T1
472
        l.addi  r8,r8,1
473
 
474
_T2:    l.jr    r9
475
        l.addi  r8,r8,1
476
 
477
_T1:    l.jal   _T2
478
        l.addi  r8,r8,1
479
 
480
        l.sfeqi r0,0
481
        l.bf    _T3
482
        l.addi  r8,r8,1
483
 
484
_T3:    l.sfeqi r0,1
485
        l.bf    _T4
486
        l.addi  r8,r8,1
487
 
488
        l.addi  r8,r8,1
489
 
490
_T4:    l.sfeqi r0,0
491
        l.bnf    _T5
492
        l.addi  r8,r8,1
493
 
494
        l.addi  r8,r8,1
495
 
496
_T5:    l.sfeqi r0,1
497
        l.bnf    _T6
498
        l.addi  r8,r8,1
499
 
500
        l.addi  r8,r8,1
501
 
502
_T6:    l.movhi r3,hi(_T7)
503
        l.ori  r3,r3,lo(_T7)
504
        l.mtspr r0,r3,32
505
        l.mfspr r5,r0,17
506
        l.mtspr r0,r5,64
507
        l.rfe
508
        l.addi  r8,r8,1         /* l.rfe should not have a delay slot */
509
 
510
        l.addi  r8,r8,1
511
 
512
_T7:    l.or  r3,r0,r8
513
        l.nop NOP_REPORT        /* Should be 0x000000009 */
514
 
515
        l.lwz   r9,0(r31)
516
        l.add   r8,r9,r8
517
        l.sw    0(r31),r8
518
 
519
        l.lwz   r9,0(r31)
520
        l.movhi r3,0x4c69
521
        l.ori   r3,r3,0xe5f7
522
        l.add   r8,r8,r3
523
 
524
        l.or  r3,r0,r8
525
        l.nop NOP_REPORT        /* Should be 0xdeaddead */
526
 
527
        l.addi  r3,r0,0
528
        l.nop NOP_EXIT
529
 

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