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/* cache_asm.S. Machine code support for cache test of Or1ksim
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
#include "spr-defs.h"
#include "board.h"
 
#define IC_ENABLE 0
#define DC_ENABLE 0
 
        .extern main
 
        .global ic_enable
        .global ic_disable
        .global dc_enable
        .global dc_disable
        .global dc_inv
        .global ic_inv_test
        .global dc_inv_test
 
        .section .stack
        .space 0x1000
stack:
 
        .section .reset, "ax"
 
        .org    0x100
reset_vector:
        // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
        // and indeed it is not when simulating the or1200 Verilog core.
        l.andi  r0,r0,0x0
 
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
start:
 
        l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
        l.ori   r2,r1, 0
 
        l.movhi r3,hi(main)
        l.ori   r3,r3,lo(main)
        l.jr    r3
        l.nop
 
        .section .text
 
ic_enable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Invalidate IC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_ICBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable IC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_ICE
        l.mtspr r0,r13,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
ic_disable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_enable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Flush DC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_DCBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable DC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_DCE
        l.mtspr r0,r13,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_disable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_inv:
        l.mfspr r4,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r4,r5
        l.mtspr r0,r5,SPR_SR
        l.mtspr r0,r3,SPR_DCBIR
        l.mtspr r0,r4,SPR_SR
        l.jr    r9
        l.nop
 
        .align  0x10
ic_inv_test:
        l.movhi r7,hi(ic_test_1)
        l.ori   r7,r7,lo(ic_test_1)
        l.addi  r3,r0,0
        l.addi  r4,r0,0
        l.addi  r5,r0,0
        l.nop
        l.nop
        l.nop
 
ic_test_1:
3:      l.addi  r3,r3,1
 
        l.sfeqi r4,0x01
        l.bnf   1f
        l.nop
 
        l.mfspr r8,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r8,r11
        l.mtspr r0,r11,SPR_SR
        l.mtspr r0,r7,SPR_ICBIR
        l.mtspr r0,r8,SPR_SR
        l.bf    2f
        l.nop
 
1:      l.lwz   r6,0(r7)
        l.addi  r6,r6,1
        l.sw    0(r7),r6
 
2:      l.addi  r5,r5,1
        l.sfeqi r5,10
        l.bnf   3b
        l.xori  r4,r4,0x01
 
        l.addi  r11,r3,0
        l.jr    r9
        l.nop
 
dc_inv_test:
        l.movhi r4,hi(0x08040201)
        l.ori   r4,r4,lo(0x08040201)
        l.sw    0x00(r3),r4
        l.slli  r4,r4,1
        l.sw    0x14(r3),r4
        l.slli  r4,r4,1
        l.sw    0x28(r3),r4
 
        l.addi  r8,r9,0
        l.jal   dc_enable
        l.nop
        l.addi  r9,r8,0
 
        l.lbz   r4,0x03(r3)
        l.lhz   r5,0x16(r3)
        l.add   r4,r4,r5
        l.lwz   r5,0x28(r3)
        l.add   r4,r4,r5
 
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        l.addi  r7,r3,0x10
        l.mtspr r0,r7,SPR_DCBIR
 
        l.lwz   r5,0(r3)
        l.slli  r5,r5,3
        l.sw    0x00(r3),r5
        l.slli  r5,r5,1
        l.sw    0x14(r3),r5
        l.slli  r5,r5,1
        l.sw    0x28(r3),r5
 
        l.mtspr r0,r6,SPR_SR
 
        l.lbz   r5,0x03(r3)
        l.add   r4,r4,r5
        l.lhz   r5,0x16(r3)
        l.add   r4,r4,r5
        l.lwz   r5,0x28(r3)
        l.add   r4,r4,r5
 
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        l.addi  r11,r4,0x0
1:
        l.jr  r9
        l.nop

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* cache_asm.S. Machine code support for cache test of Or1ksim`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`#include "spr-defs.h"`
29			`#include "board.h"`
30
31			`#define IC_ENABLE 0`
32			`#define DC_ENABLE 0`
33
34	346	jeremybenn	`.extern main`
35	90	jeremybenn
36	346	jeremybenn	`.global ic_enable`
37			`.global ic_disable`
38			`.global dc_enable`
39			`.global dc_disable`
40			`.global dc_inv`
41			`.global ic_inv_test`
42			`.global dc_inv_test`
43	90	jeremybenn
44			`.section .stack`
45			`.space 0x1000`
46	346	jeremybenn	`stack:`
47	90	jeremybenn
48			`.section .reset, "ax"`
49
50			`.org 0x100`
51	346	jeremybenn	`reset_vector:`
52	787	jeremybenn	`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
53			`// and indeed it is not when simulating the or1200 Verilog core.`
54			`l.andi r0,r0,0x0`
55
56	90	jeremybenn	`l.addi r2,r0,0x0`
57			`l.addi r3,r0,0x0`
58			`l.addi r4,r0,0x0`
59			`l.addi r5,r0,0x0`
60			`l.addi r6,r0,0x0`
61			`l.addi r7,r0,0x0`
62			`l.addi r8,r0,0x0`
63			`l.addi r9,r0,0x0`
64			`l.addi r10,r0,0x0`
65			`l.addi r11,r0,0x0`
66			`l.addi r12,r0,0x0`
67			`l.addi r13,r0,0x0`
68			`l.addi r14,r0,0x0`
69			`l.addi r15,r0,0x0`
70			`l.addi r16,r0,0x0`
71			`l.addi r17,r0,0x0`
72			`l.addi r18,r0,0x0`
73			`l.addi r19,r0,0x0`
74			`l.addi r20,r0,0x0`
75			`l.addi r21,r0,0x0`
76			`l.addi r22,r0,0x0`
77			`l.addi r23,r0,0x0`
78			`l.addi r24,r0,0x0`
79			`l.addi r25,r0,0x0`
80			`l.addi r26,r0,0x0`
81			`l.addi r27,r0,0x0`
82			`l.addi r28,r0,0x0`
83			`l.addi r29,r0,0x0`
84			`l.addi r30,r0,0x0`
85			`l.addi r31,r0,0x0`
86
87			`l.movhi r3,hi(start)`
88			`l.ori r3,r3,lo(start)`
89			`l.jr r3`
90			`l.nop`
91			`start:`
92
93	346	jeremybenn	`l.movhi r1,hi(stack)`
94			`l.ori r1,r1,lo(stack)`
95	458	julius	`l.ori r2,r1, 0`
96
97			`l.movhi r3,hi(main)`
98			`l.ori r3,r3,lo(main)`
99			`l.jr r3`
100	90	jeremybenn	`l.nop`
101
102			`.section .text`
103
104	346	jeremybenn	`ic_enable:`
105	90	jeremybenn	`/* Disable IC */`
106			`l.mfspr r13,r0,SPR_SR`
107			`l.addi r11,r0,-1`
108			`l.xori r11,r11,SPR_SR_ICE`
109			`l.and r11,r13,r11`
110			`l.mtspr r0,r11,SPR_SR`
111
112			`/* Invalidate IC */`
113			`l.addi r13,r0,0`
114			`l.addi r11,r0,8192`
115			`1:`
116			`l.mtspr r0,r13,SPR_ICBIR`
117			`l.sfne r13,r11`
118			`l.bf 1b`
119			`l.addi r13,r13,16`
120
121			`/* Enable IC */`
122			`l.mfspr r13,r0,SPR_SR`
123			`l.ori r13,r13,SPR_SR_ICE`
124			`l.mtspr r0,r13,SPR_SR`
125			`l.nop`
126			`l.nop`
127			`l.nop`
128			`l.nop`
129			`l.nop`
130
131			`l.jr r9`
132			`l.nop`
133
134	346	jeremybenn	`ic_disable:`
135	90	jeremybenn	`/* Disable IC */`
136			`l.mfspr r13,r0,SPR_SR`
137			`l.addi r11,r0,-1`
138			`l.xori r11,r11,SPR_SR_ICE`
139			`l.and r11,r13,r11`
140			`l.mtspr r0,r11,SPR_SR`
141
142			`l.jr r9`
143			`l.nop`
144
145	346	jeremybenn	`dc_enable:`
146	90	jeremybenn	`/* Disable DC */`
147			`l.mfspr r13,r0,SPR_SR`
148			`l.addi r11,r0,-1`
149			`l.xori r11,r11,SPR_SR_DCE`
150			`l.and r11,r13,r11`
151			`l.mtspr r0,r11,SPR_SR`
152
153			`/* Flush DC */`
154			`l.addi r13,r0,0`
155			`l.addi r11,r0,8192`
156			`1:`
157			`l.mtspr r0,r13,SPR_DCBIR`
158			`l.sfne r13,r11`
159			`l.bf 1b`
160			`l.addi r13,r13,16`
161
162			`/* Enable DC */`
163			`l.mfspr r13,r0,SPR_SR`
164			`l.ori r13,r13,SPR_SR_DCE`
165			`l.mtspr r0,r13,SPR_SR`
166
167			`l.jr r9`
168			`l.nop`
169
170	346	jeremybenn	`dc_disable:`
171	90	jeremybenn	`/* Disable DC */`
172			`l.mfspr r13,r0,SPR_SR`
173			`l.addi r11,r0,-1`
174			`l.xori r11,r11,SPR_SR_DCE`
175			`l.and r11,r13,r11`
176			`l.mtspr r0,r11,SPR_SR`
177
178			`l.jr r9`
179			`l.nop`
180
181	346	jeremybenn	`dc_inv:`
182	90	jeremybenn	`l.mfspr r4,r0,SPR_SR`
183			`l.addi r5,r0,-1`
184			`l.xori r5,r5,SPR_SR_DCE`
185			`l.and r5,r4,r5`
186			`l.mtspr r0,r5,SPR_SR`
187			`l.mtspr r0,r3,SPR_DCBIR`
188			`l.mtspr r0,r4,SPR_SR`
189			`l.jr r9`
190			`l.nop`
191
192			`.align 0x10`
193	346	jeremybenn	`ic_inv_test:`
194			`l.movhi r7,hi(ic_test_1)`
195			`l.ori r7,r7,lo(ic_test_1)`
196	90	jeremybenn	`l.addi r3,r0,0`
197			`l.addi r4,r0,0`
198			`l.addi r5,r0,0`
199			`l.nop`
200			`l.nop`
201			`l.nop`
202
203	346	jeremybenn	`ic_test_1:`
204	90	jeremybenn	`3: l.addi r3,r3,1`
205
206			`l.sfeqi r4,0x01`
207			`l.bnf 1f`
208			`l.nop`
209
210			`l.mfspr r8,r0,SPR_SR`
211			`l.addi r11,r0,-1`
212			`l.xori r11,r11,SPR_SR_ICE`
213			`l.and r11,r8,r11`
214			`l.mtspr r0,r11,SPR_SR`
215			`l.mtspr r0,r7,SPR_ICBIR`
216			`l.mtspr r0,r8,SPR_SR`
217			`l.bf 2f`
218			`l.nop`
219
220			`1: l.lwz r6,0(r7)`
221			`l.addi r6,r6,1`
222			`l.sw 0(r7),r6`
223
224			`2: l.addi r5,r5,1`
225			`l.sfeqi r5,10`
226			`l.bnf 3b`
227			`l.xori r4,r4,0x01`
228
229			`l.addi r11,r3,0`
230			`l.jr r9`
231			`l.nop`
232
233	346	jeremybenn	`dc_inv_test:`
234	90	jeremybenn	`l.movhi r4,hi(0x08040201)`
235			`l.ori r4,r4,lo(0x08040201)`
236			`l.sw 0x00(r3),r4`
237			`l.slli r4,r4,1`
238			`l.sw 0x14(r3),r4`
239			`l.slli r4,r4,1`
240			`l.sw 0x28(r3),r4`
241
242			`l.addi r8,r9,0`
243	346	jeremybenn	`l.jal dc_enable`
244	90	jeremybenn	`l.nop`
245			`l.addi r9,r8,0`
246
247			`l.lbz r4,0x03(r3)`
248			`l.lhz r5,0x16(r3)`
249			`l.add r4,r4,r5`
250			`l.lwz r5,0x28(r3)`
251			`l.add r4,r4,r5`
252
253			`l.mfspr r6,r0,SPR_SR`
254			`l.addi r5,r0,-1`
255			`l.xori r5,r5,SPR_SR_DCE`
256			`l.and r5,r6,r5`
257			`l.mtspr r0,r5,SPR_SR`
258			`l.addi r7,r3,0x10`
259			`l.mtspr r0,r7,SPR_DCBIR`
260
261			`l.lwz r5,0(r3)`
262			`l.slli r5,r5,3`
263			`l.sw 0x00(r3),r5`
264			`l.slli r5,r5,1`
265			`l.sw 0x14(r3),r5`
266			`l.slli r5,r5,1`
267			`l.sw 0x28(r3),r5`
268
269			`l.mtspr r0,r6,SPR_SR`
270
271			`l.lbz r5,0x03(r3)`
272			`l.add r4,r4,r5`
273			`l.lhz r5,0x16(r3)`
274			`l.add r4,r4,r5`
275			`l.lwz r5,0x28(r3)`
276			`l.add r4,r4,r5`
277
278			`l.addi r5,r0,-1`
279			`l.xori r5,r5,SPR_SR_DCE`
280			`l.and r5,r6,r5`
281			`l.mtspr r0,r5,SPR_SR`
282
283			`l.addi r11,r4,0x0`
284			`1:`
285			`l.jr r9`
286			`l.nop`

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