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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [cache/] [cache-asm.S] - Blame information for rev 430

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/* cache_asm.S. Machine code support for cache test of Or1ksim
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
#include "spr-defs.h"
#include "board.h"
 
#define IC_ENABLE 0
#define DC_ENABLE 0
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
 
        .extern main
 
        .global ic_enable
        .global ic_disable
        .global dc_enable
        .global dc_disable
        .global dc_inv
        .global ic_inv_test
        .global dc_inv_test
 
        .section .stack
        .space 0x1000
stack:
 
        .section .reset, "ax"
 
        .org    0x100
reset_vector:
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
start:
        l.jal   init_mc
        l.nop
 
        l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
 
        /* Copy data section */
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r2,hi(main)
        l.ori   r2,r2,lo(main)
        l.jr    r2
        l.nop
 
init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
 
 
        .section .text
 
ic_enable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Invalidate IC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_ICBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable IC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_ICE
        l.mtspr r0,r13,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
ic_disable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_enable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Flush DC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_DCBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable DC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_DCE
        l.mtspr r0,r13,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_disable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_inv:
        l.mfspr r4,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r4,r5
        l.mtspr r0,r5,SPR_SR
        l.mtspr r0,r3,SPR_DCBIR
        l.mtspr r0,r4,SPR_SR
        l.jr    r9
        l.nop
 
        .align  0x10
ic_inv_test:
        l.movhi r7,hi(ic_test_1)
        l.ori   r7,r7,lo(ic_test_1)
        l.addi  r3,r0,0
        l.addi  r4,r0,0
        l.addi  r5,r0,0
        l.nop
        l.nop
        l.nop
 
ic_test_1:
3:      l.addi  r3,r3,1
 
        l.sfeqi r4,0x01
        l.bnf   1f
        l.nop
 
        l.mfspr r8,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r8,r11
        l.mtspr r0,r11,SPR_SR
        l.mtspr r0,r7,SPR_ICBIR
        l.mtspr r0,r8,SPR_SR
        l.bf    2f
        l.nop
 
1:      l.lwz   r6,0(r7)
        l.addi  r6,r6,1
        l.sw    0(r7),r6
 
2:      l.addi  r5,r5,1
        l.sfeqi r5,10
        l.bnf   3b
        l.xori  r4,r4,0x01
 
        l.addi  r11,r3,0
        l.jr    r9
        l.nop
 
dc_inv_test:
        l.movhi r4,hi(0x08040201)
        l.ori   r4,r4,lo(0x08040201)
        l.sw    0x00(r3),r4
        l.slli  r4,r4,1
        l.sw    0x14(r3),r4
        l.slli  r4,r4,1
        l.sw    0x28(r3),r4
 
        l.addi  r8,r9,0
        l.jal   dc_enable
        l.nop
        l.addi  r9,r8,0
 
        l.lbz   r4,0x03(r3)
        l.lhz   r5,0x16(r3)
        l.add   r4,r4,r5
        l.lwz   r5,0x28(r3)
        l.add   r4,r4,r5
 
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        l.addi  r7,r3,0x10
        l.mtspr r0,r7,SPR_DCBIR
 
        l.lwz   r5,0(r3)
        l.slli  r5,r5,3
        l.sw    0x00(r3),r5
        l.slli  r5,r5,1
        l.sw    0x14(r3),r5
        l.slli  r5,r5,1
        l.sw    0x28(r3),r5
 
        l.mtspr r0,r6,SPR_SR
 
        l.lbz   r5,0x03(r3)
        l.add   r4,r4,r5
        l.lhz   r5,0x16(r3)
        l.add   r4,r4,r5
        l.lwz   r5,0x28(r3)
        l.add   r4,r4,r5
 
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        l.addi  r11,r4,0x0
1:
        l.jr  r9
        l.nop

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* cache_asm.S. Machine code support for cache test of Or1ksim`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`#include "spr-defs.h"`
29			`#include "board.h"`
30
31			`#define IC_ENABLE 0`
32			`#define DC_ENABLE 0`
33
34			`#define MC_CSR (0x00)`
35			`#define MC_POC (0x04)`
36			`#define MC_BA_MASK (0x08)`
37			`#define MC_CSC(i) (0x10 + (i) * 8)`
38			`#define MC_TMS(i) (0x14 + (i) * 8)`
39
40
41	346	jeremybenn	`.extern main`
42	90	jeremybenn
43	346	jeremybenn	`.global ic_enable`
44			`.global ic_disable`
45			`.global dc_enable`
46			`.global dc_disable`
47			`.global dc_inv`
48			`.global ic_inv_test`
49			`.global dc_inv_test`
50	90	jeremybenn
51			`.section .stack`
52			`.space 0x1000`
53	346	jeremybenn	`stack:`
54	90	jeremybenn
55			`.section .reset, "ax"`
56
57			`.org 0x100`
58	346	jeremybenn	`reset_vector:`
59	90	jeremybenn	`l.addi r2,r0,0x0`
60			`l.addi r3,r0,0x0`
61			`l.addi r4,r0,0x0`
62			`l.addi r5,r0,0x0`
63			`l.addi r6,r0,0x0`
64			`l.addi r7,r0,0x0`
65			`l.addi r8,r0,0x0`
66			`l.addi r9,r0,0x0`
67			`l.addi r10,r0,0x0`
68			`l.addi r11,r0,0x0`
69			`l.addi r12,r0,0x0`
70			`l.addi r13,r0,0x0`
71			`l.addi r14,r0,0x0`
72			`l.addi r15,r0,0x0`
73			`l.addi r16,r0,0x0`
74			`l.addi r17,r0,0x0`
75			`l.addi r18,r0,0x0`
76			`l.addi r19,r0,0x0`
77			`l.addi r20,r0,0x0`
78			`l.addi r21,r0,0x0`
79			`l.addi r22,r0,0x0`
80			`l.addi r23,r0,0x0`
81			`l.addi r24,r0,0x0`
82			`l.addi r25,r0,0x0`
83			`l.addi r26,r0,0x0`
84			`l.addi r27,r0,0x0`
85			`l.addi r28,r0,0x0`
86			`l.addi r29,r0,0x0`
87			`l.addi r30,r0,0x0`
88			`l.addi r31,r0,0x0`
89
90			`l.movhi r3,hi(start)`
91			`l.ori r3,r3,lo(start)`
92			`l.jr r3`
93			`l.nop`
94			`start:`
95	346	jeremybenn	`l.jal init_mc`
96	90	jeremybenn	`l.nop`
97
98	346	jeremybenn	`l.movhi r1,hi(stack)`
99			`l.ori r1,r1,lo(stack)`
100	90	jeremybenn
101			`/* Copy data section */`
102			`l.movhi r3,hi(_src_beg)`
103			`l.ori r3,r3,lo(_src_beg)`
104			`l.movhi r4,hi(_dst_beg)`
105			`l.ori r4,r4,lo(_dst_beg)`
106			`l.movhi r5,hi(_dst_end)`
107			`l.ori r5,r5,lo(_dst_end)`
108			`l.sub r5,r5,r4`
109			`l.sfeqi r5,0`
110			`l.bf 2f`
111			`l.nop`
112			`1: l.lwz r6,0(r3)`
113			`l.sw 0(r4),r6`
114			`l.addi r3,r3,4`
115			`l.addi r4,r4,4`
116			`l.addi r5,r5,-4`
117			`l.sfgtsi r5,0`
118			`l.bf 1b`
119			`l.nop`
120			`2:`
121	346	jeremybenn	`l.movhi r2,hi(main)`
122			`l.ori r2,r2,lo(main)`
123	90	jeremybenn	`l.jr r2`
124			`l.nop`
125
126	346	jeremybenn	`init_mc:`
127	90	jeremybenn
128			`l.movhi r3,hi(MC_BASE_ADDR)`
129			`l.ori r3,r3,lo(MC_BASE_ADDR)`
130
131			`l.addi r4,r3,MC_CSC(0)`
132			`l.movhi r5,hi(FLASH_BASE_ADDR)`
133			`l.srai r5,r5,6`
134			`l.ori r5,r5,0x0025`
135			`l.sw 0(r4),r5`
136
137			`l.addi r4,r3,MC_TMS(0)`
138			`l.movhi r5,hi(FLASH_TMS_VAL)`
139			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
140			`l.sw 0(r4),r5`
141
142			`l.addi r4,r3,MC_BA_MASK`
143			`l.addi r5,r0,MC_MASK_VAL`
144			`l.sw 0(r4),r5`
145
146			`l.addi r4,r3,MC_CSR`
147			`l.movhi r5,hi(MC_CSR_VAL)`
148			`l.ori r5,r5,lo(MC_CSR_VAL)`
149			`l.sw 0(r4),r5`
150
151			`l.addi r4,r3,MC_TMS(1)`
152			`l.movhi r5,hi(SDRAM_TMS_VAL)`
153			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
154			`l.sw 0(r4),r5`
155
156			`l.addi r4,r3,MC_CSC(1)`
157			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
158			`l.srai r5,r5,6`
159			`l.ori r5,r5,0x0411`
160			`l.sw 0(r4),r5`
161
162			`l.jr r9`
163			`l.nop`
164
165
166			`.section .text`
167
168	346	jeremybenn	`ic_enable:`
169	90	jeremybenn	`/* Disable IC */`
170			`l.mfspr r13,r0,SPR_SR`
171			`l.addi r11,r0,-1`
172			`l.xori r11,r11,SPR_SR_ICE`
173			`l.and r11,r13,r11`
174			`l.mtspr r0,r11,SPR_SR`
175
176			`/* Invalidate IC */`
177			`l.addi r13,r0,0`
178			`l.addi r11,r0,8192`
179			`1:`
180			`l.mtspr r0,r13,SPR_ICBIR`
181			`l.sfne r13,r11`
182			`l.bf 1b`
183			`l.addi r13,r13,16`
184
185			`/* Enable IC */`
186			`l.mfspr r13,r0,SPR_SR`
187			`l.ori r13,r13,SPR_SR_ICE`
188			`l.mtspr r0,r13,SPR_SR`
189			`l.nop`
190			`l.nop`
191			`l.nop`
192			`l.nop`
193			`l.nop`
194
195			`l.jr r9`
196			`l.nop`
197
198	346	jeremybenn	`ic_disable:`
199	90	jeremybenn	`/* Disable IC */`
200			`l.mfspr r13,r0,SPR_SR`
201			`l.addi r11,r0,-1`
202			`l.xori r11,r11,SPR_SR_ICE`
203			`l.and r11,r13,r11`
204			`l.mtspr r0,r11,SPR_SR`
205
206			`l.jr r9`
207			`l.nop`
208
209	346	jeremybenn	`dc_enable:`
210	90	jeremybenn	`/* Disable DC */`
211			`l.mfspr r13,r0,SPR_SR`
212			`l.addi r11,r0,-1`
213			`l.xori r11,r11,SPR_SR_DCE`
214			`l.and r11,r13,r11`
215			`l.mtspr r0,r11,SPR_SR`
216
217			`/* Flush DC */`
218			`l.addi r13,r0,0`
219			`l.addi r11,r0,8192`
220			`1:`
221			`l.mtspr r0,r13,SPR_DCBIR`
222			`l.sfne r13,r11`
223			`l.bf 1b`
224			`l.addi r13,r13,16`
225
226			`/* Enable DC */`
227			`l.mfspr r13,r0,SPR_SR`
228			`l.ori r13,r13,SPR_SR_DCE`
229			`l.mtspr r0,r13,SPR_SR`
230
231			`l.jr r9`
232			`l.nop`
233
234	346	jeremybenn	`dc_disable:`
235	90	jeremybenn	`/* Disable DC */`
236			`l.mfspr r13,r0,SPR_SR`
237			`l.addi r11,r0,-1`
238			`l.xori r11,r11,SPR_SR_DCE`
239			`l.and r11,r13,r11`
240			`l.mtspr r0,r11,SPR_SR`
241
242			`l.jr r9`
243			`l.nop`
244
245	346	jeremybenn	`dc_inv:`
246	90	jeremybenn	`l.mfspr r4,r0,SPR_SR`
247			`l.addi r5,r0,-1`
248			`l.xori r5,r5,SPR_SR_DCE`
249			`l.and r5,r4,r5`
250			`l.mtspr r0,r5,SPR_SR`
251			`l.mtspr r0,r3,SPR_DCBIR`
252			`l.mtspr r0,r4,SPR_SR`
253			`l.jr r9`
254			`l.nop`
255
256			`.align 0x10`
257	346	jeremybenn	`ic_inv_test:`
258			`l.movhi r7,hi(ic_test_1)`
259			`l.ori r7,r7,lo(ic_test_1)`
260	90	jeremybenn	`l.addi r3,r0,0`
261			`l.addi r4,r0,0`
262			`l.addi r5,r0,0`
263			`l.nop`
264			`l.nop`
265			`l.nop`
266
267	346	jeremybenn	`ic_test_1:`
268	90	jeremybenn	`3: l.addi r3,r3,1`
269
270			`l.sfeqi r4,0x01`
271			`l.bnf 1f`
272			`l.nop`
273
274			`l.mfspr r8,r0,SPR_SR`
275			`l.addi r11,r0,-1`
276			`l.xori r11,r11,SPR_SR_ICE`
277			`l.and r11,r8,r11`
278			`l.mtspr r0,r11,SPR_SR`
279			`l.mtspr r0,r7,SPR_ICBIR`
280			`l.mtspr r0,r8,SPR_SR`
281			`l.bf 2f`
282			`l.nop`
283
284			`1: l.lwz r6,0(r7)`
285			`l.addi r6,r6,1`
286			`l.sw 0(r7),r6`
287
288			`2: l.addi r5,r5,1`
289			`l.sfeqi r5,10`
290			`l.bnf 3b`
291			`l.xori r4,r4,0x01`
292
293			`l.addi r11,r3,0`
294			`l.jr r9`
295			`l.nop`
296
297	346	jeremybenn	`dc_inv_test:`
298	90	jeremybenn	`l.movhi r4,hi(0x08040201)`
299			`l.ori r4,r4,lo(0x08040201)`
300			`l.sw 0x00(r3),r4`
301			`l.slli r4,r4,1`
302			`l.sw 0x14(r3),r4`
303			`l.slli r4,r4,1`
304			`l.sw 0x28(r3),r4`
305
306			`l.addi r8,r9,0`
307	346	jeremybenn	`l.jal dc_enable`
308	90	jeremybenn	`l.nop`
309			`l.addi r9,r8,0`
310
311			`l.lbz r4,0x03(r3)`
312			`l.lhz r5,0x16(r3)`
313			`l.add r4,r4,r5`
314			`l.lwz r5,0x28(r3)`
315			`l.add r4,r4,r5`
316
317			`l.mfspr r6,r0,SPR_SR`
318			`l.addi r5,r0,-1`
319			`l.xori r5,r5,SPR_SR_DCE`
320			`l.and r5,r6,r5`
321			`l.mtspr r0,r5,SPR_SR`
322			`l.addi r7,r3,0x10`
323			`l.mtspr r0,r7,SPR_DCBIR`
324
325			`l.lwz r5,0(r3)`
326			`l.slli r5,r5,3`
327			`l.sw 0x00(r3),r5`
328			`l.slli r5,r5,1`
329			`l.sw 0x14(r3),r5`
330			`l.slli r5,r5,1`
331			`l.sw 0x28(r3),r5`
332
333			`l.mtspr r0,r6,SPR_SR`
334
335			`l.lbz r5,0x03(r3)`
336			`l.add r4,r4,r5`
337			`l.lhz r5,0x16(r3)`
338			`l.add r4,r4,r5`
339			`l.lwz r5,0x28(r3)`
340			`l.add r4,r4,r5`
341
342			`l.addi r5,r0,-1`
343			`l.xori r5,r5,SPR_SR_DCE`
344			`l.and r5,r6,r5`
345			`l.mtspr r0,r5,SPR_SR`
346
347			`l.addi r11,r4,0x0`
348			`1:`
349			`l.jr r9`
350			`l.nop`

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