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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [cfg/] [cfg.S] - Blame information for rev 791

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Line No. Rev Author Line
1 90 jeremybenn 
/* cfg.s. CPU configuration test of Or1ksim
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   Copyright (C) 1999-2006 OpenCores
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   Copyright (C) 2010 Embecosm Limited
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   Contributors various OpenCores participants
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   Contributor Jeremy Bennett
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see .  */
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/* ----------------------------------------------------------------------------
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   This code is commented throughout for use with Doxygen.
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   --------------------------------------------------------------------------*/
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#include "spr-defs.h"
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30 458 julius 
        .section .except,"ax"
31 90 jeremybenn 
        .org 0x100
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_reset:
33 787 jeremybenn 
        // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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        // and indeed it is not when simulating the or1200 Verilog core.
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        l.andi  r0,r0,0x0
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37 90 jeremybenn 
        l.addi  r1,r0,0x7f00
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        l.movhi r2,hi(_main)
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        l.ori   r2,r2,lo(_main)
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        l.jr    r2
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        l.nop
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43 458 julius 
        .section .text
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_main:
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        l.addi  r2,r0,0
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        l.mfspr r3,r0,SPR_VR            /* Version */
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  l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_UPR           /* Unit Present */
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  l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r4,r0,SPR_PMR           /* Power Management */
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        l.addi  r3,r0,0
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        l.mtspr r0,r3,SPR_PMR
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        l.mfspr r3,r0,SPR_PMR
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        l.andi  r3,r3,0xff
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.addi  r3,r0,5
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        l.mtspr r0,r3,SPR_PMR
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        l.mfspr r3,r0,SPR_PMR
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        l.andi  r3,r3,0xff
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mtspr r0,r4,SPR_PMR
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        l.mfspr r3,r0,SPR_CPUCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_DMMUCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_IMMUCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_DCCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_ICCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_DCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        l.mfspr r3,r0,SPR_PCCFGR
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        l.nop NOP_REPORT
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        l.add   r2,r2,r3
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        /* Configurations may differ, so we will insert another report*/
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        l.movhi r3,hi(0xdeacf5cc)
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        l.ori   r3,r3,lo(0xdeacf5cc)
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        l.add   r3,r2,r3
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  l.nop NOP_REPORT
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        l.movhi r3,hi(0xdeaddead)
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        l.ori   r3,r3,lo(0xdeaddead)
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  l.nop NOP_REPORT
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        l.addi  r3,r0,0
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        l.nop NOP_EXIT

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