OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [default.ld] - Blame information for rev 153

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* default.ld. Default linker script for Or1ksim test programs
2
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
MEMORY
29
        {
30
        except : ORIGIN = 0x00000000, LENGTH = 0x00002000
31
        flash  : ORIGIN = 0xf0000000, LENGTH = 0x00200000
32
        ram    : ORIGIN = 0x00002000, LENGTH = 0x001fe000
33
        }
34
 
35
SECTIONS
36
{
37
        /* Section .except-text guarantees that the code for exception
38
           handling is placed first. For some reason the linker script can't
39
           see the _reset_vector symbol (even if we declare it global), so we
40
           explicitly set it. */
41
        .text :
42
        {
43
        *(.except-text)
44
        *(.text)
45
        *(.rodata)
46
        _reset_vector = DEFINED (_reset_vector) ? _reset_vector : 0x00000100;
47
        _src_beg = .;
48
        } > flash
49
 
50
        .dummy ALIGN(0x4):
51
        {
52
         _src_beg = .;
53
        } > flash
54
 
55
        .except :
56
        AT ( ADDR (.dummy))
57
        {
58
        _except_beg = .;
59
        *(.except)
60
        _except_end = .;
61
        } > except
62
 
63
        .data :
64
        AT ( ADDR (.dummy) + SIZEOF (.except))
65
        {
66
        _dst_beg = .;
67
        *(.data)
68
        *(.data.rel)
69
        *(.data.rel.local)
70
        _dst_end = .;
71
        } > ram
72
 
73
        .bss :
74
        {
75
        *(.bss)
76
        } > ram
77
 
78
        .stack  ALIGN(0x10) (NOLOAD):
79
        {
80
        *(.stack)
81
        _ram_end = .;
82
        } > ram
83
}
84
 
85
ENTRY (_reset_vector)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.