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/* except.s. Exception handling support for Or1k tests
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
#include "spr-defs.h"
#include "board.h"
 
#define reset reset
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
        .section .stack
        .space 0x1000
stack:
 
        .extern reset_support
        .extern c_reset
        .extern excpt_buserr
        .extern excpt_dpfault
        .extern excpt_ipfault
        .extern excpt_tick
        .extern excpt_align
        .extern excpt_illinsn
        .extern excpt_int
        .extern excpt_dtlbmiss
        .extern excpt_itlbmiss
        .extern excpt_range
        .extern excpt_syscall
        .extern excpt_break
        .extern excpt_trap
 
 
        .section .except, "ax"
buserr_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_buserr)
        l.ori   r10,r10,lo(excpt_buserr)
        l.jr    r9
        l.nop
buserr_vector_end:
 
dpfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_dpfault)
        l.ori   r10,r10,lo(excpt_dpfault)
        l.jr    r9
        l.nop
dpfault_vector_end:
 
ipfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_ipfault)
        l.ori   r10,r10,lo(excpt_ipfault)
        l.jr    r9
        l.nop
ipfault_vector_end:
 
lpint_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_tick)
        l.ori   r10,r10,lo(excpt_tick)
        l.jr    r9
        l.nop
lpint_vector_end:
 
align_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_align)
        l.ori   r10,r10,lo(excpt_align)
        l.jr    r9
        l.nop
align_vector_end:
 
illinsn_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_illinsn)
        l.ori   r10,r10,lo(excpt_illinsn)
        l.jr    r9
        l.nop
illinsn_vector_end:
 
hpint_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_int)
        l.ori   r10,r10,lo(excpt_int)
        l.jr    r9
        l.nop
hpint_vector_end:
 
dtlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_dtlbmiss)
        l.ori   r10,r10,lo(excpt_dtlbmiss)
        l.jr    r9
        l.nop
dtlbmiss_vector_end:
 
itlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_itlbmiss)
        l.ori   r10,r10,lo(excpt_itlbmiss)
        l.jr    r9
        l.nop
itlbmiss_vector_end:
 
range_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_range)
        l.ori   r10,r10,lo(excpt_range)
        l.jr    r9
        l.nop
range_vector_end:
 
syscall_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_syscall)
        l.ori   r10,r10,lo(excpt_syscall)
        l.jr    r9
        l.nop
syscall_vector_end:
 
break_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_break)
        l.ori   r10,r10,lo(excpt_break)
        l.jr    r9
        l.nop
break_vector_end:
 
trap_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_trap)
        l.ori   r10,r10,lo(excpt_trap)
        l.jr    r9
        l.nop
trap_vector_end:
 
        /* Our special text section is used to guarantee this code goes first
           when linking. */
        .section .except-text
 
        .org    0x100
        .align  4
reset_vector:
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
        .global start
start:
        l.jal   init_mc
        l.nop
 
        l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
 
        /* Setup exception wrappers */
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.addi  r7,r0,0x100
 
1:      l.addi  r7,r7,0x100
        l.sfeqi r7,0xf00
        l.bf    1f
        l.nop
        l.addi  r4,r7,0
        l.addi  r5,r0,0
2:
        l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,1
        l.sfeqi r5,9
        l.bf    1b
        l.nop
        l.j     2b
        l.nop
1:
        /* Copy data section */
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
 
2:
 
        l.movhi r2,hi(reset)
        l.ori   r2,r2,lo(reset)
        l.jr    r2
        l.nop
 
init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
 
store_regs:
        l.sw    0x00(r1),r2
        l.sw    0x04(r1),r3
        l.sw    0x08(r1),r4
        l.sw    0x0c(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
end_except:
        l.lwz   r2,0x00(r1)
        l.lwz   r3,0x04(r1)
        l.lwz   r4,0x08(r1)
        l.lwz   r5,0x0c(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.addi  r1,r1,120
        l.rfe
        l.nop

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except.s. Exception handling support for Or1k tests`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`#include "spr-defs.h"`
29			`#include "board.h"`
30
31	346	jeremybenn	`#define reset reset`
32	90	jeremybenn
33			`#define MC_CSR (0x00)`
34			`#define MC_POC (0x04)`
35			`#define MC_BA_MASK (0x08)`
36			`#define MC_CSC(i) (0x10 + (i) * 8)`
37			`#define MC_TMS(i) (0x14 + (i) * 8)`
38
39			`.section .stack`
40			`.space 0x1000`
41	346	jeremybenn	`stack:`
42	90	jeremybenn
43	346	jeremybenn	`.extern reset_support`
44			`.extern c_reset`
45			`.extern excpt_buserr`
46			`.extern excpt_dpfault`
47			`.extern excpt_ipfault`
48			`.extern excpt_tick`
49			`.extern excpt_align`
50			`.extern excpt_illinsn`
51			`.extern excpt_int`
52			`.extern excpt_dtlbmiss`
53			`.extern excpt_itlbmiss`
54			`.extern excpt_range`
55			`.extern excpt_syscall`
56			`.extern excpt_break`
57			`.extern excpt_trap`
58	90	jeremybenn
59
60			`.section .except, "ax"`
61	346	jeremybenn	`buserr_vector:`
62	90	jeremybenn	`l.addi r1,r1,-120`
63			`l.sw 0x1c(r1),r9`
64			`l.sw 0x20(r1),r10`
65			`l.movhi r9,hi(store_regs)`
66			`l.ori r9,r9,lo(store_regs)`
67	346	jeremybenn	`l.movhi r10,hi(excpt_buserr)`
68			`l.ori r10,r10,lo(excpt_buserr)`
69	90	jeremybenn	`l.jr r9`
70			`l.nop`
71	346	jeremybenn	`buserr_vector_end:`
72	90	jeremybenn
73	346	jeremybenn	`dpfault_vector:`
74	90	jeremybenn	`l.addi r1,r1,-120`
75			`l.sw 0x1c(r1),r9`
76			`l.sw 0x20(r1),r10`
77			`l.movhi r9,hi(store_regs)`
78			`l.ori r9,r9,lo(store_regs)`
79	346	jeremybenn	`l.movhi r10,hi(excpt_dpfault)`
80			`l.ori r10,r10,lo(excpt_dpfault)`
81	90	jeremybenn	`l.jr r9`
82			`l.nop`
83	346	jeremybenn	`dpfault_vector_end:`
84	90	jeremybenn
85	346	jeremybenn	`ipfault_vector:`
86	90	jeremybenn	`l.addi r1,r1,-120`
87			`l.sw 0x1c(r1),r9`
88			`l.sw 0x20(r1),r10`
89			`l.movhi r9,hi(store_regs)`
90			`l.ori r9,r9,lo(store_regs)`
91	346	jeremybenn	`l.movhi r10,hi(excpt_ipfault)`
92			`l.ori r10,r10,lo(excpt_ipfault)`
93	90	jeremybenn	`l.jr r9`
94			`l.nop`
95	346	jeremybenn	`ipfault_vector_end:`
96	90	jeremybenn
97	346	jeremybenn	`lpint_vector:`
98	90	jeremybenn	`l.addi r1,r1,-120`
99			`l.sw 0x1c(r1),r9`
100			`l.sw 0x20(r1),r10`
101			`l.movhi r9,hi(store_regs)`
102			`l.ori r9,r9,lo(store_regs)`
103	346	jeremybenn	`l.movhi r10,hi(excpt_tick)`
104			`l.ori r10,r10,lo(excpt_tick)`
105	90	jeremybenn	`l.jr r9`
106			`l.nop`
107	346	jeremybenn	`lpint_vector_end:`
108	90	jeremybenn
109	346	jeremybenn	`align_vector:`
110	90	jeremybenn	`l.addi r1,r1,-120`
111			`l.sw 0x1c(r1),r9`
112			`l.sw 0x20(r1),r10`
113			`l.movhi r9,hi(store_regs)`
114			`l.ori r9,r9,lo(store_regs)`
115	346	jeremybenn	`l.movhi r10,hi(excpt_align)`
116			`l.ori r10,r10,lo(excpt_align)`
117	90	jeremybenn	`l.jr r9`
118			`l.nop`
119	346	jeremybenn	`align_vector_end:`
120	90	jeremybenn
121	346	jeremybenn	`illinsn_vector:`
122	90	jeremybenn	`l.addi r1,r1,-120`
123			`l.sw 0x1c(r1),r9`
124			`l.sw 0x20(r1),r10`
125			`l.movhi r9,hi(store_regs)`
126			`l.ori r9,r9,lo(store_regs)`
127	346	jeremybenn	`l.movhi r10,hi(excpt_illinsn)`
128			`l.ori r10,r10,lo(excpt_illinsn)`
129	90	jeremybenn	`l.jr r9`
130			`l.nop`
131	346	jeremybenn	`illinsn_vector_end:`
132	90	jeremybenn
133	346	jeremybenn	`hpint_vector:`
134	90	jeremybenn	`l.addi r1,r1,-120`
135			`l.sw 0x1c(r1),r9`
136			`l.sw 0x20(r1),r10`
137			`l.movhi r9,hi(store_regs)`
138			`l.ori r9,r9,lo(store_regs)`
139	346	jeremybenn	`l.movhi r10,hi(excpt_int)`
140			`l.ori r10,r10,lo(excpt_int)`
141	90	jeremybenn	`l.jr r9`
142			`l.nop`
143	346	jeremybenn	`hpint_vector_end:`
144	90	jeremybenn
145	346	jeremybenn	`dtlbmiss_vector:`
146	90	jeremybenn	`l.addi r1,r1,-120`
147			`l.sw 0x1c(r1),r9`
148			`l.sw 0x20(r1),r10`
149			`l.movhi r9,hi(store_regs)`
150			`l.ori r9,r9,lo(store_regs)`
151	346	jeremybenn	`l.movhi r10,hi(excpt_dtlbmiss)`
152			`l.ori r10,r10,lo(excpt_dtlbmiss)`
153	90	jeremybenn	`l.jr r9`
154			`l.nop`
155	346	jeremybenn	`dtlbmiss_vector_end:`
156	90	jeremybenn
157	346	jeremybenn	`itlbmiss_vector:`
158	90	jeremybenn	`l.addi r1,r1,-120`
159			`l.sw 0x1c(r1),r9`
160			`l.sw 0x20(r1),r10`
161			`l.movhi r9,hi(store_regs)`
162			`l.ori r9,r9,lo(store_regs)`
163	346	jeremybenn	`l.movhi r10,hi(excpt_itlbmiss)`
164			`l.ori r10,r10,lo(excpt_itlbmiss)`
165	90	jeremybenn	`l.jr r9`
166			`l.nop`
167	346	jeremybenn	`itlbmiss_vector_end:`
168	90	jeremybenn
169	346	jeremybenn	`range_vector:`
170	90	jeremybenn	`l.addi r1,r1,-120`
171			`l.sw 0x1c(r1),r9`
172			`l.sw 0x20(r1),r10`
173			`l.movhi r9,hi(store_regs)`
174			`l.ori r9,r9,lo(store_regs)`
175	346	jeremybenn	`l.movhi r10,hi(excpt_range)`
176			`l.ori r10,r10,lo(excpt_range)`
177	90	jeremybenn	`l.jr r9`
178			`l.nop`
179	346	jeremybenn	`range_vector_end:`
180	90	jeremybenn
181	346	jeremybenn	`syscall_vector:`
182	90	jeremybenn	`l.addi r1,r1,-120`
183			`l.sw 0x1c(r1),r9`
184			`l.sw 0x20(r1),r10`
185			`l.movhi r9,hi(store_regs)`
186			`l.ori r9,r9,lo(store_regs)`
187	346	jeremybenn	`l.movhi r10,hi(excpt_syscall)`
188			`l.ori r10,r10,lo(excpt_syscall)`
189	90	jeremybenn	`l.jr r9`
190			`l.nop`
191	346	jeremybenn	`syscall_vector_end:`
192	90	jeremybenn
193	346	jeremybenn	`break_vector:`
194	90	jeremybenn	`l.addi r1,r1,-120`
195			`l.sw 0x1c(r1),r9`
196			`l.sw 0x20(r1),r10`
197			`l.movhi r9,hi(store_regs)`
198			`l.ori r9,r9,lo(store_regs)`
199	346	jeremybenn	`l.movhi r10,hi(excpt_break)`
200			`l.ori r10,r10,lo(excpt_break)`
201	90	jeremybenn	`l.jr r9`
202			`l.nop`
203	346	jeremybenn	`break_vector_end:`
204	90	jeremybenn
205	346	jeremybenn	`trap_vector:`
206	90	jeremybenn	`l.addi r1,r1,-120`
207			`l.sw 0x1c(r1),r9`
208			`l.sw 0x20(r1),r10`
209			`l.movhi r9,hi(store_regs)`
210			`l.ori r9,r9,lo(store_regs)`
211	346	jeremybenn	`l.movhi r10,hi(excpt_trap)`
212			`l.ori r10,r10,lo(excpt_trap)`
213	90	jeremybenn	`l.jr r9`
214			`l.nop`
215	346	jeremybenn	`trap_vector_end:`
216	90	jeremybenn
217			`/* Our special text section is used to guarantee this code goes first`
218			`when linking. */`
219			`.section .except-text`
220
221			`.org 0x100`
222			`.align 4`
223	346	jeremybenn	`reset_vector:`
224	90	jeremybenn	`l.addi r2,r0,0x0`
225			`l.addi r3,r0,0x0`
226			`l.addi r4,r0,0x0`
227			`l.addi r5,r0,0x0`
228			`l.addi r6,r0,0x0`
229			`l.addi r7,r0,0x0`
230			`l.addi r8,r0,0x0`
231			`l.addi r9,r0,0x0`
232			`l.addi r10,r0,0x0`
233			`l.addi r11,r0,0x0`
234			`l.addi r12,r0,0x0`
235			`l.addi r13,r0,0x0`
236			`l.addi r14,r0,0x0`
237			`l.addi r15,r0,0x0`
238			`l.addi r16,r0,0x0`
239			`l.addi r17,r0,0x0`
240			`l.addi r18,r0,0x0`
241			`l.addi r19,r0,0x0`
242			`l.addi r20,r0,0x0`
243			`l.addi r21,r0,0x0`
244			`l.addi r22,r0,0x0`
245			`l.addi r23,r0,0x0`
246			`l.addi r24,r0,0x0`
247			`l.addi r25,r0,0x0`
248			`l.addi r26,r0,0x0`
249			`l.addi r27,r0,0x0`
250			`l.addi r28,r0,0x0`
251			`l.addi r29,r0,0x0`
252			`l.addi r30,r0,0x0`
253			`l.addi r31,r0,0x0`
254
255			`l.movhi r3,hi(start)`
256			`l.ori r3,r3,lo(start)`
257			`l.jr r3`
258			`l.nop`
259			`.global start`
260			`start:`
261	346	jeremybenn	`l.jal init_mc`
262	90	jeremybenn	`l.nop`
263
264	346	jeremybenn	`l.movhi r1,hi(stack)`
265			`l.ori r1,r1,lo(stack)`
266	90	jeremybenn
267			`/* Setup exception wrappers */`
268			`l.movhi r3,hi(_src_beg)`
269			`l.ori r3,r3,lo(_src_beg)`
270			`l.addi r7,r0,0x100`
271
272			`1: l.addi r7,r7,0x100`
273			`l.sfeqi r7,0xf00`
274			`l.bf 1f`
275			`l.nop`
276			`l.addi r4,r7,0`
277			`l.addi r5,r0,0`
278			`2:`
279			`l.lwz r6,0(r3)`
280			`l.sw 0(r4),r6`
281			`l.addi r3,r3,4`
282			`l.addi r4,r4,4`
283			`l.addi r5,r5,1`
284			`l.sfeqi r5,9`
285			`l.bf 1b`
286			`l.nop`
287			`l.j 2b`
288			`l.nop`
289			`1:`
290			`/* Copy data section */`
291			`l.movhi r4,hi(_dst_beg)`
292			`l.ori r4,r4,lo(_dst_beg)`
293			`l.movhi r5,hi(_dst_end)`
294			`l.ori r5,r5,lo(_dst_end)`
295			`l.sub r5,r5,r4`
296			`l.sfeqi r5,0`
297			`l.bf 2f`
298			`l.nop`
299			`1: l.lwz r6,0(r3)`
300			`l.sw 0(r4),r6`
301			`l.addi r3,r3,4`
302			`l.addi r4,r4,4`
303			`l.addi r5,r5,-4`
304			`l.sfgtsi r5,0`
305			`l.bf 1b`
306			`l.nop`
307
308			`2:`
309
310			`l.movhi r2,hi(reset)`
311			`l.ori r2,r2,lo(reset)`
312			`l.jr r2`
313			`l.nop`
314
315	346	jeremybenn	`init_mc:`
316	90	jeremybenn
317			`l.movhi r3,hi(MC_BASE_ADDR)`
318			`l.ori r3,r3,lo(MC_BASE_ADDR)`
319
320			`l.addi r4,r3,MC_CSC(0)`
321			`l.movhi r5,hi(FLASH_BASE_ADDR)`
322			`l.srai r5,r5,6`
323			`l.ori r5,r5,0x0025`
324			`l.sw 0(r4),r5`
325
326			`l.addi r4,r3,MC_TMS(0)`
327			`l.movhi r5,hi(FLASH_TMS_VAL)`
328			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
329			`l.sw 0(r4),r5`
330
331			`l.addi r4,r3,MC_BA_MASK`
332			`l.addi r5,r0,MC_MASK_VAL`
333			`l.sw 0(r4),r5`
334
335			`l.addi r4,r3,MC_CSR`
336			`l.movhi r5,hi(MC_CSR_VAL)`
337			`l.ori r5,r5,lo(MC_CSR_VAL)`
338			`l.sw 0(r4),r5`
339
340			`l.addi r4,r3,MC_TMS(1)`
341			`l.movhi r5,hi(SDRAM_TMS_VAL)`
342			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
343			`l.sw 0(r4),r5`
344
345			`l.addi r4,r3,MC_CSC(1)`
346			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
347			`l.srai r5,r5,6`
348			`l.ori r5,r5,0x0411`
349			`l.sw 0(r4),r5`
350
351			`l.jr r9`
352			`l.nop`
353
354			`store_regs:`
355			`l.sw 0x00(r1),r2`
356			`l.sw 0x04(r1),r3`
357			`l.sw 0x08(r1),r4`
358			`l.sw 0x0c(r1),r5`
359			`l.sw 0x10(r1),r6`
360			`l.sw 0x14(r1),r7`
361			`l.sw 0x18(r1),r8`
362			`l.sw 0x24(r1),r11`
363			`l.sw 0x28(r1),r12`
364			`l.sw 0x2c(r1),r13`
365			`l.sw 0x30(r1),r14`
366			`l.sw 0x34(r1),r15`
367			`l.sw 0x38(r1),r16`
368			`l.sw 0x3c(r1),r17`
369			`l.sw 0x40(r1),r18`
370			`l.sw 0x44(r1),r19`
371			`l.sw 0x48(r1),r20`
372			`l.sw 0x4c(r1),r21`
373			`l.sw 0x50(r1),r22`
374			`l.sw 0x54(r1),r23`
375			`l.sw 0x58(r1),r24`
376			`l.sw 0x5c(r1),r25`
377			`l.sw 0x60(r1),r26`
378			`l.sw 0x64(r1),r27`
379			`l.sw 0x68(r1),r28`
380			`l.sw 0x6c(r1),r29`
381			`l.sw 0x70(r1),r30`
382			`l.sw 0x74(r1),r31`
383			`l.movhi r9,hi(end_except)`
384			`l.ori r9,r9,lo(end_except)`
385			`l.lwz r10,0(r10)`
386			`l.jr r10`
387			`l.nop`
388
389			`end_except:`
390			`l.lwz r2,0x00(r1)`
391			`l.lwz r3,0x04(r1)`
392			`l.lwz r4,0x08(r1)`
393			`l.lwz r5,0x0c(r1)`
394			`l.lwz r6,0x10(r1)`
395			`l.lwz r7,0x14(r1)`
396			`l.lwz r8,0x18(r1)`
397			`l.lwz r9,0x1c(r1)`
398			`l.lwz r10,0x20(r1)`
399			`l.lwz r11,0x24(r1)`
400			`l.lwz r12,0x28(r1)`
401			`l.lwz r13,0x2c(r1)`
402			`l.lwz r14,0x30(r1)`
403			`l.lwz r15,0x34(r1)`
404			`l.lwz r16,0x38(r1)`
405			`l.lwz r17,0x3c(r1)`
406			`l.lwz r18,0x40(r1)`
407			`l.lwz r19,0x44(r1)`
408			`l.lwz r20,0x48(r1)`
409			`l.lwz r21,0x4c(r1)`
410			`l.lwz r22,0x50(r1)`
411			`l.lwz r23,0x54(r1)`
412			`l.lwz r24,0x58(r1)`
413			`l.lwz r25,0x5c(r1)`
414			`l.lwz r26,0x60(r1)`
415			`l.lwz r27,0x64(r1)`
416			`l.lwz r28,0x68(r1)`
417			`l.lwz r29,0x6c(r1)`
418			`l.lwz r30,0x70(r1)`
419			`l.lwz r31,0x74(r1)`
420			`l.addi r1,r1,120`
421			`l.rfe`
422			`l.nop`

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