URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except/] [except.S] - Blame information for rev 808

Go to most recent revision | Details | Compare with Previous | View Log


/* except.s. Exception handling support for Or1k tests
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
/* Support file for c based tests */
#include "spr-defs.h"
 
#define reset reset
 
#define REDZONE_SIZE 128
#define EXCEPT_STACK_SIZE (116 + REDZONE_SIZE)
 
        .section .stack
        .space 0x1000
stack:
 
        .extern reset_support
        .extern c_reset
        .extern excpt_buserr
        .extern excpt_dpfault
        .extern excpt_ipfault
        .extern excpt_tick
        .extern excpt_align
        .extern excpt_illinsn
        .extern excpt_int
        .extern excpt_dtlbmiss
        .extern excpt_itlbmiss
        .extern excpt_range
        .extern excpt_syscall
        .extern excpt_break
        .extern excpt_trap
 
        .section .except,"ax"
        .org    0x100
reset_vector:
        l.nop
        l.nop
 
        // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
        // and indeed it is not when simulating the or1200 Verilog core.
        l.andi  r0,r0,0x0
 
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
        l.j     start
        l.nop
 
        .org    0x200
buserr_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_buserr)
        l.ori   r10,r10,lo(excpt_buserr)
        l.lwz   r10,0x0(r10)
        l.jr    r10
        l.nop
 
        .org    0x300
dpfault_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_dpfault)
        l.ori   r10,r10,lo(excpt_dpfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x400
ipfault_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_ipfault)
        l.ori   r10,r10,lo(excpt_ipfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x500
lpint_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_tick)
        l.ori   r10,r10,lo(excpt_tick)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x600
align_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_align)
        l.ori   r10,r10,lo(excpt_align)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x700
illinsn_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_illinsn)
        l.ori   r10,r10,lo(excpt_illinsn)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x800
hpint_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_int)
        l.ori   r10,r10,lo(excpt_int)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x900
dtlbmiss_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_dtlbmiss)
        l.ori   r10,r10,lo(excpt_dtlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xa00
itlbmiss_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_itlbmiss)
        l.ori   r10,r10,lo(excpt_itlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xb00
range_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_range)
        l.ori   r10,r10,lo(excpt_range)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xc00
syscall_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_syscall)
        l.ori   r10,r10,lo(excpt_syscall)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xd00
break_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_break)
        l.ori   r10,r10,lo(excpt_break)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xe00
trap_vector:
        l.addi  r1,r1,-EXCEPT_STACK_SIZE
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_trap)
        l.ori   r10,r10,lo(excpt_trap)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .section .text
 
start:  l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
        l.ori   r2,r1, 0
 
        /* Call reset() function, in support library, which calls main() */
        l.movhi r4,hi(reset)
        l.ori   r4,r4,lo(reset)
        l.jr    r4
        l.nop
 
 
store_regs:
        l.sw    0x00(r1),r3
        l.sw    0x04(r1),r4
        l.sw    0x08(r1),r5
        l.sw    0x0c(r1),r6
        l.sw    0x10(r1),r7
        l.sw    0x14(r1),r8
        l.sw    0x1c(r1),r10
        l.sw    0x20(r1),r11
        l.sw    0x24(r1),r12
        l.sw    0x28(r1),r13
        l.sw    0x2c(r1),r14
        l.sw    0x30(r1),r15
        l.sw    0x34(r1),r16
        l.sw    0x38(r1),r17
        l.sw    0x3c(r1),r18
        l.sw    0x40(r1),r19
        l.sw    0x44(r1),r20
        l.sw    0x48(r1),r21
        l.sw    0x4c(r1),r22
        l.sw    0x50(r1),r23
        l.sw    0x54(r1),r24
        l.sw    0x58(r1),r25
        l.sw    0x5c(r1),r26
        l.sw    0x60(r1),r27
        l.sw    0x64(r1),r28
        l.sw    0x68(r1),r29
        l.sw    0x6c(r1),r30
        l.sw    0x70(r1),r31
        l.jr    r9
        l.nop
 
end_except:
        l.lwz   r3,0x00(r1)
        l.lwz   r4,0x04(r1)
        l.lwz   r5,0x08(r1)
        l.lwz   r6,0x0c(r1)
        l.lwz   r7,0x10(r1)
        l.lwz   r8,0x14(r1)
        l.lwz   r9,0x18(r1)
        l.lwz   r10,0x1c(r1)
        l.lwz   r11,0x20(r1)
        l.lwz   r12,0x24(r1)
        l.lwz   r13,0x28(r1)
        l.lwz   r14,0x2c(r1)
        l.lwz   r15,0x30(r1)
        l.lwz   r16,0x34(r1)
        l.lwz   r17,0x38(r1)
        l.lwz   r18,0x3c(r1)
        l.lwz   r19,0x40(r1)
        l.lwz   r20,0x44(r1)
        l.lwz   r21,0x48(r1)
        l.lwz   r22,0x4c(r1)
        l.lwz   r23,0x50(r1)
        l.lwz   r24,0x54(r1)
        l.lwz   r25,0x58(r1)
        l.lwz   r26,0x5c(r1)
        l.lwz   r27,0x60(r1)
        l.lwz   r28,0x64(r1)
        l.lwz   r29,0x68(r1)
        l.lwz   r30,0x6c(r1)
        l.lwz   r31,0x70(r1)
        l.addi  r1,r1,EXCEPT_STACK_SIZE
        l.rfe
        l.nop
 

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except.s. Exception handling support for Or1k tests`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28	458	julius	`/* Support file for c based tests */`
29	90	jeremybenn	`#include "spr-defs.h"`
30
31	346	jeremybenn	`#define reset reset`
32	90	jeremybenn
33	458	julius	`#define REDZONE_SIZE 128`
34			`#define EXCEPT_STACK_SIZE (116 + REDZONE_SIZE)`
35
36	90	jeremybenn	`.section .stack`
37			`.space 0x1000`
38	346	jeremybenn	`stack:`
39	90	jeremybenn
40	346	jeremybenn	`.extern reset_support`
41			`.extern c_reset`
42			`.extern excpt_buserr`
43			`.extern excpt_dpfault`
44			`.extern excpt_ipfault`
45			`.extern excpt_tick`
46			`.extern excpt_align`
47			`.extern excpt_illinsn`
48			`.extern excpt_int`
49			`.extern excpt_dtlbmiss`
50			`.extern excpt_itlbmiss`
51			`.extern excpt_range`
52			`.extern excpt_syscall`
53			`.extern excpt_break`
54			`.extern excpt_trap`
55	90	jeremybenn
56	458	julius	`.section .except,"ax"`
57			`.org 0x100`
58			`reset_vector:`
59			`l.nop`
60			`l.nop`
61	787	jeremybenn
62			`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
63			`// and indeed it is not when simulating the or1200 Verilog core.`
64			`l.andi r0,r0,0x0`
65
66	458	julius	`l.addi r4,r0,0x0`
67			`l.addi r5,r0,0x0`
68			`l.addi r6,r0,0x0`
69			`l.addi r7,r0,0x0`
70			`l.addi r8,r0,0x0`
71			`l.addi r9,r0,0x0`
72			`l.addi r10,r0,0x0`
73			`l.addi r11,r0,0x0`
74			`l.addi r12,r0,0x0`
75			`l.addi r13,r0,0x0`
76			`l.addi r14,r0,0x0`
77			`l.addi r15,r0,0x0`
78			`l.addi r16,r0,0x0`
79			`l.addi r17,r0,0x0`
80			`l.addi r18,r0,0x0`
81			`l.addi r19,r0,0x0`
82			`l.addi r20,r0,0x0`
83			`l.addi r21,r0,0x0`
84			`l.addi r22,r0,0x0`
85			`l.addi r23,r0,0x0`
86			`l.addi r24,r0,0x0`
87			`l.addi r25,r0,0x0`
88			`l.addi r26,r0,0x0`
89			`l.addi r27,r0,0x0`
90			`l.addi r28,r0,0x0`
91			`l.addi r29,r0,0x0`
92			`l.addi r30,r0,0x0`
93			`l.addi r31,r0,0x0`
94			`l.j start`
95			`l.nop`
96
97			`.org 0x200`
98	346	jeremybenn	`buserr_vector:`
99	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
100			`l.sw 0x18(r1),r9`
101			`l.jal store_regs`
102			`l.nop`
103			`l.movhi r9,hi(end_except)`
104			`l.ori r9,r9,lo(end_except)`
105	346	jeremybenn	`l.movhi r10,hi(excpt_buserr)`
106			`l.ori r10,r10,lo(excpt_buserr)`
107	458	julius	`l.lwz r10,0x0(r10)`
108			`l.jr r10`
109	90	jeremybenn	`l.nop`
110
111	458	julius	`.org 0x300`
112	346	jeremybenn	`dpfault_vector:`
113	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
114			`l.sw 0x18(r1),r9`
115			`l.jal store_regs`
116			`l.nop`
117
118			`l.movhi r9,hi(end_except)`
119			`l.ori r9,r9,lo(end_except)`
120	346	jeremybenn	`l.movhi r10,hi(excpt_dpfault)`
121			`l.ori r10,r10,lo(excpt_dpfault)`
122	458	julius	`l.lwz r10,0(r10)`
123			`l.jr r10`
124	90	jeremybenn	`l.nop`
125
126	458	julius	`.org 0x400`
127	346	jeremybenn	`ipfault_vector:`
128	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
129			`l.sw 0x18(r1),r9`
130			`l.jal store_regs`
131			`l.nop`
132			`l.movhi r9,hi(end_except)`
133			`l.ori r9,r9,lo(end_except)`
134	346	jeremybenn	`l.movhi r10,hi(excpt_ipfault)`
135			`l.ori r10,r10,lo(excpt_ipfault)`
136	458	julius	`l.lwz r10,0(r10)`
137			`l.jr r10`
138	90	jeremybenn	`l.nop`
139
140	458	julius	`.org 0x500`
141	346	jeremybenn	`lpint_vector:`
142	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
143			`l.sw 0x18(r1),r9`
144			`l.jal store_regs`
145			`l.nop`
146			`l.movhi r9,hi(end_except)`
147			`l.ori r9,r9,lo(end_except)`
148	346	jeremybenn	`l.movhi r10,hi(excpt_tick)`
149			`l.ori r10,r10,lo(excpt_tick)`
150	458	julius	`l.lwz r10,0(r10)`
151			`l.jr r10`
152	90	jeremybenn	`l.nop`
153
154	458	julius	`.org 0x600`
155	346	jeremybenn	`align_vector:`
156	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
157			`l.sw 0x18(r1),r9`
158			`l.jal store_regs`
159			`l.nop`
160			`l.movhi r9,hi(end_except)`
161			`l.ori r9,r9,lo(end_except)`
162	346	jeremybenn	`l.movhi r10,hi(excpt_align)`
163			`l.ori r10,r10,lo(excpt_align)`
164	458	julius	`l.lwz r10,0(r10)`
165			`l.jr r10`
166	90	jeremybenn	`l.nop`
167
168	458	julius	`.org 0x700`
169	346	jeremybenn	`illinsn_vector:`
170	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
171			`l.sw 0x18(r1),r9`
172			`l.jal store_regs`
173			`l.nop`
174			`l.movhi r9,hi(end_except)`
175			`l.ori r9,r9,lo(end_except)`
176	346	jeremybenn	`l.movhi r10,hi(excpt_illinsn)`
177			`l.ori r10,r10,lo(excpt_illinsn)`
178	458	julius	`l.lwz r10,0(r10)`
179			`l.jr r10`
180	90	jeremybenn	`l.nop`
181
182	458	julius	`.org 0x800`
183	346	jeremybenn	`hpint_vector:`
184	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
185			`l.sw 0x18(r1),r9`
186			`l.jal store_regs`
187			`l.nop`
188			`l.movhi r9,hi(end_except)`
189			`l.ori r9,r9,lo(end_except)`
190	346	jeremybenn	`l.movhi r10,hi(excpt_int)`
191			`l.ori r10,r10,lo(excpt_int)`
192	458	julius	`l.lwz r10,0(r10)`
193			`l.jr r10`
194	90	jeremybenn	`l.nop`
195
196	458	julius	`.org 0x900`
197	346	jeremybenn	`dtlbmiss_vector:`
198	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
199			`l.sw 0x18(r1),r9`
200			`l.jal store_regs`
201			`l.nop`
202
203			`l.movhi r9,hi(end_except)`
204			`l.ori r9,r9,lo(end_except)`
205	346	jeremybenn	`l.movhi r10,hi(excpt_dtlbmiss)`
206			`l.ori r10,r10,lo(excpt_dtlbmiss)`
207	458	julius	`l.lwz r10,0(r10)`
208			`l.jr r10`
209	90	jeremybenn	`l.nop`
210
211	458	julius	`.org 0xa00`
212	346	jeremybenn	`itlbmiss_vector:`
213	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
214			`l.sw 0x18(r1),r9`
215			`l.jal store_regs`
216			`l.nop`
217			`l.movhi r9,hi(end_except)`
218			`l.ori r9,r9,lo(end_except)`
219	346	jeremybenn	`l.movhi r10,hi(excpt_itlbmiss)`
220			`l.ori r10,r10,lo(excpt_itlbmiss)`
221	458	julius	`l.lwz r10,0(r10)`
222			`l.jr r10`
223	90	jeremybenn	`l.nop`
224
225	458	julius	`.org 0xb00`
226	346	jeremybenn	`range_vector:`
227	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
228			`l.sw 0x18(r1),r9`
229			`l.jal store_regs`
230			`l.nop`
231			`l.movhi r9,hi(end_except)`
232			`l.ori r9,r9,lo(end_except)`
233	346	jeremybenn	`l.movhi r10,hi(excpt_range)`
234			`l.ori r10,r10,lo(excpt_range)`
235	458	julius	`l.lwz r10,0(r10)`
236			`l.jr r10`
237	90	jeremybenn	`l.nop`
238
239	458	julius	`.org 0xc00`
240	346	jeremybenn	`syscall_vector:`
241	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
242			`l.sw 0x18(r1),r9`
243			`l.jal store_regs`
244			`l.nop`
245			`l.movhi r9,hi(end_except)`
246			`l.ori r9,r9,lo(end_except)`
247	346	jeremybenn	`l.movhi r10,hi(excpt_syscall)`
248			`l.ori r10,r10,lo(excpt_syscall)`
249	458	julius	`l.lwz r10,0(r10)`
250			`l.jr r10`
251	90	jeremybenn	`l.nop`
252
253	458	julius	`.org 0xd00`
254	346	jeremybenn	`break_vector:`
255	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
256			`l.sw 0x18(r1),r9`
257			`l.jal store_regs`
258			`l.nop`
259			`l.movhi r9,hi(end_except)`
260			`l.ori r9,r9,lo(end_except)`
261	346	jeremybenn	`l.movhi r10,hi(excpt_break)`
262			`l.ori r10,r10,lo(excpt_break)`
263	458	julius	`l.lwz r10,0(r10)`
264			`l.jr r10`
265	90	jeremybenn	`l.nop`
266
267	458	julius	`.org 0xe00`
268	346	jeremybenn	`trap_vector:`
269	458	julius	`l.addi r1,r1,-EXCEPT_STACK_SIZE`
270			`l.sw 0x18(r1),r9`
271			`l.jal store_regs`
272			`l.nop`
273			`l.movhi r9,hi(end_except)`
274			`l.ori r9,r9,lo(end_except)`
275	346	jeremybenn	`l.movhi r10,hi(excpt_trap)`
276			`l.ori r10,r10,lo(excpt_trap)`
277	458	julius	`l.lwz r10,0(r10)`
278			`l.jr r10`
279	90	jeremybenn	`l.nop`
280
281	458	julius	`.section .text`
282
283			`start: l.movhi r1,hi(stack)`
284	346	jeremybenn	`l.ori r1,r1,lo(stack)`
285	458	julius	`l.ori r2,r1, 0`
286	90	jeremybenn
287	458	julius	`/* Call reset() function, in support library, which calls main() */`
288			`l.movhi r4,hi(reset)`
289			`l.ori r4,r4,lo(reset)`
290			`l.jr r4`
291	90	jeremybenn	`l.nop`
292
293	458	julius
294			`store_regs:`
295			`l.sw 0x00(r1),r3`
296			`l.sw 0x04(r1),r4`
297			`l.sw 0x08(r1),r5`
298			`l.sw 0x0c(r1),r6`
299			`l.sw 0x10(r1),r7`
300			`l.sw 0x14(r1),r8`
301			`l.sw 0x1c(r1),r10`
302			`l.sw 0x20(r1),r11`
303			`l.sw 0x24(r1),r12`
304			`l.sw 0x28(r1),r13`
305			`l.sw 0x2c(r1),r14`
306			`l.sw 0x30(r1),r15`
307			`l.sw 0x34(r1),r16`
308			`l.sw 0x38(r1),r17`
309			`l.sw 0x3c(r1),r18`
310			`l.sw 0x40(r1),r19`
311			`l.sw 0x44(r1),r20`
312			`l.sw 0x48(r1),r21`
313			`l.sw 0x4c(r1),r22`
314			`l.sw 0x50(r1),r23`
315			`l.sw 0x54(r1),r24`
316			`l.sw 0x58(r1),r25`
317			`l.sw 0x5c(r1),r26`
318			`l.sw 0x60(r1),r27`
319			`l.sw 0x64(r1),r28`
320			`l.sw 0x68(r1),r29`
321			`l.sw 0x6c(r1),r30`
322			`l.sw 0x70(r1),r31`
323	90	jeremybenn	`l.jr r9`
324			`l.nop`
325
326			`end_except:`
327	458	julius	`l.lwz r3,0x00(r1)`
328			`l.lwz r4,0x04(r1)`
329			`l.lwz r5,0x08(r1)`
330			`l.lwz r6,0x0c(r1)`
331			`l.lwz r7,0x10(r1)`
332			`l.lwz r8,0x14(r1)`
333			`l.lwz r9,0x18(r1)`
334			`l.lwz r10,0x1c(r1)`
335			`l.lwz r11,0x20(r1)`
336			`l.lwz r12,0x24(r1)`
337			`l.lwz r13,0x28(r1)`
338			`l.lwz r14,0x2c(r1)`
339			`l.lwz r15,0x30(r1)`
340			`l.lwz r16,0x34(r1)`
341			`l.lwz r17,0x38(r1)`
342			`l.lwz r18,0x3c(r1)`
343			`l.lwz r19,0x40(r1)`
344			`l.lwz r20,0x44(r1)`
345			`l.lwz r21,0x48(r1)`
346			`l.lwz r22,0x4c(r1)`
347			`l.lwz r23,0x50(r1)`
348			`l.lwz r24,0x54(r1)`
349			`l.lwz r25,0x58(r1)`
350			`l.lwz r26,0x5c(r1)`
351			`l.lwz r27,0x60(r1)`
352			`l.lwz r28,0x64(r1)`
353			`l.lwz r29,0x68(r1)`
354			`l.lwz r30,0x6c(r1)`
355			`l.lwz r31,0x70(r1)`
356			`l.addi r1,r1,EXCEPT_STACK_SIZE`
357	90	jeremybenn	`l.rfe`
358			`l.nop`
359	458	julius

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except/] [except.S] - Blame information for rev 808