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/* except-test-s.S. Machine code support for test of Or1ksim exception handling
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
#include "spr-defs.h"
#include "board.h"
 
#define reset main
 
        .global except_basic
        .global lo_dmmu_en
        .global lo_immu_en
        .global call
        .global call_with_int
        .global load_acc_32
        .global load_acc_16
        .global store_acc_32
        .global store_acc_16
        .global load_b_acc_32
        .global trap
        .global b_trap
        .global range
        .global b_range
        .global int_trigger
        .global int_loop
        .global jump_back
 
        .section .stack
        .space 0x1000
stack:
 
        .extern reset_support
        .extern c_reset
        .extern excpt_buserr
        .extern excpt_dpfault
        .extern excpt_ipfault
        .extern excpt_tick
        .extern excpt_align
        .extern excpt_illinsn
        .extern excpt_int
        .extern excpt_dtlbmiss
        .extern excpt_itlbmiss
        .extern excpt_range
        .extern excpt_syscall
        .extern excpt_break
        .extern excpt_trap
 
        /* Our special text section is used to guarantee this code goes first
           when linking. */
 
        .section .except,"ax"
 
        .org    0x100
reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
 
 
        .org 0x200
buserr_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_buserr)
        l.ori   r10,r10,lo(excpt_buserr)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x300
dpfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_dpfault)
        l.ori   r10,r10,lo(excpt_dpfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x400
ipfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_ipfault)
        l.ori   r10,r10,lo(excpt_ipfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x500
tick_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_tick)
        l.ori   r10,r10,lo(excpt_tick)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x600
align_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_align)
        l.ori   r10,r10,lo(excpt_align)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x700
illinsn_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_illinsn)
        l.ori   r10,r10,lo(excpt_illinsn)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x800
int_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_int)
        l.ori   r10,r10,lo(excpt_int)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x900
dtlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_dtlbmiss)
        l.ori   r10,r10,lo(excpt_dtlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xa00
itlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_itlbmiss)
        l.ori   r10,r10,lo(excpt_itlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xb00
range_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_range)
        l.ori   r10,r10,lo(excpt_range)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xc00
syscall_vector:
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(sys1)
        l.ori r5,r5,lo(sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(sys2)
        l.ori r4,r4,lo(sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
        .org 0xd00
break_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_break)
        l.ori   r10,r10,lo(excpt_break)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xe00
trap_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_trap)
        l.ori   r10,r10,lo(excpt_trap)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
 
        .section .text
 
start:
 
        l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
        l.ori   r2,r1,0
 
bss_clear:
        /* Clear BSS */
        l.movhi r3, hi(_bstart)
        l.ori   r3, r3, lo(_bstart)
        l.movhi r4, hi(_bend)
        l.ori   r4, r4, lo(_bend)
bss_clear_loop:
        l.sw    0(r3),  r0
        l.sfgtu r3, r4
        l.bnf   bss_clear_loop
        l.addi  r3, r3, 4
 
 
        l.movhi r3,hi(reset)
        l.ori   r3,r3,lo(reset)
        l.jr    r3
        l.nop
 
store_regs:
        l.sw    0x00(r1),r2
        l.sw    0x04(r1),r3
        l.sw    0x08(r1),r4
        l.sw    0x0c(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(except_pc)
        l.ori   r4,r4,lo(except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(except_ea)
        l.ori   r4,r4,lo(except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
 
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
end_except:
        l.lwz   r2,0x00(r1)
        l.lwz   r3,0x04(r1)
        l.lwz   r4,0x08(r1)
        l.lwz   r5,0x0c(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.addi  r1,r1,120
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
except_basic:
sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
b_trap:
        l.jr    r9
trap:
        l.trap  15
        l.jr    r9
        l.nop
 
b_range:
        l.jr    r9
range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
int_loop:
        l.j     int_loop
        l.lwz   r5,0(r4);
 
jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except-test-s.S. Machine code support for test of Or1ksim exception handling`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`#include "spr-defs.h"`
29			`#include "board.h"`
30
31	346	jeremybenn	`#define reset main`
32	90	jeremybenn
33	346	jeremybenn	`.global except_basic`
34			`.global lo_dmmu_en`
35			`.global lo_immu_en`
36			`.global call`
37			`.global call_with_int`
38			`.global load_acc_32`
39			`.global load_acc_16`
40			`.global store_acc_32`
41			`.global store_acc_16`
42			`.global load_b_acc_32`
43			`.global trap`
44			`.global b_trap`
45			`.global range`
46			`.global b_range`
47			`.global int_trigger`
48			`.global int_loop`
49			`.global jump_back`
50	90	jeremybenn
51			`.section .stack`
52			`.space 0x1000`
53	346	jeremybenn	`stack:`
54	90	jeremybenn
55	346	jeremybenn	`.extern reset_support`
56			`.extern c_reset`
57			`.extern excpt_buserr`
58			`.extern excpt_dpfault`
59			`.extern excpt_ipfault`
60			`.extern excpt_tick`
61			`.extern excpt_align`
62			`.extern excpt_illinsn`
63			`.extern excpt_int`
64			`.extern excpt_dtlbmiss`
65			`.extern excpt_itlbmiss`
66			`.extern excpt_range`
67			`.extern excpt_syscall`
68			`.extern excpt_break`
69			`.extern excpt_trap`
70	90	jeremybenn
71	458	julius	`/* Our special text section is used to guarantee this code goes first`
72			`when linking. */`
73	90	jeremybenn
74	458	julius	`.section .except,"ax"`
75
76			`.org 0x100`
77			`reset_vector:`
78			`l.nop`
79			`l.nop`
80			`l.addi r2,r0,0x0`
81			`l.addi r3,r0,0x0`
82			`l.addi r4,r0,0x0`
83			`l.addi r5,r0,0x0`
84			`l.addi r6,r0,0x0`
85			`l.addi r7,r0,0x0`
86			`l.addi r8,r0,0x0`
87			`l.addi r9,r0,0x0`
88			`l.addi r10,r0,0x0`
89			`l.addi r11,r0,0x0`
90			`l.addi r12,r0,0x0`
91			`l.addi r13,r0,0x0`
92			`l.addi r14,r0,0x0`
93			`l.addi r15,r0,0x0`
94			`l.addi r16,r0,0x0`
95			`l.addi r17,r0,0x0`
96			`l.addi r18,r0,0x0`
97			`l.addi r19,r0,0x0`
98			`l.addi r20,r0,0x0`
99			`l.addi r21,r0,0x0`
100			`l.addi r22,r0,0x0`
101			`l.addi r23,r0,0x0`
102			`l.addi r24,r0,0x0`
103			`l.addi r25,r0,0x0`
104			`l.addi r26,r0,0x0`
105			`l.addi r27,r0,0x0`
106			`l.addi r28,r0,0x0`
107			`l.addi r29,r0,0x0`
108			`l.addi r30,r0,0x0`
109			`l.addi r31,r0,0x0`
110
111			`l.movhi r3,hi(start)`
112			`l.ori r3,r3,lo(start)`
113			`l.jr r3`
114			`l.nop`
115
116
117			`.org 0x200`
118	346	jeremybenn	`buserr_vector:`
119	90	jeremybenn	`l.addi r1,r1,-120`
120			`l.sw 0x1c(r1),r9`
121			`l.sw 0x20(r1),r10`
122			`l.movhi r9,hi(store_regs)`
123			`l.ori r9,r9,lo(store_regs)`
124	346	jeremybenn	`l.movhi r10,hi(excpt_buserr)`
125			`l.ori r10,r10,lo(excpt_buserr)`
126	90	jeremybenn	`l.jr r9`
127			`l.nop`
128			`l.nop`
129			`l.nop`
130			`l.nop`
131			`l.nop`
132			`l.nop`
133			`l.nop`
134			`l.nop`
135	458	julius
136			`.org 0x300`
137	346	jeremybenn	`dpfault_vector:`
138	90	jeremybenn	`l.addi r1,r1,-120`
139			`l.sw 0x1c(r1),r9`
140			`l.sw 0x20(r1),r10`
141			`l.movhi r9,hi(store_regs)`
142			`l.ori r9,r9,lo(store_regs)`
143	346	jeremybenn	`l.movhi r10,hi(excpt_dpfault)`
144			`l.ori r10,r10,lo(excpt_dpfault)`
145	90	jeremybenn	`l.jr r9`
146			`l.nop`
147			`l.nop`
148			`l.nop`
149			`l.nop`
150			`l.nop`
151			`l.nop`
152			`l.nop`
153			`l.nop`
154
155	458	julius	`.org 0x400`
156	346	jeremybenn	`ipfault_vector:`
157	90	jeremybenn	`l.addi r1,r1,-120`
158			`l.sw 0x1c(r1),r9`
159			`l.sw 0x20(r1),r10`
160			`l.movhi r9,hi(store_regs)`
161			`l.ori r9,r9,lo(store_regs)`
162	346	jeremybenn	`l.movhi r10,hi(excpt_ipfault)`
163			`l.ori r10,r10,lo(excpt_ipfault)`
164	90	jeremybenn	`l.jr r9`
165			`l.nop`
166			`l.nop`
167			`l.nop`
168			`l.nop`
169			`l.nop`
170			`l.nop`
171			`l.nop`
172			`l.nop`
173
174	458	julius	`.org 0x500`
175	346	jeremybenn	`tick_vector:`
176	90	jeremybenn	`l.addi r1,r1,-120`
177			`l.sw 0x1c(r1),r9`
178			`l.sw 0x20(r1),r10`
179			`l.movhi r9,hi(store_regs)`
180			`l.ori r9,r9,lo(store_regs)`
181	346	jeremybenn	`l.movhi r10,hi(excpt_tick)`
182			`l.ori r10,r10,lo(excpt_tick)`
183	90	jeremybenn	`l.jr r9`
184			`l.nop`
185			`l.nop`
186			`l.nop`
187			`l.nop`
188			`l.nop`
189			`l.nop`
190			`l.nop`
191			`l.nop`
192
193	458	julius	`.org 0x600`
194	346	jeremybenn	`align_vector:`
195	90	jeremybenn	`l.addi r1,r1,-120`
196			`l.sw 0x1c(r1),r9`
197			`l.sw 0x20(r1),r10`
198			`l.movhi r9,hi(store_regs)`
199			`l.ori r9,r9,lo(store_regs)`
200	346	jeremybenn	`l.movhi r10,hi(excpt_align)`
201			`l.ori r10,r10,lo(excpt_align)`
202	90	jeremybenn	`l.jr r9`
203			`l.nop`
204			`l.nop`
205			`l.nop`
206			`l.nop`
207			`l.nop`
208			`l.nop`
209			`l.nop`
210			`l.nop`
211
212	458	julius	`.org 0x700`
213	346	jeremybenn	`illinsn_vector:`
214	90	jeremybenn	`l.addi r1,r1,-120`
215			`l.sw 0x1c(r1),r9`
216			`l.sw 0x20(r1),r10`
217			`l.movhi r9,hi(store_regs)`
218			`l.ori r9,r9,lo(store_regs)`
219	346	jeremybenn	`l.movhi r10,hi(excpt_illinsn)`
220			`l.ori r10,r10,lo(excpt_illinsn)`
221	90	jeremybenn	`l.jr r9`
222			`l.nop`
223			`l.nop`
224			`l.nop`
225			`l.nop`
226			`l.nop`
227			`l.nop`
228			`l.nop`
229			`l.nop`
230
231	458	julius	`.org 0x800`
232	346	jeremybenn	`int_vector:`
233	90	jeremybenn	`l.addi r1,r1,-120`
234			`l.sw 0x1c(r1),r9`
235			`l.sw 0x20(r1),r10`
236			`l.movhi r9,hi(store_regs)`
237			`l.ori r9,r9,lo(store_regs)`
238	346	jeremybenn	`l.movhi r10,hi(excpt_int)`
239			`l.ori r10,r10,lo(excpt_int)`
240	90	jeremybenn	`l.jr r9`
241			`l.nop`
242			`l.nop`
243			`l.nop`
244			`l.nop`
245			`l.nop`
246			`l.nop`
247			`l.nop`
248			`l.nop`
249
250	458	julius	`.org 0x900`
251	346	jeremybenn	`dtlbmiss_vector:`
252	90	jeremybenn	`l.addi r1,r1,-120`
253			`l.sw 0x1c(r1),r9`
254			`l.sw 0x20(r1),r10`
255			`l.movhi r9,hi(store_regs)`
256			`l.ori r9,r9,lo(store_regs)`
257	346	jeremybenn	`l.movhi r10,hi(excpt_dtlbmiss)`
258			`l.ori r10,r10,lo(excpt_dtlbmiss)`
259	90	jeremybenn	`l.jr r9`
260			`l.nop`
261			`l.nop`
262			`l.nop`
263			`l.nop`
264			`l.nop`
265			`l.nop`
266			`l.nop`
267			`l.nop`
268
269	458	julius	`.org 0xa00`
270	346	jeremybenn	`itlbmiss_vector:`
271	90	jeremybenn	`l.addi r1,r1,-120`
272			`l.sw 0x1c(r1),r9`
273			`l.sw 0x20(r1),r10`
274			`l.movhi r9,hi(store_regs)`
275			`l.ori r9,r9,lo(store_regs)`
276	346	jeremybenn	`l.movhi r10,hi(excpt_itlbmiss)`
277			`l.ori r10,r10,lo(excpt_itlbmiss)`
278	90	jeremybenn	`l.jr r9`
279			`l.nop`
280			`l.nop`
281			`l.nop`
282			`l.nop`
283			`l.nop`
284			`l.nop`
285			`l.nop`
286			`l.nop`
287
288	458	julius	`.org 0xb00`
289	346	jeremybenn	`range_vector:`
290	90	jeremybenn	`l.addi r1,r1,-120`
291			`l.sw 0x1c(r1),r9`
292			`l.sw 0x20(r1),r10`
293			`l.movhi r9,hi(store_regs)`
294			`l.ori r9,r9,lo(store_regs)`
295	346	jeremybenn	`l.movhi r10,hi(excpt_range)`
296			`l.ori r10,r10,lo(excpt_range)`
297	90	jeremybenn	`l.jr r9`
298			`l.nop`
299			`l.nop`
300			`l.nop`
301			`l.nop`
302			`l.nop`
303			`l.nop`
304			`l.nop`
305			`l.nop`
306
307	458	julius	`.org 0xc00`
308	346	jeremybenn	`syscall_vector:`
309	90	jeremybenn	`l.addi r3,r3,4`
310
311			`l.mfspr r4,r0,SPR_SR`
312			`l.andi r4,r4,7`
313			`l.add r6,r0,r4`
314
315			`l.mfspr r4,r0,SPR_EPCR_BASE`
316	346	jeremybenn	`l.movhi r5,hi(sys1)`
317			`l.ori r5,r5,lo(sys1)`
318	90	jeremybenn	`l.sub r5,r4,r5`
319
320			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
321			`l.ori r4,r4,SPR_SR_SM`
322			`l.mtspr r0,r4,SPR_ESR_BASE`
323
324	346	jeremybenn	`l.movhi r4,hi(sys2)`
325			`l.ori r4,r4,lo(sys2)`
326	90	jeremybenn	`l.mtspr r0,r4,SPR_EPCR_BASE`
327
328			`l.rfe`
329			`l.addi r3,r3,8`
330
331	458	julius	`.org 0xd00`
332	346	jeremybenn	`break_vector:`
333	90	jeremybenn	`l.addi r1,r1,-120`
334			`l.sw 0x1c(r1),r9`
335			`l.sw 0x20(r1),r10`
336			`l.movhi r9,hi(store_regs)`
337			`l.ori r9,r9,lo(store_regs)`
338	346	jeremybenn	`l.movhi r10,hi(excpt_break)`
339			`l.ori r10,r10,lo(excpt_break)`
340	90	jeremybenn	`l.jr r9`
341			`l.nop`
342			`l.nop`
343			`l.nop`
344			`l.nop`
345			`l.nop`
346			`l.nop`
347			`l.nop`
348			`l.nop`
349
350	458	julius	`.org 0xe00`
351	346	jeremybenn	`trap_vector:`
352	90	jeremybenn	`l.addi r1,r1,-120`
353			`l.sw 0x1c(r1),r9`
354			`l.sw 0x20(r1),r10`
355			`l.movhi r9,hi(store_regs)`
356			`l.ori r9,r9,lo(store_regs)`
357	346	jeremybenn	`l.movhi r10,hi(excpt_trap)`
358			`l.ori r10,r10,lo(excpt_trap)`
359	90	jeremybenn	`l.jr r9`
360			`l.nop`
361			`l.nop`
362			`l.nop`
363			`l.nop`
364			`l.nop`
365			`l.nop`
366			`l.nop`
367			`l.nop`
368	458	julius
369	90	jeremybenn
370	458	julius	`.section .text`
371
372	90	jeremybenn	`start:`
373
374	346	jeremybenn	`l.movhi r1,hi(stack)`
375			`l.ori r1,r1,lo(stack)`
376	458	julius	`l.ori r2,r1,0`
377	90	jeremybenn
378	458	julius	`bss_clear:`
379			`/* Clear BSS */`
380			`l.movhi r3, hi(_bstart)`
381			`l.ori r3, r3, lo(_bstart)`
382			`l.movhi r4, hi(_bend)`
383			`l.ori r4, r4, lo(_bend)`
384			`bss_clear_loop:`
385			`l.sw 0(r3), r0`
386			`l.sfgtu r3, r4`
387			`l.bnf bss_clear_loop`
388			`l.addi r3, r3, 4`
389
390
391			`l.movhi r3,hi(reset)`
392			`l.ori r3,r3,lo(reset)`
393			`l.jr r3`
394	90	jeremybenn	`l.nop`
395
396			`store_regs:`
397			`l.sw 0x00(r1),r2`
398			`l.sw 0x04(r1),r3`
399			`l.sw 0x08(r1),r4`
400			`l.sw 0x0c(r1),r5`
401			`l.sw 0x10(r1),r6`
402			`l.sw 0x14(r1),r7`
403			`l.sw 0x18(r1),r8`
404			`l.sw 0x24(r1),r11`
405			`l.sw 0x28(r1),r12`
406			`l.sw 0x2c(r1),r13`
407			`l.sw 0x30(r1),r14`
408			`l.sw 0x34(r1),r15`
409			`l.sw 0x38(r1),r16`
410			`l.sw 0x3c(r1),r17`
411			`l.sw 0x40(r1),r18`
412			`l.sw 0x44(r1),r19`
413			`l.sw 0x48(r1),r20`
414			`l.sw 0x4c(r1),r21`
415			`l.sw 0x50(r1),r22`
416			`l.sw 0x54(r1),r23`
417			`l.sw 0x58(r1),r24`
418			`l.sw 0x5c(r1),r25`
419			`l.sw 0x60(r1),r26`
420			`l.sw 0x64(r1),r27`
421			`l.sw 0x68(r1),r28`
422			`l.sw 0x6c(r1),r29`
423			`l.sw 0x70(r1),r30`
424			`l.sw 0x74(r1),r31`
425
426			`l.mfspr r3,r0,SPR_EPCR_BASE`
427	346	jeremybenn	`l.movhi r4,hi(except_pc)`
428			`l.ori r4,r4,lo(except_pc)`
429	90	jeremybenn	`l.sw 0(r4),r3`
430
431			`l.mfspr r3,r0,SPR_EEAR_BASE`
432	346	jeremybenn	`l.movhi r4,hi(except_ea)`
433			`l.ori r4,r4,lo(except_ea)`
434	90	jeremybenn	`l.sw 0(r4),r3`
435
436			`l.movhi r9,hi(end_except)`
437			`l.ori r9,r9,lo(end_except)`
438
439			`l.lwz r10,0(r10)`
440			`l.jr r10`
441			`l.nop`
442
443			`end_except:`
444			`l.lwz r2,0x00(r1)`
445			`l.lwz r3,0x04(r1)`
446			`l.lwz r4,0x08(r1)`
447			`l.lwz r5,0x0c(r1)`
448			`l.lwz r6,0x10(r1)`
449			`l.lwz r7,0x14(r1)`
450			`l.lwz r8,0x18(r1)`
451			`l.lwz r9,0x1c(r1)`
452			`l.lwz r10,0x20(r1)`
453			`l.lwz r11,0x24(r1)`
454			`l.lwz r12,0x28(r1)`
455			`l.lwz r13,0x2c(r1)`
456			`l.lwz r14,0x30(r1)`
457			`l.lwz r15,0x34(r1)`
458			`l.lwz r16,0x38(r1)`
459			`l.lwz r17,0x3c(r1)`
460			`l.lwz r18,0x40(r1)`
461			`l.lwz r19,0x44(r1)`
462			`l.lwz r20,0x48(r1)`
463			`l.lwz r21,0x4c(r1)`
464			`l.lwz r22,0x50(r1)`
465			`l.lwz r23,0x54(r1)`
466			`l.lwz r24,0x58(r1)`
467			`l.lwz r25,0x5c(r1)`
468			`l.lwz r26,0x60(r1)`
469			`l.lwz r27,0x64(r1)`
470			`l.lwz r28,0x68(r1)`
471			`l.lwz r29,0x6c(r1)`
472			`l.lwz r30,0x70(r1)`
473			`l.lwz r31,0x74(r1)`
474			`l.addi r1,r1,120`
475			`l.mtspr r0,r9,SPR_EPCR_BASE`
476			`l.rfe`
477			`l.nop`
478
479	346	jeremybenn	`except_basic:`
480			`sys1:`
481	90	jeremybenn	`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
482			`l.mfspr r4,r0,SPR_SR`
483			`l.and r4,r4,r3`
484			`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
485			`l.mtspr r0,r4,SPR_SR`
486
487			`l.addi r3,r0,0`
488			`l.sys 1`
489			`l.addi r3,r3,2`
490
491	346	jeremybenn	`sys2:`
492	90	jeremybenn	`l.addi r11,r0,0`
493
494			`l.mfspr r4,r0,SPR_SR /* Check SR */`
495			`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
496			`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
497			`l.bf 1f`
498			`l.nop`
499			`l.addi r11,r11,1`
500			`1:`

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