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/* except-test-s.S. Machine code support for test of Or1ksim exception handling
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
#include "spr-defs.h"
#include "board.h"
 
#define reset main
 
        .global except_basic
        .global lo_dmmu_en
        .global lo_immu_en
        .global call
        .global call_with_int
        .global load_acc_32
        .global load_acc_16
        .global store_acc_32
        .global store_acc_16
        .global load_b_acc_32
        .global trap
        .global b_trap
        .global range
        .global b_range
        .global int_trigger
        .global int_loop
        .global jump_back
 
        .section .stack
        .space 0x1000
stack:
 
        .extern reset_support
        .extern c_reset
        .extern excpt_buserr
        .extern excpt_dpfault
        .extern excpt_ipfault
        .extern excpt_tick
        .extern excpt_align
        .extern excpt_illinsn
        .extern excpt_int
        .extern excpt_dtlbmiss
        .extern excpt_itlbmiss
        .extern excpt_range
        .extern excpt_syscall
        .extern excpt_break
        .extern excpt_trap
 
        /* Our special text section is used to guarantee this code goes first
           when linking. */
 
        .section .except,"ax"
 
        .org    0x100
reset_vector:
        l.nop
        l.nop
 
        // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
        // and indeed it is not when simulating the or1200 Verilog core.
        l.andi  r0,r0,0x0
 
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
 
 
        .org 0x200
buserr_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_buserr)
        l.ori   r10,r10,lo(excpt_buserr)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x300
dpfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_dpfault)
        l.ori   r10,r10,lo(excpt_dpfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x400
ipfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_ipfault)
        l.ori   r10,r10,lo(excpt_ipfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x500
tick_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_tick)
        l.ori   r10,r10,lo(excpt_tick)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x600
align_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_align)
        l.ori   r10,r10,lo(excpt_align)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x700
illinsn_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_illinsn)
        l.ori   r10,r10,lo(excpt_illinsn)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x800
int_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_int)
        l.ori   r10,r10,lo(excpt_int)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0x900
dtlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_dtlbmiss)
        l.ori   r10,r10,lo(excpt_dtlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xa00
itlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_itlbmiss)
        l.ori   r10,r10,lo(excpt_itlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xb00
range_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_range)
        l.ori   r10,r10,lo(excpt_range)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xc00
syscall_vector:
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(sys1)
        l.ori r5,r5,lo(sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(sys2)
        l.ori r4,r4,lo(sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
        .org 0xd00
break_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_break)
        l.ori   r10,r10,lo(excpt_break)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .org 0xe00
trap_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(excpt_trap)
        l.ori   r10,r10,lo(excpt_trap)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
 
        .section .text
 
start:
 
        l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
        l.ori   r2,r1,0
 
bss_clear:
        /* Clear BSS */
        l.movhi r3, hi(_bstart)
        l.ori   r3, r3, lo(_bstart)
        l.movhi r4, hi(_bend)
        l.ori   r4, r4, lo(_bend)
bss_clear_loop:
        l.sw    0(r3),  r0
        l.sfgtu r3, r4
        l.bnf   bss_clear_loop
        l.addi  r3, r3, 4
 
 
        l.movhi r3,hi(reset)
        l.ori   r3,r3,lo(reset)
        l.jr    r3
        l.nop
 
store_regs:
        l.sw    0x00(r1),r2
        l.sw    0x04(r1),r3
        l.sw    0x08(r1),r4
        l.sw    0x0c(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(except_pc)
        l.ori   r4,r4,lo(except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(except_ea)
        l.ori   r4,r4,lo(except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
 
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
end_except:
        l.lwz   r2,0x00(r1)
        l.lwz   r3,0x04(r1)
        l.lwz   r4,0x08(r1)
        l.lwz   r5,0x0c(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.addi  r1,r1,120
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
except_basic:
sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
b_trap:
        l.jr    r9
trap:
        l.trap  15
        l.jr    r9
        l.nop
 
b_range:
        l.jr    r9
range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
int_loop:
        l.j     int_loop
        l.lwz   r5,0(r4);
 
jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except-test-s.S. Machine code support for test of Or1ksim exception handling`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`#include "spr-defs.h"`
29			`#include "board.h"`
30
31	346	jeremybenn	`#define reset main`
32	90	jeremybenn
33	346	jeremybenn	`.global except_basic`
34			`.global lo_dmmu_en`
35			`.global lo_immu_en`
36			`.global call`
37			`.global call_with_int`
38			`.global load_acc_32`
39			`.global load_acc_16`
40			`.global store_acc_32`
41			`.global store_acc_16`
42			`.global load_b_acc_32`
43			`.global trap`
44			`.global b_trap`
45			`.global range`
46			`.global b_range`
47			`.global int_trigger`
48			`.global int_loop`
49			`.global jump_back`
50	90	jeremybenn
51			`.section .stack`
52			`.space 0x1000`
53	346	jeremybenn	`stack:`
54	90	jeremybenn
55	346	jeremybenn	`.extern reset_support`
56			`.extern c_reset`
57			`.extern excpt_buserr`
58			`.extern excpt_dpfault`
59			`.extern excpt_ipfault`
60			`.extern excpt_tick`
61			`.extern excpt_align`
62			`.extern excpt_illinsn`
63			`.extern excpt_int`
64			`.extern excpt_dtlbmiss`
65			`.extern excpt_itlbmiss`
66			`.extern excpt_range`
67			`.extern excpt_syscall`
68			`.extern excpt_break`
69			`.extern excpt_trap`
70	90	jeremybenn
71	458	julius	`/* Our special text section is used to guarantee this code goes first`
72			`when linking. */`
73	90	jeremybenn
74	458	julius	`.section .except,"ax"`
75
76			`.org 0x100`
77			`reset_vector:`
78			`l.nop`
79			`l.nop`
80	787	jeremybenn
81			`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
82			`// and indeed it is not when simulating the or1200 Verilog core.`
83			`l.andi r0,r0,0x0`
84
85	458	julius	`l.addi r2,r0,0x0`
86			`l.addi r3,r0,0x0`
87			`l.addi r4,r0,0x0`
88			`l.addi r5,r0,0x0`
89			`l.addi r6,r0,0x0`
90			`l.addi r7,r0,0x0`
91			`l.addi r8,r0,0x0`
92			`l.addi r9,r0,0x0`
93			`l.addi r10,r0,0x0`
94			`l.addi r11,r0,0x0`
95			`l.addi r12,r0,0x0`
96			`l.addi r13,r0,0x0`
97			`l.addi r14,r0,0x0`
98			`l.addi r15,r0,0x0`
99			`l.addi r16,r0,0x0`
100			`l.addi r17,r0,0x0`
101			`l.addi r18,r0,0x0`
102			`l.addi r19,r0,0x0`
103			`l.addi r20,r0,0x0`
104			`l.addi r21,r0,0x0`
105			`l.addi r22,r0,0x0`
106			`l.addi r23,r0,0x0`
107			`l.addi r24,r0,0x0`
108			`l.addi r25,r0,0x0`
109			`l.addi r26,r0,0x0`
110			`l.addi r27,r0,0x0`
111			`l.addi r28,r0,0x0`
112			`l.addi r29,r0,0x0`
113			`l.addi r30,r0,0x0`
114			`l.addi r31,r0,0x0`
115
116			`l.movhi r3,hi(start)`
117			`l.ori r3,r3,lo(start)`
118			`l.jr r3`
119			`l.nop`
120
121
122			`.org 0x200`
123	346	jeremybenn	`buserr_vector:`
124	90	jeremybenn	`l.addi r1,r1,-120`
125			`l.sw 0x1c(r1),r9`
126			`l.sw 0x20(r1),r10`
127			`l.movhi r9,hi(store_regs)`
128			`l.ori r9,r9,lo(store_regs)`
129	346	jeremybenn	`l.movhi r10,hi(excpt_buserr)`
130			`l.ori r10,r10,lo(excpt_buserr)`
131	90	jeremybenn	`l.jr r9`
132			`l.nop`
133			`l.nop`
134			`l.nop`
135			`l.nop`
136			`l.nop`
137			`l.nop`
138			`l.nop`
139			`l.nop`
140	458	julius
141			`.org 0x300`
142	346	jeremybenn	`dpfault_vector:`
143	90	jeremybenn	`l.addi r1,r1,-120`
144			`l.sw 0x1c(r1),r9`
145			`l.sw 0x20(r1),r10`
146			`l.movhi r9,hi(store_regs)`
147			`l.ori r9,r9,lo(store_regs)`
148	346	jeremybenn	`l.movhi r10,hi(excpt_dpfault)`
149			`l.ori r10,r10,lo(excpt_dpfault)`
150	90	jeremybenn	`l.jr r9`
151			`l.nop`
152			`l.nop`
153			`l.nop`
154			`l.nop`
155			`l.nop`
156			`l.nop`
157			`l.nop`
158			`l.nop`
159
160	458	julius	`.org 0x400`
161	346	jeremybenn	`ipfault_vector:`
162	90	jeremybenn	`l.addi r1,r1,-120`
163			`l.sw 0x1c(r1),r9`
164			`l.sw 0x20(r1),r10`
165			`l.movhi r9,hi(store_regs)`
166			`l.ori r9,r9,lo(store_regs)`
167	346	jeremybenn	`l.movhi r10,hi(excpt_ipfault)`
168			`l.ori r10,r10,lo(excpt_ipfault)`
169	90	jeremybenn	`l.jr r9`
170			`l.nop`
171			`l.nop`
172			`l.nop`
173			`l.nop`
174			`l.nop`
175			`l.nop`
176			`l.nop`
177			`l.nop`
178
179	458	julius	`.org 0x500`
180	346	jeremybenn	`tick_vector:`
181	90	jeremybenn	`l.addi r1,r1,-120`
182			`l.sw 0x1c(r1),r9`
183			`l.sw 0x20(r1),r10`
184			`l.movhi r9,hi(store_regs)`
185			`l.ori r9,r9,lo(store_regs)`
186	346	jeremybenn	`l.movhi r10,hi(excpt_tick)`
187			`l.ori r10,r10,lo(excpt_tick)`
188	90	jeremybenn	`l.jr r9`
189			`l.nop`
190			`l.nop`
191			`l.nop`
192			`l.nop`
193			`l.nop`
194			`l.nop`
195			`l.nop`
196			`l.nop`
197
198	458	julius	`.org 0x600`
199	346	jeremybenn	`align_vector:`
200	90	jeremybenn	`l.addi r1,r1,-120`
201			`l.sw 0x1c(r1),r9`
202			`l.sw 0x20(r1),r10`
203			`l.movhi r9,hi(store_regs)`
204			`l.ori r9,r9,lo(store_regs)`
205	346	jeremybenn	`l.movhi r10,hi(excpt_align)`
206			`l.ori r10,r10,lo(excpt_align)`
207	90	jeremybenn	`l.jr r9`
208			`l.nop`
209			`l.nop`
210			`l.nop`
211			`l.nop`
212			`l.nop`
213			`l.nop`
214			`l.nop`
215			`l.nop`
216
217	458	julius	`.org 0x700`
218	346	jeremybenn	`illinsn_vector:`
219	90	jeremybenn	`l.addi r1,r1,-120`
220			`l.sw 0x1c(r1),r9`
221			`l.sw 0x20(r1),r10`
222			`l.movhi r9,hi(store_regs)`
223			`l.ori r9,r9,lo(store_regs)`
224	346	jeremybenn	`l.movhi r10,hi(excpt_illinsn)`
225			`l.ori r10,r10,lo(excpt_illinsn)`
226	90	jeremybenn	`l.jr r9`
227			`l.nop`
228			`l.nop`
229			`l.nop`
230			`l.nop`
231			`l.nop`
232			`l.nop`
233			`l.nop`
234			`l.nop`
235
236	458	julius	`.org 0x800`
237	346	jeremybenn	`int_vector:`
238	90	jeremybenn	`l.addi r1,r1,-120`
239			`l.sw 0x1c(r1),r9`
240			`l.sw 0x20(r1),r10`
241			`l.movhi r9,hi(store_regs)`
242			`l.ori r9,r9,lo(store_regs)`
243	346	jeremybenn	`l.movhi r10,hi(excpt_int)`
244			`l.ori r10,r10,lo(excpt_int)`
245	90	jeremybenn	`l.jr r9`
246			`l.nop`
247			`l.nop`
248			`l.nop`
249			`l.nop`
250			`l.nop`
251			`l.nop`
252			`l.nop`
253			`l.nop`
254
255	458	julius	`.org 0x900`
256	346	jeremybenn	`dtlbmiss_vector:`
257	90	jeremybenn	`l.addi r1,r1,-120`
258			`l.sw 0x1c(r1),r9`
259			`l.sw 0x20(r1),r10`
260			`l.movhi r9,hi(store_regs)`
261			`l.ori r9,r9,lo(store_regs)`
262	346	jeremybenn	`l.movhi r10,hi(excpt_dtlbmiss)`
263			`l.ori r10,r10,lo(excpt_dtlbmiss)`
264	90	jeremybenn	`l.jr r9`
265			`l.nop`
266			`l.nop`
267			`l.nop`
268			`l.nop`
269			`l.nop`
270			`l.nop`
271			`l.nop`
272			`l.nop`
273
274	458	julius	`.org 0xa00`
275	346	jeremybenn	`itlbmiss_vector:`
276	90	jeremybenn	`l.addi r1,r1,-120`
277			`l.sw 0x1c(r1),r9`
278			`l.sw 0x20(r1),r10`
279			`l.movhi r9,hi(store_regs)`
280			`l.ori r9,r9,lo(store_regs)`
281	346	jeremybenn	`l.movhi r10,hi(excpt_itlbmiss)`
282			`l.ori r10,r10,lo(excpt_itlbmiss)`
283	90	jeremybenn	`l.jr r9`
284			`l.nop`
285			`l.nop`
286			`l.nop`
287			`l.nop`
288			`l.nop`
289			`l.nop`
290			`l.nop`
291			`l.nop`
292
293	458	julius	`.org 0xb00`
294	346	jeremybenn	`range_vector:`
295	90	jeremybenn	`l.addi r1,r1,-120`
296			`l.sw 0x1c(r1),r9`
297			`l.sw 0x20(r1),r10`
298			`l.movhi r9,hi(store_regs)`
299			`l.ori r9,r9,lo(store_regs)`
300	346	jeremybenn	`l.movhi r10,hi(excpt_range)`
301			`l.ori r10,r10,lo(excpt_range)`
302	90	jeremybenn	`l.jr r9`
303			`l.nop`
304			`l.nop`
305			`l.nop`
306			`l.nop`
307			`l.nop`
308			`l.nop`
309			`l.nop`
310			`l.nop`
311
312	458	julius	`.org 0xc00`
313	346	jeremybenn	`syscall_vector:`
314	90	jeremybenn	`l.addi r3,r3,4`
315
316			`l.mfspr r4,r0,SPR_SR`
317			`l.andi r4,r4,7`
318			`l.add r6,r0,r4`
319
320			`l.mfspr r4,r0,SPR_EPCR_BASE`
321	346	jeremybenn	`l.movhi r5,hi(sys1)`
322			`l.ori r5,r5,lo(sys1)`
323	90	jeremybenn	`l.sub r5,r4,r5`
324
325			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
326			`l.ori r4,r4,SPR_SR_SM`
327			`l.mtspr r0,r4,SPR_ESR_BASE`
328
329	346	jeremybenn	`l.movhi r4,hi(sys2)`
330			`l.ori r4,r4,lo(sys2)`
331	90	jeremybenn	`l.mtspr r0,r4,SPR_EPCR_BASE`
332
333			`l.rfe`
334			`l.addi r3,r3,8`
335
336	458	julius	`.org 0xd00`
337	346	jeremybenn	`break_vector:`
338	90	jeremybenn	`l.addi r1,r1,-120`
339			`l.sw 0x1c(r1),r9`
340			`l.sw 0x20(r1),r10`
341			`l.movhi r9,hi(store_regs)`
342			`l.ori r9,r9,lo(store_regs)`
343	346	jeremybenn	`l.movhi r10,hi(excpt_break)`
344			`l.ori r10,r10,lo(excpt_break)`
345	90	jeremybenn	`l.jr r9`
346			`l.nop`
347			`l.nop`
348			`l.nop`
349			`l.nop`
350			`l.nop`
351			`l.nop`
352			`l.nop`
353			`l.nop`
354
355	458	julius	`.org 0xe00`
356	346	jeremybenn	`trap_vector:`
357	90	jeremybenn	`l.addi r1,r1,-120`
358			`l.sw 0x1c(r1),r9`
359			`l.sw 0x20(r1),r10`
360			`l.movhi r9,hi(store_regs)`
361			`l.ori r9,r9,lo(store_regs)`
362	346	jeremybenn	`l.movhi r10,hi(excpt_trap)`
363			`l.ori r10,r10,lo(excpt_trap)`
364	90	jeremybenn	`l.jr r9`
365			`l.nop`
366			`l.nop`
367			`l.nop`
368			`l.nop`
369			`l.nop`
370			`l.nop`
371			`l.nop`
372			`l.nop`
373	458	julius
374	90	jeremybenn
375	458	julius	`.section .text`
376
377	90	jeremybenn	`start:`
378
379	346	jeremybenn	`l.movhi r1,hi(stack)`
380			`l.ori r1,r1,lo(stack)`
381	458	julius	`l.ori r2,r1,0`
382	90	jeremybenn
383	458	julius	`bss_clear:`
384			`/* Clear BSS */`
385			`l.movhi r3, hi(_bstart)`
386			`l.ori r3, r3, lo(_bstart)`
387			`l.movhi r4, hi(_bend)`
388			`l.ori r4, r4, lo(_bend)`
389			`bss_clear_loop:`
390			`l.sw 0(r3), r0`
391			`l.sfgtu r3, r4`
392			`l.bnf bss_clear_loop`
393			`l.addi r3, r3, 4`
394
395
396			`l.movhi r3,hi(reset)`
397			`l.ori r3,r3,lo(reset)`
398			`l.jr r3`
399	90	jeremybenn	`l.nop`
400
401			`store_regs:`
402			`l.sw 0x00(r1),r2`
403			`l.sw 0x04(r1),r3`
404			`l.sw 0x08(r1),r4`
405			`l.sw 0x0c(r1),r5`
406			`l.sw 0x10(r1),r6`
407			`l.sw 0x14(r1),r7`
408			`l.sw 0x18(r1),r8`
409			`l.sw 0x24(r1),r11`
410			`l.sw 0x28(r1),r12`
411			`l.sw 0x2c(r1),r13`
412			`l.sw 0x30(r1),r14`
413			`l.sw 0x34(r1),r15`
414			`l.sw 0x38(r1),r16`
415			`l.sw 0x3c(r1),r17`
416			`l.sw 0x40(r1),r18`
417			`l.sw 0x44(r1),r19`
418			`l.sw 0x48(r1),r20`
419			`l.sw 0x4c(r1),r21`
420			`l.sw 0x50(r1),r22`
421			`l.sw 0x54(r1),r23`
422			`l.sw 0x58(r1),r24`
423			`l.sw 0x5c(r1),r25`
424			`l.sw 0x60(r1),r26`
425			`l.sw 0x64(r1),r27`
426			`l.sw 0x68(r1),r28`
427			`l.sw 0x6c(r1),r29`
428			`l.sw 0x70(r1),r30`
429			`l.sw 0x74(r1),r31`
430
431			`l.mfspr r3,r0,SPR_EPCR_BASE`
432	346	jeremybenn	`l.movhi r4,hi(except_pc)`
433			`l.ori r4,r4,lo(except_pc)`
434	90	jeremybenn	`l.sw 0(r4),r3`
435
436			`l.mfspr r3,r0,SPR_EEAR_BASE`
437	346	jeremybenn	`l.movhi r4,hi(except_ea)`
438			`l.ori r4,r4,lo(except_ea)`
439	90	jeremybenn	`l.sw 0(r4),r3`
440
441			`l.movhi r9,hi(end_except)`
442			`l.ori r9,r9,lo(end_except)`
443
444			`l.lwz r10,0(r10)`
445			`l.jr r10`
446			`l.nop`
447
448			`end_except:`
449			`l.lwz r2,0x00(r1)`
450			`l.lwz r3,0x04(r1)`
451			`l.lwz r4,0x08(r1)`
452			`l.lwz r5,0x0c(r1)`
453			`l.lwz r6,0x10(r1)`
454			`l.lwz r7,0x14(r1)`
455			`l.lwz r8,0x18(r1)`
456			`l.lwz r9,0x1c(r1)`
457			`l.lwz r10,0x20(r1)`
458			`l.lwz r11,0x24(r1)`
459			`l.lwz r12,0x28(r1)`
460			`l.lwz r13,0x2c(r1)`
461			`l.lwz r14,0x30(r1)`
462			`l.lwz r15,0x34(r1)`
463			`l.lwz r16,0x38(r1)`
464			`l.lwz r17,0x3c(r1)`
465			`l.lwz r18,0x40(r1)`
466			`l.lwz r19,0x44(r1)`
467			`l.lwz r20,0x48(r1)`
468			`l.lwz r21,0x4c(r1)`
469			`l.lwz r22,0x50(r1)`
470			`l.lwz r23,0x54(r1)`
471			`l.lwz r24,0x58(r1)`
472			`l.lwz r25,0x5c(r1)`
473			`l.lwz r26,0x60(r1)`
474			`l.lwz r27,0x64(r1)`
475			`l.lwz r28,0x68(r1)`
476			`l.lwz r29,0x6c(r1)`
477			`l.lwz r30,0x70(r1)`
478			`l.lwz r31,0x74(r1)`
479			`l.addi r1,r1,120`
480			`l.mtspr r0,r9,SPR_EPCR_BASE`
481			`l.rfe`
482			`l.nop`
483
484	346	jeremybenn	`except_basic:`
485			`sys1:`
486	90	jeremybenn	`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
487			`l.mfspr r4,r0,SPR_SR`
488			`l.and r4,r4,r3`
489			`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
490			`l.mtspr r0,r4,SPR_SR`
491
492			`l.addi r3,r0,0`
493			`l.sys 1`
494			`l.addi r3,r3,2`
495
496	346	jeremybenn	`sys2:`
497	90	jeremybenn	`l.addi r11,r0,0`
498
499			`l.mfspr r4,r0,SPR_SR /* Check SR */`
500			`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`

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