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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except-test/] [except-test-s.S] - Blame information for rev 90

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/* except-test-s.S. Machine code support for test of Or1ksim exception handling
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
#include "spr-defs.h"
#include "board.h"
 
#define reset _main
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
        .global _except_basic
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _call
        .global _call_with_int
        .global _load_acc_32
        .global _load_acc_16
        .global _store_acc_32
        .global _store_acc_16
        .global _load_b_acc_32
        .global _trap
        .global _b_trap
        .global _range
        .global _b_range
        .global _int_trigger
        .global _int_loop
        .global _jump_back
 
        .section .stack
        .space 0x1000
_stack:
 
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
  .section .except, "ax"
 
_buserr_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_dpfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_ipfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_tick_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_align_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_illinsn_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_int_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_dtlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_itlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_range_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_syscall_vector:
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(_sys1)
        l.ori r5,r5,lo(_sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(_sys2)
        l.ori r4,r4,lo(_sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
_break_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_trap_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        /* Our special text section is used to guarantee this code goes first
           when linking. */
        .section .except-text
 
        .org    0x100
_reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
start:
        l.jal   _init_mc
        l.nop
 
        l.movhi r1,hi(_stack)
        l.ori   r1,r1,lo(_stack)
 
        /* Setup exception wrappers */
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.addi  r7,r0,0x100
 
1:      l.addi  r7,r7,0x100
        l.sfeqi r7,0xf00
        l.bf    1f
        l.nop
        l.addi  r4,r7,0
        l.addi  r5,r0,0
2:
        l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,1
        l.sfeqi r5,16
        l.bf    1b
        l.nop
        l.j     2b
        l.nop
1:
        /* Copy data section */
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
 
2:
 
        l.movhi r2,hi(reset)
        l.ori   r2,r2,lo(reset)
        l.jr    r2
        l.nop
 
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
 
store_regs:
        l.sw    0x00(r1),r2
        l.sw    0x04(r1),r3
        l.sw    0x08(r1),r4
        l.sw    0x0c(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
 
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
end_except:
        l.lwz   r2,0x00(r1)
        l.lwz   r3,0x04(r1)
        l.lwz   r4,0x08(r1)
        l.lwz   r5,0x0c(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.addi  r1,r1,120
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
  .section .text
 
_except_basic:
_sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
_sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
_lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
_call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
_load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
_load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
_store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
_store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
_load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
_b_trap:
        l.jr    r9
_trap:
        l.trap  1
        l.jr    r9
        l.nop
 
_b_range:
        l.jr    r9
_range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
_int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
_int_loop:
        l.j     _int_loop
        l.lwz   r5,0(r4);
 
_jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1
 

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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except-test/] [except-test-s.S] - Blame information for rev 90

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except-test-s.S. Machine code support for test of Or1ksim exception handling`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`#include "spr-defs.h"`
29			`#include "board.h"`
30
31			`#define reset _main`
32
33			`#define MC_CSR (0x00)`
34			`#define MC_POC (0x04)`
35			`#define MC_BA_MASK (0x08)`
36			`#define MC_CSC(i) (0x10 + (i) * 8)`
37			`#define MC_TMS(i) (0x14 + (i) * 8)`
38
39			`.global _except_basic`
40			`.global _lo_dmmu_en`
41			`.global _lo_immu_en`
42			`.global _call`
43			`.global _call_with_int`
44			`.global _load_acc_32`
45			`.global _load_acc_16`
46			`.global _store_acc_32`
47			`.global _store_acc_16`
48			`.global _load_b_acc_32`
49			`.global _trap`
50			`.global _b_trap`
51			`.global _range`
52			`.global _b_range`
53			`.global _int_trigger`
54			`.global _int_loop`
55			`.global _jump_back`
56
57			`.section .stack`
58			`.space 0x1000`
59			`_stack:`
60
61			`.extern _reset_support`
62			`.extern _c_reset`
63			`.extern _excpt_buserr`
64			`.extern _excpt_dpfault`
65			`.extern _excpt_ipfault`
66			`.extern _excpt_tick`
67			`.extern _excpt_align`
68			`.extern _excpt_illinsn`
69			`.extern _excpt_int`
70			`.extern _excpt_dtlbmiss`
71			`.extern _excpt_itlbmiss`
72			`.extern _excpt_range`
73			`.extern _excpt_syscall`
74			`.extern _excpt_break`
75			`.extern _excpt_trap`
76
77			`.section .except, "ax"`
78
79			`_buserr_vector:`
80			`l.addi r1,r1,-120`
81			`l.sw 0x1c(r1),r9`
82			`l.sw 0x20(r1),r10`
83			`l.movhi r9,hi(store_regs)`
84			`l.ori r9,r9,lo(store_regs)`
85			`l.movhi r10,hi(_excpt_buserr)`
86			`l.ori r10,r10,lo(_excpt_buserr)`
87			`l.jr r9`
88			`l.nop`
89			`l.nop`
90			`l.nop`
91			`l.nop`
92			`l.nop`
93			`l.nop`
94			`l.nop`
95			`l.nop`
96
97			`_dpfault_vector:`
98			`l.addi r1,r1,-120`
99			`l.sw 0x1c(r1),r9`
100			`l.sw 0x20(r1),r10`
101			`l.movhi r9,hi(store_regs)`
102			`l.ori r9,r9,lo(store_regs)`
103			`l.movhi r10,hi(_excpt_dpfault)`
104			`l.ori r10,r10,lo(_excpt_dpfault)`
105			`l.jr r9`
106			`l.nop`
107			`l.nop`
108			`l.nop`
109			`l.nop`
110			`l.nop`
111			`l.nop`
112			`l.nop`
113			`l.nop`
114
115			`_ipfault_vector:`
116			`l.addi r1,r1,-120`
117			`l.sw 0x1c(r1),r9`
118			`l.sw 0x20(r1),r10`
119			`l.movhi r9,hi(store_regs)`
120			`l.ori r9,r9,lo(store_regs)`
121			`l.movhi r10,hi(_excpt_ipfault)`
122			`l.ori r10,r10,lo(_excpt_ipfault)`
123			`l.jr r9`
124			`l.nop`
125			`l.nop`
126			`l.nop`
127			`l.nop`
128			`l.nop`
129			`l.nop`
130			`l.nop`
131			`l.nop`
132
133			`_tick_vector:`
134			`l.addi r1,r1,-120`
135			`l.sw 0x1c(r1),r9`
136			`l.sw 0x20(r1),r10`
137			`l.movhi r9,hi(store_regs)`
138			`l.ori r9,r9,lo(store_regs)`
139			`l.movhi r10,hi(_excpt_tick)`
140			`l.ori r10,r10,lo(_excpt_tick)`
141			`l.jr r9`
142			`l.nop`
143			`l.nop`
144			`l.nop`
145			`l.nop`
146			`l.nop`
147			`l.nop`
148			`l.nop`
149			`l.nop`
150
151			`_align_vector:`
152			`l.addi r1,r1,-120`
153			`l.sw 0x1c(r1),r9`
154			`l.sw 0x20(r1),r10`
155			`l.movhi r9,hi(store_regs)`
156			`l.ori r9,r9,lo(store_regs)`
157			`l.movhi r10,hi(_excpt_align)`
158			`l.ori r10,r10,lo(_excpt_align)`
159			`l.jr r9`
160			`l.nop`
161			`l.nop`
162			`l.nop`
163			`l.nop`
164			`l.nop`
165			`l.nop`
166			`l.nop`
167			`l.nop`
168
169			`_illinsn_vector:`
170			`l.addi r1,r1,-120`
171			`l.sw 0x1c(r1),r9`
172			`l.sw 0x20(r1),r10`
173			`l.movhi r9,hi(store_regs)`
174			`l.ori r9,r9,lo(store_regs)`
175			`l.movhi r10,hi(_excpt_illinsn)`
176			`l.ori r10,r10,lo(_excpt_illinsn)`
177			`l.jr r9`
178			`l.nop`
179			`l.nop`
180			`l.nop`
181			`l.nop`
182			`l.nop`
183			`l.nop`
184			`l.nop`
185			`l.nop`
186
187			`_int_vector:`
188			`l.addi r1,r1,-120`
189			`l.sw 0x1c(r1),r9`
190			`l.sw 0x20(r1),r10`
191			`l.movhi r9,hi(store_regs)`
192			`l.ori r9,r9,lo(store_regs)`
193			`l.movhi r10,hi(_excpt_int)`
194			`l.ori r10,r10,lo(_excpt_int)`
195			`l.jr r9`
196			`l.nop`
197			`l.nop`
198			`l.nop`
199			`l.nop`
200			`l.nop`
201			`l.nop`
202			`l.nop`
203			`l.nop`
204
205			`_dtlbmiss_vector:`
206			`l.addi r1,r1,-120`
207			`l.sw 0x1c(r1),r9`
208			`l.sw 0x20(r1),r10`
209			`l.movhi r9,hi(store_regs)`
210			`l.ori r9,r9,lo(store_regs)`
211			`l.movhi r10,hi(_excpt_dtlbmiss)`
212			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
213			`l.jr r9`
214			`l.nop`
215			`l.nop`
216			`l.nop`
217			`l.nop`
218			`l.nop`
219			`l.nop`
220			`l.nop`
221			`l.nop`
222
223			`_itlbmiss_vector:`
224			`l.addi r1,r1,-120`
225			`l.sw 0x1c(r1),r9`
226			`l.sw 0x20(r1),r10`
227			`l.movhi r9,hi(store_regs)`
228			`l.ori r9,r9,lo(store_regs)`
229			`l.movhi r10,hi(_excpt_itlbmiss)`
230			`l.ori r10,r10,lo(_excpt_itlbmiss)`
231			`l.jr r9`
232			`l.nop`
233			`l.nop`
234			`l.nop`
235			`l.nop`
236			`l.nop`
237			`l.nop`
238			`l.nop`
239			`l.nop`
240
241			`_range_vector:`
242			`l.addi r1,r1,-120`
243			`l.sw 0x1c(r1),r9`
244			`l.sw 0x20(r1),r10`
245			`l.movhi r9,hi(store_regs)`
246			`l.ori r9,r9,lo(store_regs)`
247			`l.movhi r10,hi(_excpt_range)`
248			`l.ori r10,r10,lo(_excpt_range)`
249			`l.jr r9`
250			`l.nop`
251			`l.nop`
252			`l.nop`
253			`l.nop`
254			`l.nop`
255			`l.nop`
256			`l.nop`
257			`l.nop`
258
259			`_syscall_vector:`
260			`l.addi r3,r3,4`
261
262			`l.mfspr r4,r0,SPR_SR`
263			`l.andi r4,r4,7`
264			`l.add r6,r0,r4`
265
266			`l.mfspr r4,r0,SPR_EPCR_BASE`
267			`l.movhi r5,hi(_sys1)`
268			`l.ori r5,r5,lo(_sys1)`
269			`l.sub r5,r4,r5`
270
271			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
272			`l.ori r4,r4,SPR_SR_SM`
273			`l.mtspr r0,r4,SPR_ESR_BASE`
274
275			`l.movhi r4,hi(_sys2)`
276			`l.ori r4,r4,lo(_sys2)`
277			`l.mtspr r0,r4,SPR_EPCR_BASE`
278
279			`l.rfe`
280			`l.addi r3,r3,8`
281
282			`_break_vector:`
283			`l.addi r1,r1,-120`
284			`l.sw 0x1c(r1),r9`
285			`l.sw 0x20(r1),r10`
286			`l.movhi r9,hi(store_regs)`
287			`l.ori r9,r9,lo(store_regs)`
288			`l.movhi r10,hi(_excpt_break)`
289			`l.ori r10,r10,lo(_excpt_break)`
290			`l.jr r9`
291			`l.nop`
292			`l.nop`
293			`l.nop`
294			`l.nop`
295			`l.nop`
296			`l.nop`
297			`l.nop`
298			`l.nop`
299
300			`_trap_vector:`
301			`l.addi r1,r1,-120`
302			`l.sw 0x1c(r1),r9`
303			`l.sw 0x20(r1),r10`
304			`l.movhi r9,hi(store_regs)`
305			`l.ori r9,r9,lo(store_regs)`
306			`l.movhi r10,hi(_excpt_trap)`
307			`l.ori r10,r10,lo(_excpt_trap)`
308			`l.jr r9`
309			`l.nop`
310			`l.nop`
311			`l.nop`
312			`l.nop`
313			`l.nop`
314			`l.nop`
315			`l.nop`
316			`l.nop`
317
318			`/* Our special text section is used to guarantee this code goes first`
319			`when linking. */`
320			`.section .except-text`
321
322			`.org 0x100`
323			`_reset_vector:`
324			`l.nop`
325			`l.nop`
326			`l.addi r2,r0,0x0`
327			`l.addi r3,r0,0x0`
328			`l.addi r4,r0,0x0`
329			`l.addi r5,r0,0x0`
330			`l.addi r6,r0,0x0`
331			`l.addi r7,r0,0x0`
332			`l.addi r8,r0,0x0`
333			`l.addi r9,r0,0x0`
334			`l.addi r10,r0,0x0`
335			`l.addi r11,r0,0x0`
336			`l.addi r12,r0,0x0`
337			`l.addi r13,r0,0x0`
338			`l.addi r14,r0,0x0`
339			`l.addi r15,r0,0x0`
340			`l.addi r16,r0,0x0`
341			`l.addi r17,r0,0x0`
342			`l.addi r18,r0,0x0`
343			`l.addi r19,r0,0x0`
344			`l.addi r20,r0,0x0`
345			`l.addi r21,r0,0x0`
346			`l.addi r22,r0,0x0`
347			`l.addi r23,r0,0x0`
348			`l.addi r24,r0,0x0`
349			`l.addi r25,r0,0x0`
350			`l.addi r26,r0,0x0`
351			`l.addi r27,r0,0x0`
352			`l.addi r28,r0,0x0`
353			`l.addi r29,r0,0x0`
354			`l.addi r30,r0,0x0`
355			`l.addi r31,r0,0x0`
356
357			`l.movhi r3,hi(start)`
358			`l.ori r3,r3,lo(start)`
359			`l.jr r3`
360			`l.nop`
361			`start:`
362			`l.jal _init_mc`
363			`l.nop`
364
365			`l.movhi r1,hi(_stack)`
366			`l.ori r1,r1,lo(_stack)`
367
368			`/* Setup exception wrappers */`
369			`l.movhi r3,hi(_src_beg)`
370			`l.ori r3,r3,lo(_src_beg)`
371			`l.addi r7,r0,0x100`
372
373			`1: l.addi r7,r7,0x100`
374			`l.sfeqi r7,0xf00`
375			`l.bf 1f`
376			`l.nop`
377			`l.addi r4,r7,0`
378			`l.addi r5,r0,0`
379			`2:`
380			`l.lwz r6,0(r3)`
381			`l.sw 0(r4),r6`
382			`l.addi r3,r3,4`
383			`l.addi r4,r4,4`
384			`l.addi r5,r5,1`
385			`l.sfeqi r5,16`
386			`l.bf 1b`
387			`l.nop`
388			`l.j 2b`
389			`l.nop`
390			`1:`
391			`/* Copy data section */`
392			`l.movhi r4,hi(_dst_beg)`
393			`l.ori r4,r4,lo(_dst_beg)`
394			`l.movhi r5,hi(_dst_end)`
395			`l.ori r5,r5,lo(_dst_end)`
396			`l.sub r5,r5,r4`
397			`l.sfeqi r5,0`
398			`l.bf 2f`
399			`l.nop`
400			`1: l.lwz r6,0(r3)`
401			`l.sw 0(r4),r6`
402			`l.addi r3,r3,4`
403			`l.addi r4,r4,4`
404			`l.addi r5,r5,-4`
405			`l.sfgtsi r5,0`
406			`l.bf 1b`
407			`l.nop`
408
409			`2:`
410
411			`l.movhi r2,hi(reset)`
412			`l.ori r2,r2,lo(reset)`
413			`l.jr r2`
414			`l.nop`
415
416			`_init_mc:`
417
418			`l.movhi r3,hi(MC_BASE_ADDR)`
419			`l.ori r3,r3,lo(MC_BASE_ADDR)`
420
421			`l.addi r4,r3,MC_CSC(0)`
422			`l.movhi r5,hi(FLASH_BASE_ADDR)`
423			`l.srai r5,r5,6`
424			`l.ori r5,r5,0x0025`
425			`l.sw 0(r4),r5`
426
427			`l.addi r4,r3,MC_TMS(0)`
428			`l.movhi r5,hi(FLASH_TMS_VAL)`
429			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
430			`l.sw 0(r4),r5`
431
432			`l.addi r4,r3,MC_BA_MASK`
433			`l.addi r5,r0,MC_MASK_VAL`
434			`l.sw 0(r4),r5`
435
436			`l.addi r4,r3,MC_CSR`
437			`l.movhi r5,hi(MC_CSR_VAL)`
438			`l.ori r5,r5,lo(MC_CSR_VAL)`
439			`l.sw 0(r4),r5`
440
441			`l.addi r4,r3,MC_TMS(1)`
442			`l.movhi r5,hi(SDRAM_TMS_VAL)`
443			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
444			`l.sw 0(r4),r5`
445
446			`l.addi r4,r3,MC_CSC(1)`
447			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
448			`l.srai r5,r5,6`
449			`l.ori r5,r5,0x0411`
450			`l.sw 0(r4),r5`
451
452			`l.jr r9`
453			`l.nop`
454
455			`store_regs:`
456			`l.sw 0x00(r1),r2`
457			`l.sw 0x04(r1),r3`
458			`l.sw 0x08(r1),r4`
459			`l.sw 0x0c(r1),r5`
460			`l.sw 0x10(r1),r6`
461			`l.sw 0x14(r1),r7`
462			`l.sw 0x18(r1),r8`
463			`l.sw 0x24(r1),r11`
464			`l.sw 0x28(r1),r12`
465			`l.sw 0x2c(r1),r13`
466			`l.sw 0x30(r1),r14`
467			`l.sw 0x34(r1),r15`
468			`l.sw 0x38(r1),r16`
469			`l.sw 0x3c(r1),r17`
470			`l.sw 0x40(r1),r18`
471			`l.sw 0x44(r1),r19`
472			`l.sw 0x48(r1),r20`
473			`l.sw 0x4c(r1),r21`
474			`l.sw 0x50(r1),r22`
475			`l.sw 0x54(r1),r23`
476			`l.sw 0x58(r1),r24`
477			`l.sw 0x5c(r1),r25`
478			`l.sw 0x60(r1),r26`
479			`l.sw 0x64(r1),r27`
480			`l.sw 0x68(r1),r28`
481			`l.sw 0x6c(r1),r29`
482			`l.sw 0x70(r1),r30`
483			`l.sw 0x74(r1),r31`
484
485			`l.mfspr r3,r0,SPR_EPCR_BASE`
486			`l.movhi r4,hi(_except_pc)`
487			`l.ori r4,r4,lo(_except_pc)`
488			`l.sw 0(r4),r3`
489
490			`l.mfspr r3,r0,SPR_EEAR_BASE`
491			`l.movhi r4,hi(_except_ea)`
492			`l.ori r4,r4,lo(_except_ea)`
493			`l.sw 0(r4),r3`
494
495			`l.movhi r9,hi(end_except)`
496			`l.ori r9,r9,lo(end_except)`
497
498			`l.lwz r10,0(r10)`
499			`l.jr r10`
500			`l.nop`
501
502			`end_except:`
503			`l.lwz r2,0x00(r1)`
504			`l.lwz r3,0x04(r1)`
505			`l.lwz r4,0x08(r1)`
506			`l.lwz r5,0x0c(r1)`
507			`l.lwz r6,0x10(r1)`
508			`l.lwz r7,0x14(r1)`
509			`l.lwz r8,0x18(r1)`
510			`l.lwz r9,0x1c(r1)`
511			`l.lwz r10,0x20(r1)`
512			`l.lwz r11,0x24(r1)`
513			`l.lwz r12,0x28(r1)`
514			`l.lwz r13,0x2c(r1)`
515			`l.lwz r14,0x30(r1)`
516			`l.lwz r15,0x34(r1)`
517			`l.lwz r16,0x38(r1)`
518			`l.lwz r17,0x3c(r1)`
519			`l.lwz r18,0x40(r1)`
520			`l.lwz r19,0x44(r1)`
521			`l.lwz r20,0x48(r1)`
522			`l.lwz r21,0x4c(r1)`
523			`l.lwz r22,0x50(r1)`
524			`l.lwz r23,0x54(r1)`
525			`l.lwz r24,0x58(r1)`
526			`l.lwz r25,0x5c(r1)`
527			`l.lwz r26,0x60(r1)`
528			`l.lwz r27,0x64(r1)`
529			`l.lwz r28,0x68(r1)`
530			`l.lwz r29,0x6c(r1)`
531			`l.lwz r30,0x70(r1)`
532			`l.lwz r31,0x74(r1)`
533			`l.addi r1,r1,120`
534			`l.mtspr r0,r9,SPR_EPCR_BASE`
535			`l.rfe`
536			`l.nop`
537
538			`.section .text`
539
540			`_except_basic:`
541			`_sys1:`
542			`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
543			`l.mfspr r4,r0,SPR_SR`
544			`l.and r4,r4,r3`
545			`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
546			`l.mtspr r0,r4,SPR_SR`
547
548			`l.addi r3,r0,0`
549			`l.sys 1`
550			`l.addi r3,r3,2`
551
552			`_sys2:`
553			`l.addi r11,r0,0`
554
555			`l.mfspr r4,r0,SPR_SR /* Check SR */`
556			`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
557			`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
558			`l.bf 1f`
559			`l.nop`
560			`l.addi r11,r11,1`
561			`1:`
562			`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`
563			`l.bf 1f`
564			`l.nop`
565			`l.addi r11,r11,2`
566			`1:`
567			`l.sfeqi r5,0x1c /* Check the EPCR */`
568			`l.bf 1f`
569			`l.nop`
570			`l.addi r11,r11,4`
571			`1:`
572			`l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */`
573			`l.bf 1f`
574			`l.nop`
575			`l.addi r11,r11,8`
576			`1:`
577			`l.jr r9`
578			`l.nop`
579
580			`_lo_dmmu_en:`
581			`l.mfspr r3,r0,SPR_SR`
582			`l.ori r3,r3,SPR_SR_DME`
583			`l.mtspr r0,r3,SPR_ESR_BASE`
584			`l.mtspr r0,r9,SPR_EPCR_BASE`
585			`l.rfe`
586			`l.nop`
587
588			`_lo_immu_en:`
589			`l.mfspr r3,r0,SPR_SR`
590			`l.ori r3,r3,SPR_SR_IME`
591			`l.mtspr r0,r3,SPR_ESR_BASE`
592			`l.mtspr r0,r9,SPR_EPCR_BASE`
593			`l.rfe`
594			`l.nop`
595
596			`_call:`
597			`l.addi r11,r0,0`
598			`l.jr r3`
599			`l.nop`
600
601			`_call_with_int:`
602			`l.mfspr r8,r0,SPR_SR`
603			`l.ori r8,r8,SPR_SR_TEE`
604			`l.mtspr r0,r8,SPR_ESR_BASE`
605			`l.mtspr r0,r3,SPR_EPCR_BASE`
606			`l.rfe`
607
608			`_load_acc_32:`
609			`l.movhi r11,hi(0x12345678)`
610			`l.ori r11,r11,lo(0x12345678)`
611			`l.lwz r11,0(r4)`
612			`l.jr r9`
613			`l.nop`
614
615			`_load_acc_16:`
616			`l.movhi r11,hi(0x12345678)`
617			`l.ori r11,r11,lo(0x12345678)`
618			`l.lhz r11,0(r4)`
619			`l.jr r9`
620			`l.nop`
621
622			`_store_acc_32:`
623			`l.movhi r3,hi(0x12345678)`
624			`l.ori r3,r3,lo(0x12345678)`
625			`l.sw 0(r4),r3`
626			`l.jr r9`
627			`l.nop`
628
629			`_store_acc_16:`
630			`l.movhi r3,hi(0x12345678)`
631			`l.ori r3,r3,lo(0x12345678)`
632			`l.sh 0(r4),r3`
633			`l.jr r9`
634			`l.nop`
635
636			`_load_b_acc_32:`
637			`l.movhi r11,hi(0x12345678)`
638			`l.ori r11,r11,lo(0x12345678)`
639			`l.jr r9`
640			`l.lwz r11,0(r4)`
641
642			`_b_trap:`
643			`l.jr r9`
644			`_trap:`
645			`l.trap 1`
646			`l.jr r9`
647			`l.nop`
648
649			`_b_range:`
650			`l.jr r9`
651			`_range:`
652			`l.addi r3,r0,-1`
653			`l.jr r9`
654			`l.nop`
655
656			`_int_trigger:`
657			`l.addi r11,r0,0`
658			`l.mfspr r3,r0,SPR_SR`
659			`l.ori r3,r3,SPR_SR_TEE`
660			`l.mtspr r0,r3,SPR_SR`
661			`l.addi r11,r11,1`
662
663			`_int_loop:`
664			`l.j _int_loop`
665			`l.lwz r5,0(r4);`
666
667			`_jump_back:`
668			`l.addi r11,r0,0`
669			`l.jr r9`
670			`l.addi r11,r11,1`
671