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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [ext/] [ext.S] - Blame information for rev 867

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Line No. Rev Author Line
1 90 jeremybenn 
/* ext.S -- Tests the l.ext{b,h}{s,z} instructions
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   Copyright (C) 2005 György `nog' Jeney
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   Copyright (C) 2010 Embecosm Limited
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   Contributor György `nog' Jeney
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   Contributor Jeremy Bennett
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see .  */
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/* ----------------------------------------------------------------------------
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   This code is commented throughout for use with Doxygen.
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   --------------------------------------------------------------------------*/
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#include "spr-defs.h"
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30 458 julius 
        .section .except,"ax"
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32 90 jeremybenn 
        .org 0x100
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        l.j     start_test
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        l.nop
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        .org 0x200
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        l.jal   unhandled_except
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        l.nop
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        .org 0x300
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        l.jal   unhandled_except
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        l.nop
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        .org 0x400
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        l.jal   unhandled_except
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        l.nop
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        .org 0x500
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        l.jal   unhandled_except
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        l.nop
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        .org 0x600
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        l.jal   unhandled_except
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        l.nop
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        .org 0x700
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        l.jal   unhandled_except
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        l.nop
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        .org 0x800
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        l.jal   unhandled_except
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        l.nop
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        .org 0x900
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        l.jal   unhandled_except
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        l.nop
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        .org 0xa00
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        l.jal   unhandled_except
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        l.nop
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        .org 0xb00
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        l.jal   unhandled_except
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        l.nop
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        .org 0xc00
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        l.jal   unhandled_except
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        l.nop
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        .org 0xd00
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        l.jal   unhandled_except
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        l.nop
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        .org 0xe00
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        l.jal   unhandled_except
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        l.nop
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        .org 0xf00
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        l.jal   unhandled_except
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        l.nop
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#define CHECK_EXT(insn, val, mask, high_mask) \
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        l.movhi r4,hi(val); \
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        l.ori   r4,r4,lo(val); \
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        l.ori   r3,r4,0; \
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        l.nop   NOP_REPORT; \
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        insn    r5,r4; \
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        l.ori   r3,r5,0; \
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        l.nop   NOP_REPORT; \
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        \
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        l.movhi r6,hi(mask); \
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        l.ori   r6,r6,lo(mask); \
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        l.xori  r7,r6,-1; \
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        \
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        l.and   r8,r4,r6; \
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        l.and   r9,r5,r6; \
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        l.sfne  r8,r9; \
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        l.bf    ext_fail; \
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        l.nop; \
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        l.and   r8,r5,r7; \
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        \
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        l.movhi r7,hi(high_mask); \
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        l.ori   r7,r7,lo(high_mask); \
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        \
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        l.sfne  r8,r7; \
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        l.bf    ext_fail; \
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        l.nop;
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#define CHECK_HIGH3_CLEAR(insn, val) CHECK_EXT(insn, val, 0x000000ff, 0)
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#define CHECK_HIGH3_SET(val) CHECK_EXT(l.extbs, val, 0x000000ff, 0xffffff00)
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#define CHECK_HIGH2_CLEAR(insn, val) CHECK_EXT(insn, val, 0x0000ffff, 0)
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#define CHECK_HIGH2_SET(val) CHECK_EXT(l.exths, val, 0x0000ffff, 0xffff0000)
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#define CHECK_MOVE(insn, val) \
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        l.movhi r4,hi(val); \
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        l.ori   r4,r4,lo(val); \
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        l.ori   r3,r4,0; \
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        l.nop   NOP_REPORT; \
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        insn    r5,r4; \
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        l.ori   r3,r5,0; \
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        l.nop   NOP_REPORT; \
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        l.sfne  r5,r4; \
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        l.bf    ext_fail; \
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        l.nop;
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122 458 julius 
        .section .text
123 90 jeremybenn 
start_test:
124 787 jeremybenn 
    // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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    // and indeed it is not when simulating the or1200 Verilog core.
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    l.andi  r0,r0,0x0
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128 90 jeremybenn 
        /* Test l.extbs */
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        CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
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        CHECK_HIGH3_CLEAR(l.extbs, 0x53)
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        CHECK_HIGH3_CLEAR(l.extbs, 0xff53)
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        CHECK_HIGH3_CLEAR(l.extbs, 0x1234)
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        CHECK_HIGH3_SET(0xff)
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        CHECK_HIGH3_SET(0x80)
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        CHECK_HIGH3_SET(0xff80)
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        CHECK_HIGH3_SET(0x7f80)
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        CHECK_HIGH3_SET(0x7fff)
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        /* Test l.extbz */
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        CHECK_HIGH3_CLEAR(l.extbz, 0x7f)
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        CHECK_HIGH3_CLEAR(l.extbz, 0x53)
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        CHECK_HIGH3_CLEAR(l.extbz, 0xff53)
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        CHECK_HIGH3_CLEAR(l.extbz, 0x1234)
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        CHECK_HIGH3_CLEAR(l.extbz, 0xff)
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        CHECK_HIGH3_CLEAR(l.extbz, 0x80)
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        CHECK_HIGH3_CLEAR(l.extbz, 0xff80)
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        CHECK_HIGH3_CLEAR(l.extbz, 0x7f80)
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        CHECK_HIGH3_CLEAR(l.extbz, 0x7fff)
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        /* Test l.exths */
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        CHECK_HIGH2_CLEAR(l.exths, 0x7fff)
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        CHECK_HIGH2_CLEAR(l.exths, 0x5233)
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        CHECK_HIGH2_CLEAR(l.exths, 0xffff2f53)
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        CHECK_HIGH2_CLEAR(l.exths, 0x12345678)
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        CHECK_HIGH2_SET(0xffff)
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        CHECK_HIGH2_SET(0x8000)
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        CHECK_HIGH2_SET(0xff80)
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        CHECK_HIGH2_SET(0x80008000)
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        CHECK_HIGH2_SET(0x7fffffff)
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        /* Test l.exthz */
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        CHECK_HIGH2_CLEAR(l.exthz, 0x7fff)
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        CHECK_HIGH2_CLEAR(l.exthz, 0x5233)
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        CHECK_HIGH2_CLEAR(l.exthz, 0xffff2f53)
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        CHECK_HIGH2_CLEAR(l.exthz, 0x12345678)
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        CHECK_HIGH2_CLEAR(l.exthz, 0xffff)
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        CHECK_HIGH2_CLEAR(l.exthz, 0x8000)
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        CHECK_HIGH2_CLEAR(l.exthz, 0xff80)
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        CHECK_HIGH2_CLEAR(l.exthz, 0x80008000)
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        CHECK_HIGH2_CLEAR(l.exthz, 0x7fffffff)
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        /* Test l.extws */
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        CHECK_MOVE(l.extws, 0xffffffff)
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        CHECK_MOVE(l.extws, 0x7fffffff)
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        CHECK_MOVE(l.extws, 0x7fff7fff)
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        CHECK_MOVE(l.extws, 0xffff7f7f)
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        CHECK_MOVE(l.extws, 0xffffff7f)
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        CHECK_MOVE(l.extws, 0xffff7fff)
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        CHECK_MOVE(l.extws, 0x7fff7f7f)
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        CHECK_MOVE(l.extws, 0x12345678)
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        /* Test l.extwz */
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        CHECK_MOVE(l.extwz, 0xffffffff)
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        CHECK_MOVE(l.extwz, 0x7fffffff)
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        CHECK_MOVE(l.extwz, 0x7fff7fff)
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        CHECK_MOVE(l.extwz, 0xffff7f7f)
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        CHECK_MOVE(l.extwz, 0xffffff7f)
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        CHECK_MOVE(l.extwz, 0xffff7fff)
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        CHECK_MOVE(l.extwz, 0x7fff7f7f)
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        CHECK_MOVE(l.extwz, 0x12345678)
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196 
        l.movhi r3,0xdead
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        l.ori   r3,r3,0xdead
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        l.nop   NOP_REPORT
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        l.ori   r3,r0,0
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        l.nop   NOP_EXIT
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ext_fail:
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        l.ori   r3,r0,0x1234
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        l.nop   NOP_EXIT
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unhandled_except:
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        l.addi  r3,r9,-8
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        l.nop   NOP_REPORT
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        l.nop   NOP_EXIT
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