OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [flag/] [flag.S] - Blame information for rev 566

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn 
/* flag.S. Test of Or1ksim status register flags
2 
 
3 
   Copyright (C) 1999-2006 OpenCores
4 
   Copyright (C) 2010 Embecosm Limited
5 
 
6 
   Contributors various OpenCores participants
7 
   Contributor Jeremy Bennett
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see .  */
23 
 
24 
/* ----------------------------------------------------------------------------
25 
   This code is commented throughout for use with Doxygen.
26 
   --------------------------------------------------------------------------*/
27 
 
28 
/* Basic SR flag test */
29 
 
30 
#include "spr-defs.h"
31 
 
32 
#define SET_ARITH_FLAG   0  /* If this is not set this test has no meaning */
33 
 
34 
        .section .except, "ax"
35 
 
36 
        .org 0x100
37 
_reset:
38 
        l.nop
39 458 julius 
        l.movhi r10,0x8000
40 
        l.addi  r11,r0,-1
41 
        l.addi  r12,r0,2
42 
        l.addi  r13,r0,0x5678
43 
        l.movhi r14,0xdead
44 
        l.ori   r14,r14,0xdead
45 
        l.addi  r15,r0,0xdead
46 
        l.movhi r3,hi(start)
47 
        l.ori   r3,r3,lo(start)
48 
        l.jr    r3
49 
        l.nop
50 90 jeremybenn 
 
51 458 julius 
 
52 
        .section .text
53 
start:
54 90 jeremybenn 
  /* Test start */
55 
 
56 
#if SET_ARITH_FLAG
57 
  /* Simple zero test */
58 
  l.addi r1,r0,1        /* f = 0 */
59 
  l.addi  r1, r0, 0
60 
  l.bnf     _err
61 
  l.bf     _err
62 
  l.addi r1,r0,1        /* f = 0 */
63 
  l.add  r1, r0, r0
64 
  l.bnf     _err
65 
  l.addi r1,r0,1        /* f = 0 */
66 
  l.andi  r1, r0, 0
67 
  l.bnf     _err
68 
  l.addi r1,r0,1        /* f = 0 */
69 
  l.and  r1, r0, r0
70 
  l.bnf     _err
71 
 
72 
  l.addi r1,r0,1        /* f = 0 */
73 
  l.sub  r1, r0, r0
74 
  l.bf     _err
75 
  l.or   r1, r0, r0
76 
  l.bf     _err
77 
  l.ori  r1, r0, 0
78 
  l.bf     _err
79 
  l.xor  r1, r0, r0
80 
  l.bf     _err
81 
  l.xori r1, r0, 0
82 
  l.bf     _err
83 
 
84 
  l.addi r1,r0,0        /* f = 1 */
85 
  l.sub  r1, r0, r0
86 
  l.bnf     _err
87 
  l.or   r1, r0, r0
88 
  l.bnf     _err
89 
  l.ori  r1, r0, 0
90 
  l.bnf     _err
91 
  l.xor  r1, r0, r0
92 
  l.bnf     _err
93 
  l.xori r1, r0, 0
94 
  l.bnf     _err
95 
 
96 
  l.addi r1,r0,0        /* f = 1 */
97 
  l.addi  r1, r0, 0xdead
98 
  l.bf     _err
99 
  l.addi r1,r0,0        /* f = 1 */
100 
  l.add  r1, r0, r15
101 
  l.bf     _err
102 
  l.addi r1,r0,0        /* f = 1 */
103 
  l.andi  r1, r11, 0xdead
104 
  l.bf     _err
105 
  l.addi r1,r0,0        /* f = 1 */
106 
  l.and  r1, r11, r15
107 
  l.bf     _err
108 
 
109 
  l.addi r1,r0,0        /* f = 1 */
110 
  l.addi  r1, r11, 0
111 
  l.bf     _err
112 
  l.addi r1,r0,0        /* f = 1 */
113 
  l.add  r1, r11, r0
114 
  l.bf     _err
115 
  l.addi r1,r0,0        /* f = 1 */
116 
  l.andi  r1, r11, 0x1234
117 
  l.bf     _err
118 
  l.addi r1,r0,0        /* f = 1 */
119 
  l.and  r1, r11, r10
120 
  l.bf     _err
121 
#endif
122 
 
123 
  l.movhi r3,0xdead
124 
  l.ori   r3,r3,0xdead
125 
  l.nop   NOP_REPORT
126 
  l.ori   r3,r0,0
127 
  l.nop   NOP_EXIT
128 
 
129 
_err:
130 
  l.ori   r3,r1,0
131 
  l.nop   NOP_REPORT
132 
  l.mfspr r3,r0,SPR_SR
133 
  l.nop   NOP_REPORT
134 
  l.nop   NOP_EXIT

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.