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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [flag/] [flag.S] - Blame information for rev 787

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1 90 jeremybenn 
/* flag.S. Test of Or1ksim status register flags
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   Copyright (C) 1999-2006 OpenCores
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   Copyright (C) 2010 Embecosm Limited
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   Contributors various OpenCores participants
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   Contributor Jeremy Bennett
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see .  */
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/* ----------------------------------------------------------------------------
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   This code is commented throughout for use with Doxygen.
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   --------------------------------------------------------------------------*/
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/* Basic SR flag test */
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#include "spr-defs.h"
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#define SET_ARITH_FLAG   0  /* If this is not set this test has no meaning */
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        .section .except, "ax"
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        .org 0x100
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_reset:
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        l.nop
39 787 jeremybenn 
 
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    // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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    // and indeed it is not when simulating the or1200 Verilog core.
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    l.andi  r0,r0,0x0
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44 458 julius 
        l.movhi r10,0x8000
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        l.addi  r11,r0,-1
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        l.addi  r12,r0,2
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        l.addi  r13,r0,0x5678
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        l.movhi r14,0xdead
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        l.ori   r14,r14,0xdead
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        l.addi  r15,r0,0xdead
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        l.movhi r3,hi(start)
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        l.ori   r3,r3,lo(start)
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        l.jr    r3
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        l.nop
55 90 jeremybenn 
 
56 458 julius 
 
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        .section .text
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start:
59 90 jeremybenn 
  /* Test start */
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#if SET_ARITH_FLAG
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  /* Simple zero test */
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  l.addi r1,r0,1        /* f = 0 */
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  l.addi  r1, r0, 0
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  l.bnf     _err
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  l.bf     _err
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  l.addi r1,r0,1        /* f = 0 */
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  l.add  r1, r0, r0
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  l.bnf     _err
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  l.addi r1,r0,1        /* f = 0 */
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  l.andi  r1, r0, 0
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  l.bnf     _err
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  l.addi r1,r0,1        /* f = 0 */
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  l.and  r1, r0, r0
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  l.bnf     _err
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  l.addi r1,r0,1        /* f = 0 */
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  l.sub  r1, r0, r0
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  l.bf     _err
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  l.or   r1, r0, r0
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  l.bf     _err
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  l.ori  r1, r0, 0
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  l.bf     _err
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  l.xor  r1, r0, r0
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  l.bf     _err
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  l.xori r1, r0, 0
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.sub  r1, r0, r0
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  l.bnf     _err
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  l.or   r1, r0, r0
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  l.bnf     _err
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  l.ori  r1, r0, 0
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  l.bnf     _err
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  l.xor  r1, r0, r0
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  l.bnf     _err
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  l.xori r1, r0, 0
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  l.bnf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.addi  r1, r0, 0xdead
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.add  r1, r0, r15
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.andi  r1, r11, 0xdead
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.and  r1, r11, r15
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.addi  r1, r11, 0
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.add  r1, r11, r0
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.andi  r1, r11, 0x1234
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  l.bf     _err
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  l.addi r1,r0,0        /* f = 1 */
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  l.and  r1, r11, r10
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  l.bf     _err
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#endif
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  l.movhi r3,0xdead
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  l.ori   r3,r3,0xdead
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  l.nop   NOP_REPORT
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  l.ori   r3,r0,0
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  l.nop   NOP_EXIT
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_err:
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  l.ori   r3,r1,0
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  l.nop   NOP_REPORT
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  l.mfspr r3,r0,SPR_SR
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  l.nop   NOP_REPORT
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  l.nop   NOP_EXIT

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