OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [flag/] [flag.S] - Blame information for rev 90

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn 
/* flag.S. Test of Or1ksim status register flags
2 
 
3 
   Copyright (C) 1999-2006 OpenCores
4 
   Copyright (C) 2010 Embecosm Limited
5 
 
6 
   Contributors various OpenCores participants
7 
   Contributor Jeremy Bennett
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see .  */
23 
 
24 
/* ----------------------------------------------------------------------------
25 
   This code is commented throughout for use with Doxygen.
26 
   --------------------------------------------------------------------------*/
27 
 
28 
/* Basic SR flag test */
29 
 
30 
#include "spr-defs.h"
31 
 
32 
#define SET_ARITH_FLAG   0  /* If this is not set this test has no meaning */
33 
 
34 
        .section .except, "ax"
35 
  l.movhi r10,0x8000
36 
 
37 
  .section .text
38 
        .org 0x100
39 
_reset:
40 
        l.nop
41 
 
42 
  l.movhi r10,0x8000
43 
  l.addi  r11,r0,-1
44 
  l.addi  r12,r0,2
45 
  l.addi  r13,r0,0x5678
46 
  l.movhi r14,0xdead
47 
  l.ori   r14,r14,0xdead
48 
  l.addi  r15,r0,0xdead
49 
 
50 
  /* Test start */
51 
 
52 
#if SET_ARITH_FLAG
53 
  /* Simple zero test */
54 
  l.addi r1,r0,1        /* f = 0 */
55 
  l.addi  r1, r0, 0
56 
  l.bnf     _err
57 
  l.bf     _err
58 
  l.addi r1,r0,1        /* f = 0 */
59 
  l.add  r1, r0, r0
60 
  l.bnf     _err
61 
  l.addi r1,r0,1        /* f = 0 */
62 
  l.andi  r1, r0, 0
63 
  l.bnf     _err
64 
  l.addi r1,r0,1        /* f = 0 */
65 
  l.and  r1, r0, r0
66 
  l.bnf     _err
67 
 
68 
  l.addi r1,r0,1        /* f = 0 */
69 
  l.sub  r1, r0, r0
70 
  l.bf     _err
71 
  l.or   r1, r0, r0
72 
  l.bf     _err
73 
  l.ori  r1, r0, 0
74 
  l.bf     _err
75 
  l.xor  r1, r0, r0
76 
  l.bf     _err
77 
  l.xori r1, r0, 0
78 
  l.bf     _err
79 
 
80 
  l.addi r1,r0,0        /* f = 1 */
81 
  l.sub  r1, r0, r0
82 
  l.bnf     _err
83 
  l.or   r1, r0, r0
84 
  l.bnf     _err
85 
  l.ori  r1, r0, 0
86 
  l.bnf     _err
87 
  l.xor  r1, r0, r0
88 
  l.bnf     _err
89 
  l.xori r1, r0, 0
90 
  l.bnf     _err
91 
 
92 
  l.addi r1,r0,0        /* f = 1 */
93 
  l.addi  r1, r0, 0xdead
94 
  l.bf     _err
95 
  l.addi r1,r0,0        /* f = 1 */
96 
  l.add  r1, r0, r15
97 
  l.bf     _err
98 
  l.addi r1,r0,0        /* f = 1 */
99 
  l.andi  r1, r11, 0xdead
100 
  l.bf     _err
101 
  l.addi r1,r0,0        /* f = 1 */
102 
  l.and  r1, r11, r15
103 
  l.bf     _err
104 
 
105 
  l.addi r1,r0,0        /* f = 1 */
106 
  l.addi  r1, r11, 0
107 
  l.bf     _err
108 
  l.addi r1,r0,0        /* f = 1 */
109 
  l.add  r1, r11, r0
110 
  l.bf     _err
111 
  l.addi r1,r0,0        /* f = 1 */
112 
  l.andi  r1, r11, 0x1234
113 
  l.bf     _err
114 
  l.addi r1,r0,0        /* f = 1 */
115 
  l.and  r1, r11, r10
116 
  l.bf     _err
117 
#endif
118 
 
119 
  l.movhi r3,0xdead
120 
  l.ori   r3,r3,0xdead
121 
  l.nop   NOP_REPORT
122 
  l.ori   r3,r0,0
123 
  l.nop   NOP_EXIT
124 
 
125 
_err:
126 
  l.ori   r3,r1,0
127 
  l.nop   NOP_REPORT
128 
  l.mfspr r3,r0,SPR_SR
129 
  l.nop   NOP_REPORT
130 
  l.nop   NOP_EXIT

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.