| 1 |
107 |
jeremybenn |
/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
|
| 2 |
|
|
*
|
| 3 |
|
|
* Copyright (C) 1999-2006 OpenCores
|
| 4 |
|
|
* Copyright (C) 2010 Embecosm Limited
|
| 5 |
|
|
*
|
| 6 |
|
|
* Contributors various OpenCores participants
|
| 7 |
|
|
* Contributor Jeremy Bennett
|
| 8 |
|
|
*
|
| 9 |
|
|
* This file is part of OpenRISC 1000 Architectural Simulator.
|
| 10 |
|
|
*
|
| 11 |
|
|
* This program is free software; you can redistribute it and/or modify it
|
| 12 |
|
|
* under the terms of the GNU General Public License as published by the Free
|
| 13 |
|
|
* Software Foundation; either version 3 of the License, or (at your option)
|
| 14 |
|
|
* any later version.
|
| 15 |
|
|
*
|
| 16 |
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
| 17 |
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 18 |
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
| 19 |
|
|
* more details.
|
| 20 |
|
|
*
|
| 21 |
|
|
* You should have received a copy of the GNU General Public License along
|
| 22 |
|
|
* with this program. If not, see .
|
| 23 |
|
|
*/
|
| 24 |
|
|
|
| 25 |
|
|
/* ----------------------------------------------------------------------------
|
| 26 |
|
|
* Coding conventions
|
| 27 |
|
|
*
|
| 28 |
|
|
* A simple rising stack is provided starting at _stack and pointed to by
|
| 29 |
|
|
* r1. r1 points to the next free word. Only 32-bit registers may be pushed
|
| 30 |
|
|
* onto the stack.
|
| 31 |
|
|
*
|
| 32 |
|
|
* Local labels up to 49 are reserved for macros. Each is used only once in
|
| 33 |
|
|
* all macros. You can get in a serious mess if you get local label clashing
|
| 34 |
|
|
* in macros.
|
| 35 |
|
|
*
|
| 36 |
|
|
* Arguments to functions are passed in r3 through r8.
|
| 37 |
|
|
* r9 is the link (return address)
|
| 38 |
|
|
* r11 is for returning results
|
| 39 |
|
|
*
|
| 40 |
|
|
* Only r1 and r2 are preserved across function calls. It is up to the callee
|
| 41 |
|
|
* to save any other registers required.
|
| 42 |
|
|
* ------------------------------------------------------------------------- */
|
| 43 |
|
|
|
| 44 |
|
|
/* ----------------------------------------------------------------------------
|
| 45 |
|
|
* Test coverage
|
| 46 |
|
|
*
|
| 47 |
|
|
* The l.div and l.divu instructions should set the carry flag as well as
|
| 48 |
|
|
* triggering an event when divide by zero occurs.
|
| 49 |
|
|
*
|
| 50 |
|
|
* Having fixed the problem, this is (in good software engineering style), a
|
| 51 |
|
|
* regresison test to go with the fix.
|
| 52 |
|
|
*
|
| 53 |
|
|
* This is not a comprehensive test of either instruction (yet).
|
| 54 |
|
|
*
|
| 55 |
|
|
* Of course what is really needed is a comprehensive instruction test...
|
| 56 |
|
|
* ------------------------------------------------------------------------- */
|
| 57 |
|
|
|
| 58 |
|
|
|
| 59 |
|
|
#include "inst-set-test.h"
|
| 60 |
|
|
|
| 61 |
|
|
/* ----------------------------------------------------------------------------
|
| 62 |
|
|
* Test of divide l.div
|
| 63 |
|
|
* ------------------------------------------------------------------------- */
|
| 64 |
|
|
|
| 65 |
|
|
.section .text
|
| 66 |
|
|
.global _start
|
| 67 |
|
|
_start:
|
| 68 |
|
|
/* Signed divide by zero */
|
| 69 |
|
|
_div:
|
| 70 |
|
|
LOAD_STR (r3, "l.div\n")
|
| 71 |
|
|
l.jal _puts
|
| 72 |
|
|
l.nop
|
| 73 |
|
|
|
| 74 |
|
|
LOAD_CONST (r2, ~SPR_SR_CY) /* Clear the carry flag */
|
| 75 |
|
|
l.mfspr r3,r0,SPR_SR
|
| 76 |
|
|
l.and r3,r3,r2
|
| 77 |
|
|
l.mtspr r0,r3,SPR_SR
|
| 78 |
|
|
|
| 79 |
|
|
LOAD_CONST (r5,1) /* Set up args for division */
|
| 80 |
|
|
LOAD_CONST (r6,0)
|
| 81 |
|
|
l.div r4,r5,r6
|
| 82 |
|
|
|
| 83 |
|
|
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
|
| 84 |
|
|
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
|
| 85 |
|
|
l.and r2,r2,r4
|
| 86 |
|
|
l.sfeq r2,r4
|
| 87 |
|
|
CHECK_FLAG ("1 / 0 (with error) carry flag set: ", TRUE)
|
| 88 |
|
|
|
| 89 |
|
|
/* Signed divide by zero */
|
| 90 |
|
|
_divu:
|
| 91 |
|
|
LOAD_STR (r3, "l.divu\n")
|
| 92 |
|
|
l.jal _puts
|
| 93 |
|
|
l.nop
|
| 94 |
|
|
|
| 95 |
|
|
LOAD_CONST (r2, ~SPR_SR_CY) /* Clear the carry flag */
|
| 96 |
|
|
l.mfspr r3,r0,SPR_SR
|
| 97 |
|
|
l.and r3,r3,r2
|
| 98 |
|
|
l.mtspr r0,r3,SPR_SR
|
| 99 |
|
|
|
| 100 |
|
|
LOAD_CONST (r5,1) /* Set up args for division */
|
| 101 |
|
|
LOAD_CONST (r6,0)
|
| 102 |
|
|
l.divu r4,r5,r6
|
| 103 |
|
|
|
| 104 |
|
|
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
|
| 105 |
|
|
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
|
| 106 |
|
|
l.and r2,r2,r4
|
| 107 |
|
|
l.sfeq r2,r4
|
| 108 |
|
|
CHECK_FLAG ("1 / 0 (with error) carry flag set: ", TRUE)
|
| 109 |
|
|
|
| 110 |
|
|
/* ----------------------------------------------------------------------------
|
| 111 |
|
|
* All done
|
| 112 |
|
|
* ------------------------------------------------------------------------- */
|
| 113 |
|
|
_exit:
|
| 114 |
|
|
LOAD_STR (r3, "Test completed\n")
|
| 115 |
|
|
l.jal _puts
|
| 116 |
|
|
l.nop
|
| 117 |
|
|
|
| 118 |
|
|
TEST_EXIT
|
