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/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
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*
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* Copyright (C) 1999-2006 OpenCores
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* Copyright (C) 2010 Embecosm Limited
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*
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* Contributors various OpenCores participants
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* Contributor Jeremy Bennett
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*
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* This file is part of OpenRISC 1000 Architectural Simulator.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 3 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see .
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*/
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/* ----------------------------------------------------------------------------
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116 |
jeremybenn |
* Coding conventions are described in inst-set-test.S
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107 |
jeremybenn |
* ------------------------------------------------------------------------- */
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/* ----------------------------------------------------------------------------
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* Test coverage
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*
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* The l.div and l.divu instructions should set the carry flag as well as
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* triggering an event when divide by zero occurs.
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*
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* Having fixed the problem, this is (in good software engineering style), a
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* regresison test to go with the fix.
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*
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* This is not a comprehensive test of either instruction (yet).
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*
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* Of course what is really needed is a comprehensive instruction test...
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* ------------------------------------------------------------------------- */
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#include "inst-set-test.h"
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/* ----------------------------------------------------------------------------
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* Test of divide l.div
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* ------------------------------------------------------------------------- */
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.section .text
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.global _start
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_start:
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/* Signed divide by zero */
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_div:
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LOAD_STR (r3, "l.div\n")
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l.jal _puts
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l.nop
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LOAD_CONST (r2, ~SPR_SR_CY) /* Clear the carry flag */
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l.mfspr r3,r0,SPR_SR
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l.and r3,r3,r2
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l.mtspr r0,r3,SPR_SR
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LOAD_CONST (r5,1) /* Set up args for division */
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LOAD_CONST (r6,0)
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l.div r4,r5,r6
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l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
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LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
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l.and r2,r2,r4
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l.sfeq r2,r4
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CHECK_FLAG ("1 / 0 (with error) carry flag set: ", TRUE)
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/* Signed divide by zero */
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_divu:
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LOAD_STR (r3, "l.divu\n")
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l.jal _puts
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l.nop
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LOAD_CONST (r2, ~SPR_SR_CY) /* Clear the carry flag */
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l.mfspr r3,r0,SPR_SR
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l.and r3,r3,r2
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l.mtspr r0,r3,SPR_SR
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LOAD_CONST (r5,1) /* Set up args for division */
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LOAD_CONST (r6,0)
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l.divu r4,r5,r6
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l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
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LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
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l.and r2,r2,r4
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l.sfeq r2,r4
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CHECK_FLAG ("1 / 0 (with error) carry flag set: ", TRUE)
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/* ----------------------------------------------------------------------------
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* All done
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* ------------------------------------------------------------------------- */
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_exit:
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LOAD_STR (r3, "Test completed\n")
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l.jal _puts
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l.nop
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TEST_EXIT
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