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/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
 *
 * Copyright (C) 1999-2006 OpenCores
 * Copyright (C) 2010 Embecosm Limited
 *
 * Contributors various OpenCores participants
 * Contributor Jeremy Bennett 
 *
 * This file is part of OpenRISC 1000 Architectural Simulator.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 3 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program.  If not, see .
 */
 
/* ----------------------------------------------------------------------------
 * Coding conventions are described in inst-set-test.S
 * ------------------------------------------------------------------------- */
 
/* ----------------------------------------------------------------------------
 * Test coverage
 *
 * The l.div and l.divu instructions should set the carry flag as well as
 * triggering an event when divide by zero occurs.
 *
 * Having fixed the problem, this is (in good software engineering style), a
 * regresison test to go with the fix.
 *
 * This is not a comprehensive test of either instruction (yet).
 *
 * Of course what is really needed is a comprehensive instruction test...
 * ------------------------------------------------------------------------- */
 
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
 * A macro to carry out a test of divide signed or unsigned
 *
 * Arguments
 *   opc:       The opcode
 *   op1:       First operand value
 *   op2:       Second operand value
 *   res:       Expected result
 *   cy:        Expected carry flag
 *   ov:        Expected overflow flag
 * ------------------------------------------------------------------------- */
#define TEST_DIV(opc, op1, op2, res, cy, ov)                             \
        l.mfspr r3,r0,SPR_SR                                            ;\
        LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV))                       ;\
        l.and   r3,r3,r2                /* Clear flags */               ;\
        l.mtspr r0,r3,SPR_SR                                            ;\
                                                                        ;\
        l.or    r4,r0,r0                /* Clear result reg */          ;\
        LOAD_CONST (r5,op1)             /* Load numbers to add */       ;\
        LOAD_CONST (r6,op2)                                             ;\
        l.mtspr r0,r0,SPR_EPCR_BASE     /* Clear record */              ;\
50:     opc     r4,r5,r6                                                ;\
        l.mfspr r2,r0,SPR_SR            /* So we can examine flags */   ;\
        l.mfspr r5,r0,SPR_EPCR_BASE     /* What triggered exception */  ;\
        PUSH (r5)                       /* Save EPCR for later */       ;\
        PUSH (r2)                       /* Save SR for later */         ;\
        PUSH (r4)                       /* Save result for later */     ;\
                                                                        ;\
        PUTS ("  0x")                                                   ;\
        PUTH (op1)                                                      ;\
        PUTS (" / 0x")                                                  ;\
        PUTH (op2)                                                      ;\
        PUTS (" = 0x")                                                  ;\
        PUTH (res)                                                      ;\
        PUTS (": ")                                                     ;\
        POP (r4)                                                        ;\
        CHECK_RES1 (r4, res)                                            ;\
                                                                        ;\
        POP (r2)                        /* Retrieve SR */               ;\
        PUSH (r2)                                                       ;\
        LOAD_CONST (r4, SPR_SR_CY)      /* The carry bit */             ;\
        l.and   r2,r2,r4                                                ;\
        l.sfeq  r2,r4                                                   ;\
        CHECK_FLAG ("- carry flag set:      ", cy)                      ;\
                                                                        ;\
        POP (r2)                        /* Retrieve SR */               ;\
        LOAD_CONST (r4, SPR_SR_OV)      /* The overflow bit */          ;\
        l.and   r2,r2,r4                                                ;\
        l.sfeq  r2,r4                                                   ;\
        CHECK_FLAG ("- overflow flag set:   ", ov)                      ;\
                                                                        ;\
        POP (r2)                        /* Retrieve EPCR */             ;\
        LOAD_CONST (r4, 50b)            /* The opcode of interest */    ;\
        l.and   r2,r2,r4                                                ;\
        l.sfeq  r2,r4                                                   ;\
        l.bnf   51f                                                     ;\
                                                                        ;\
        PUTS ("  - exception triggered: TRUE\n")                        ;\
        l.j     52f                                                     ;\
        l.nop                                                           ;\
                                                                        ;\
51:     PUTS ("  - exception triggered: FALSE\n")                       ;\
52:
 
 
/* ----------------------------------------------------------------------------
 * Start of code
 * ------------------------------------------------------------------------- */
        .section .text
        .global _start
_start:
        l.mfspr r3,r0,SPR_SR
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
        l.and   r3,r3,r2
        l.mtspr r0,r3,SPR_SR
 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
        l.jal   _puts
        l.nop
 
/* ----------------------------------------------------------------------------
 * Test of divide signed, l.div
 * ------------------------------------------------------------------------- */
_div:
        LOAD_STR (r3, "l.div\n")
        l.jal   _puts
        l.nop
 
        /* Divide two positive numbers and check rounding. Should set no
           flags. */
        TEST_DIV (l.div, 0x0000000c, 0x00000003,
                  0x00000004, FALSE, FALSE)
 
        TEST_DIV (l.div, 0x0000000b, 0x00000003,
                  0x00000003, FALSE, FALSE)
 
        /* Divide two negative numbers and check rounding. Should set no
           flags. */
        TEST_DIV (l.div, 0xfffffff4, 0xfffffffd,
                  0x00000004, FALSE, FALSE)
 
        TEST_DIV (l.div, 0xfffffff5, 0xfffffffd,
                  0x00000003, FALSE, FALSE)
 
        /* Divide a negative number by a positive number and check
           rounding. Should set no flags. */
        TEST_DIV (l.div, 0xfffffff4, 0x00000003,
                  0xfffffffc, FALSE, FALSE)
 
        TEST_DIV (l.div, 0xfffffff5, 0x00000003,
                  0xfffffffd, FALSE, FALSE)
 
        /* Divide a positive number by a negative number and check
           rounding. Should set no flags. */
        TEST_DIV (l.div, 0x0000000c, 0xfffffffd,
                  0xfffffffc, FALSE, FALSE)
 
        TEST_DIV (l.div, 0x0000000b, 0xfffffffd,
                  0xfffffffd, FALSE, FALSE)
 
        /* Divide by zero. Should set the overflow flag. */
        TEST_DIV (l.div, 0x0000000c, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        TEST_DIV (l.div, 0xfffffff4, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        /* Check that range exceptions are triggered */
        l.mfspr r3,r0,SPR_SR
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
        l.or    r3,r3,r2
        l.mtspr r0,r3,SPR_SR
 
        LOAD_STR (r3, "  ** OVE flag set **\n")
        l.jal   _puts
        l.nop
 
        /* Divide by zero. Should set the overflow flag and trigger an
           exception. */
        TEST_DIV (l.div, 0x0000000c, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        TEST_DIV (l.div, 0xfffffff4, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        /* Finished checking range exceptions */
        l.mfspr r3,r0,SPR_SR
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
        l.and   r3,r3,r2
        l.mtspr r0,r3,SPR_SR
 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
        l.jal   _puts
        l.nop
 
/* ----------------------------------------------------------------------------
 * Test of divide unsigned, l.divu
 * ------------------------------------------------------------------------- */
_divu:
        LOAD_STR (r3, "l.divu\n")
        l.jal   _puts
        l.nop
 
        /* Divide two positive numbers and check rounding. Should set no
           flags. */
        TEST_DIV (l.divu, 0x0000000c, 0x00000003,
                  0x00000004, FALSE, FALSE)
 
        TEST_DIV (l.divu, 0x0000000b, 0x00000003,
                  0x00000003, FALSE, FALSE)
 
        /* Divide two numbers that would be negative under 2's complement and
           check rounding. Should set no flags. */
        TEST_DIV (l.divu, 0xfffffff4, 0xfffffffd,
                  0x00000000, FALSE, FALSE)
 
        TEST_DIV (l.divu, 0xfffffff5, 0xfffffffd,
                  0x00000000, FALSE, FALSE)
 
        /* Divide a number that would be negative under 2's complement by a
           number that would be positive under 2's complement and check
           rounding. Should set no flags. */
        TEST_DIV (l.divu, 0xfffffff4, 0x00000003,
                  0x55555551, FALSE, FALSE)
 
        TEST_DIV (l.divu, 0xfffffff5, 0x00000003,
                  0x55555551, FALSE, FALSE)
 
        /* Divide a number that would be positive under 2's complement by a
           number that would be negative under 2's complement and check
           rounding. Should set no flags. */
        TEST_DIV (l.divu, 0x0000000c, 0xfffffffd,
                  0x00000000, FALSE, FALSE)
 
        TEST_DIV (l.divu, 0x0000000b, 0xfffffffd,
                  0x00000000, FALSE, FALSE)
 
        /* Divide by zero. Should set the overflow flag. */
        TEST_DIV (l.divu, 0x0000000c, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        TEST_DIV (l.divu, 0xfffffff4, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        /* Check that range exceptions are triggered */
        l.mfspr r3,r0,SPR_SR
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
        l.or    r3,r3,r2
        l.mtspr r0,r3,SPR_SR
 
        LOAD_STR (r3, "  ** OVE flag set **\n")
        l.jal   _puts
        l.nop
 
        /* Divide by zero. Should set the overflow flag and trigger an
           exception. */
        TEST_DIV (l.divu, 0x0000000c, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        TEST_DIV (l.divu, 0xfffffff4, 0x00000000,
                  0x00000000, TRUE, FALSE)
 
        /* Finished checking range exceptions */
        l.mfspr r3,r0,SPR_SR
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
        l.and   r3,r3,r2
        l.mtspr r0,r3,SPR_SR
 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
        l.jal   _puts
        l.nop
 
/* ----------------------------------------------------------------------------
 * All done
 * ------------------------------------------------------------------------- */
_exit:
        LOAD_STR (r3, "Test completed\n")
        l.jal   _puts
        l.nop
 
        TEST_EXIT

Line No.	Rev	Author	Line
1	107	jeremybenn	`/* is-div-test.S. l.div and l.divu instruction test of Or1ksim`
2			`*`
3			`* Copyright (C) 1999-2006 OpenCores`
4			`* Copyright (C) 2010 Embecosm Limited`
5			`*`
6			`* Contributors various OpenCores participants`
7			`* Contributor Jeremy Bennett`
8			`*`
9			`* This file is part of OpenRISC 1000 Architectural Simulator.`
10			`*`
11			`* This program is free software; you can redistribute it and/or modify it`
12			`* under the terms of the GNU General Public License as published by the Free`
13			`* Software Foundation; either version 3 of the License, or (at your option)`
14			`* any later version.`
15			`*`
16			`* This program is distributed in the hope that it will be useful, but WITHOUT`
17			`* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`* more details.`
20			`*`
21			`* You should have received a copy of the GNU General Public License along`
22			`* with this program. If not, see .`
23			`*/`
24
25			`/* ----------------------------------------------------------------------------`
26	116	jeremybenn	`* Coding conventions are described in inst-set-test.S`
27	107	jeremybenn	`* ------------------------------------------------------------------------- */`
28
29			`/* ----------------------------------------------------------------------------`
30			`* Test coverage`
31			`*`
32			`* The l.div and l.divu instructions should set the carry flag as well as`
33			`* triggering an event when divide by zero occurs.`
34			`*`
35			`* Having fixed the problem, this is (in good software engineering style), a`
36			`* regresison test to go with the fix.`
37			`*`
38			`* This is not a comprehensive test of either instruction (yet).`
39			`*`
40			`* Of course what is really needed is a comprehensive instruction test...`
41			`* ------------------------------------------------------------------------- */`
42
43
44			`#include "inst-set-test.h"`
45
46			`/* ----------------------------------------------------------------------------`
47	118	jeremybenn	`* A macro to carry out a test of divide signed or unsigned`
48			`*`
49			`* Arguments`
50			`* opc: The opcode`
51			`* op1: First operand value`
52			`* op2: Second operand value`
53			`* res: Expected result`
54			`* cy: Expected carry flag`
55			`* ov: Expected overflow flag`
56	107	jeremybenn	`* ------------------------------------------------------------------------- */`
57	118	jeremybenn	`#define TEST_DIV(opc, op1, op2, res, cy, ov) \`
58			`l.mfspr r3,r0,SPR_SR ;\`
59			`LOAD_CONST (r2, ~(SPR_SR_CY \| SPR_SR_OV)) ;\`
60			`l.and r3,r3,r2 /* Clear flags */ ;\`
61			`l.mtspr r0,r3,SPR_SR ;\`
62			`;\`
63			`l.or r4,r0,r0 /* Clear result reg */ ;\`
64			`LOAD_CONST (r5,op1) /* Load numbers to add */ ;\`
65			`LOAD_CONST (r6,op2) ;\`
66			`l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\`
67			`50: opc r4,r5,r6 ;\`
68			`l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\`
69			`l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\`
70			`PUSH (r5) /* Save EPCR for later */ ;\`
71			`PUSH (r2) /* Save SR for later */ ;\`
72			`PUSH (r4) /* Save result for later */ ;\`
73			`;\`
74			`PUTS (" 0x") ;\`
75			`PUTH (op1) ;\`
76			`PUTS (" / 0x") ;\`
77			`PUTH (op2) ;\`
78			`PUTS (" = 0x") ;\`
79			`PUTH (res) ;\`
80			`PUTS (": ") ;\`
81			`POP (r4) ;\`
82			`CHECK_RES1 (r4, res) ;\`
83			`;\`
84			`POP (r2) /* Retrieve SR */ ;\`
85			`PUSH (r2) ;\`
86			`LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\`
87			`l.and r2,r2,r4 ;\`
88			`l.sfeq r2,r4 ;\`
89			`CHECK_FLAG ("- carry flag set: ", cy) ;\`
90			`;\`
91			`POP (r2) /* Retrieve SR */ ;\`
92			`LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\`
93			`l.and r2,r2,r4 ;\`
94			`l.sfeq r2,r4 ;\`
95			`CHECK_FLAG ("- overflow flag set: ", ov) ;\`
96			`;\`
97			`POP (r2) /* Retrieve EPCR */ ;\`
98			`LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\`
99			`l.and r2,r2,r4 ;\`
100			`l.sfeq r2,r4 ;\`
101			`l.bnf 51f ;\`
102			`;\`
103			`PUTS (" - exception triggered: TRUE\n") ;\`
104			`l.j 52f ;\`
105			`l.nop ;\`
106			`;\`
107			`51: PUTS (" - exception triggered: FALSE\n") ;\`
108			`52:`
109
110
111			`/* ----------------------------------------------------------------------------`
112			`* Start of code`
113			`* ------------------------------------------------------------------------- */`
114	107	jeremybenn	`.section .text`
115			`.global _start`
116			`_start:`
117	118	jeremybenn	`l.mfspr r3,r0,SPR_SR`
118			`LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */`
119			`l.and r3,r3,r2`
120			`l.mtspr r0,r3,SPR_SR`
121
122			`LOAD_STR (r3, " OVE flag cleared \n")`
123			`l.jal _puts`
124			`l.nop`
125
126			`/* ----------------------------------------------------------------------------`
127			`* Test of divide signed, l.div`
128			`* ------------------------------------------------------------------------- */`
129	107	jeremybenn	`_div:`
130			`LOAD_STR (r3, "l.div\n")`
131			`l.jal _puts`
132			`l.nop`
133
134	118	jeremybenn	`/* Divide two positive numbers and check rounding. Should set no`
135			`flags. */`
136			`TEST_DIV (l.div, 0x0000000c, 0x00000003,`
137			`0x00000004, FALSE, FALSE)`
138
139			`TEST_DIV (l.div, 0x0000000b, 0x00000003,`
140			`0x00000003, FALSE, FALSE)`
141
142			`/* Divide two negative numbers and check rounding. Should set no`
143			`flags. */`
144			`TEST_DIV (l.div, 0xfffffff4, 0xfffffffd,`
145			`0x00000004, FALSE, FALSE)`
146
147			`TEST_DIV (l.div, 0xfffffff5, 0xfffffffd,`
148			`0x00000003, FALSE, FALSE)`
149
150			`/* Divide a negative number by a positive number and check`
151			`rounding. Should set no flags. */`
152			`TEST_DIV (l.div, 0xfffffff4, 0x00000003,`
153			`0xfffffffc, FALSE, FALSE)`
154
155			`TEST_DIV (l.div, 0xfffffff5, 0x00000003,`
156			`0xfffffffd, FALSE, FALSE)`
157
158			`/* Divide a positive number by a negative number and check`
159			`rounding. Should set no flags. */`
160			`TEST_DIV (l.div, 0x0000000c, 0xfffffffd,`
161			`0xfffffffc, FALSE, FALSE)`
162
163			`TEST_DIV (l.div, 0x0000000b, 0xfffffffd,`
164			`0xfffffffd, FALSE, FALSE)`
165
166			`/* Divide by zero. Should set the overflow flag. */`
167			`TEST_DIV (l.div, 0x0000000c, 0x00000000,`
168			`0x00000000, TRUE, FALSE)`
169
170			`TEST_DIV (l.div, 0xfffffff4, 0x00000000,`
171			`0x00000000, TRUE, FALSE)`
172
173			`/* Check that range exceptions are triggered */`
174	107	jeremybenn	`l.mfspr r3,r0,SPR_SR`
175	118	jeremybenn	`LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */`
176			`l.or r3,r3,r2`
177	107	jeremybenn	`l.mtspr r0,r3,SPR_SR`
178	118	jeremybenn
179			`LOAD_STR (r3, " OVE flag set \n")`
180			`l.jal _puts`
181			`l.nop`
182	107	jeremybenn
183	118	jeremybenn	`/* Divide by zero. Should set the overflow flag and trigger an`
184			`exception. */`
185			`TEST_DIV (l.div, 0x0000000c, 0x00000000,`
186			`0x00000000, TRUE, FALSE)`
187
188			`TEST_DIV (l.div, 0xfffffff4, 0x00000000,`
189			`0x00000000, TRUE, FALSE)`
190	107	jeremybenn
191	118	jeremybenn	`/* Finished checking range exceptions */`
192			`l.mfspr r3,r0,SPR_SR`
193			`LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */`
194			`l.and r3,r3,r2`
195			`l.mtspr r0,r3,SPR_SR`
196
197			`LOAD_STR (r3, " OVE flag cleared \n")`
198			`l.jal _puts`
199			`l.nop`
200	107	jeremybenn
201	118	jeremybenn	`/* ----------------------------------------------------------------------------`
202			`* Test of divide unsigned, l.divu`
203			`* ------------------------------------------------------------------------- */`
204	107	jeremybenn	`_divu:`
205			`LOAD_STR (r3, "l.divu\n")`
206			`l.jal _puts`
207			`l.nop`
208
209	118	jeremybenn	`/* Divide two positive numbers and check rounding. Should set no`
210			`flags. */`
211			`TEST_DIV (l.divu, 0x0000000c, 0x00000003,`
212			`0x00000004, FALSE, FALSE)`
213
214			`TEST_DIV (l.divu, 0x0000000b, 0x00000003,`
215			`0x00000003, FALSE, FALSE)`
216
217			`/* Divide two numbers that would be negative under 2's complement and`
218			`check rounding. Should set no flags. */`
219			`TEST_DIV (l.divu, 0xfffffff4, 0xfffffffd,`
220			`0x00000000, FALSE, FALSE)`
221
222			`TEST_DIV (l.divu, 0xfffffff5, 0xfffffffd,`
223			`0x00000000, FALSE, FALSE)`
224
225			`/* Divide a number that would be negative under 2's complement by a`
226			`number that would be positive under 2's complement and check`
227			`rounding. Should set no flags. */`
228			`TEST_DIV (l.divu, 0xfffffff4, 0x00000003,`
229			`0x55555551, FALSE, FALSE)`
230
231			`TEST_DIV (l.divu, 0xfffffff5, 0x00000003,`
232			`0x55555551, FALSE, FALSE)`
233
234			`/* Divide a number that would be positive under 2's complement by a`
235			`number that would be negative under 2's complement and check`
236			`rounding. Should set no flags. */`
237			`TEST_DIV (l.divu, 0x0000000c, 0xfffffffd,`
238			`0x00000000, FALSE, FALSE)`
239
240			`TEST_DIV (l.divu, 0x0000000b, 0xfffffffd,`
241			`0x00000000, FALSE, FALSE)`
242
243			`/* Divide by zero. Should set the overflow flag. */`
244			`TEST_DIV (l.divu, 0x0000000c, 0x00000000,`
245			`0x00000000, TRUE, FALSE)`
246
247			`TEST_DIV (l.divu, 0xfffffff4, 0x00000000,`
248			`0x00000000, TRUE, FALSE)`
249
250			`/* Check that range exceptions are triggered */`
251	107	jeremybenn	`l.mfspr r3,r0,SPR_SR`
252	118	jeremybenn	`LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */`
253			`l.or r3,r3,r2`
254	107	jeremybenn	`l.mtspr r0,r3,SPR_SR`
255	118	jeremybenn
256			`LOAD_STR (r3, " OVE flag set \n")`
257			`l.jal _puts`
258			`l.nop`
259	107	jeremybenn
260	118	jeremybenn	`/* Divide by zero. Should set the overflow flag and trigger an`
261			`exception. */`
262			`TEST_DIV (l.divu, 0x0000000c, 0x00000000,`
263			`0x00000000, TRUE, FALSE)`
264
265			`TEST_DIV (l.divu, 0xfffffff4, 0x00000000,`
266			`0x00000000, TRUE, FALSE)`
267	107	jeremybenn
268	118	jeremybenn	`/* Finished checking range exceptions */`
269			`l.mfspr r3,r0,SPR_SR`
270			`LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */`
271			`l.and r3,r3,r2`
272			`l.mtspr r0,r3,SPR_SR`
273
274			`LOAD_STR (r3, " OVE flag cleared \n")`
275			`l.jal _puts`
276			`l.nop`
277	107	jeremybenn
278			`/* ----------------------------------------------------------------------------`
279			`* All done`
280			`* ------------------------------------------------------------------------- */`
281			`_exit:`
282			`LOAD_STR (r3, "Test completed\n")`
283			`l.jal _puts`
284			`l.nop`
285
286	118	jeremybenn	`TEST_EXIT`

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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [inst-set-test/] [is-div-test.S] - Blame information for rev 118