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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [inst-set-test/] [is-div-test.S] - Blame information for rev 808

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1 107 jeremybenn
/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
2
 *
3
 * Copyright (C) 1999-2006 OpenCores
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 * Copyright (C) 2010 Embecosm Limited
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 *
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 * Contributors various OpenCores participants
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 * Contributor Jeremy Bennett 
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 *
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 * This file is part of OpenRISC 1000 Architectural Simulator.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License as published by the Free
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 * Software Foundation; either version 3 of the License, or (at your option)
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 * any later version.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program.  If not, see .
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 */
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25
/* ----------------------------------------------------------------------------
26 116 jeremybenn
 * Coding conventions are described in inst-set-test.S
27 107 jeremybenn
 * ------------------------------------------------------------------------- */
28
 
29
/* ----------------------------------------------------------------------------
30
 * Test coverage
31
 *
32
 * The l.div and l.divu instructions should set the carry flag as well as
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 * triggering an event when divide by zero occurs.
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 *
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 * Having fixed the problem, this is (in good software engineering style), a
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 * regresison test to go with the fix.
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 *
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 * This is not a comprehensive test of either instruction (yet).
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 *
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 * Of course what is really needed is a comprehensive instruction test...
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 * ------------------------------------------------------------------------- */
42
 
43
 
44
#include "inst-set-test.h"
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46
/* ----------------------------------------------------------------------------
47 118 jeremybenn
 * A macro to carry out a test of divide signed or unsigned
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 *
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 * Arguments
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 *   opc:       The opcode
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 *   op1:       First operand value
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 *   op2:       Second operand value
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 *   res:       Expected result
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 *   cy:        Expected carry flag
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 *   ov:        Expected overflow flag
56 107 jeremybenn
 * ------------------------------------------------------------------------- */
57 118 jeremybenn
#define TEST_DIV(opc, op1, op2, res, cy, ov)                             \
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        l.mfspr r3,r0,SPR_SR                                            ;\
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        LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV))                       ;\
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        l.and   r3,r3,r2                /* Clear flags */               ;\
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        l.mtspr r0,r3,SPR_SR                                            ;\
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                                                                        ;\
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        l.or    r4,r0,r0                /* Clear result reg */          ;\
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        LOAD_CONST (r5,op1)             /* Load numbers to add */       ;\
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        LOAD_CONST (r6,op2)                                             ;\
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        l.mtspr r0,r0,SPR_EPCR_BASE     /* Clear record */              ;\
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50:     opc     r4,r5,r6                                                ;\
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        l.mfspr r2,r0,SPR_SR            /* So we can examine flags */   ;\
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        l.mfspr r5,r0,SPR_EPCR_BASE     /* What triggered exception */  ;\
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        PUSH (r5)                       /* Save EPCR for later */       ;\
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        PUSH (r2)                       /* Save SR for later */         ;\
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        PUSH (r4)                       /* Save result for later */     ;\
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                                                                        ;\
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        PUTS ("  0x")                                                   ;\
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        PUTH (op1)                                                      ;\
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        PUTS (" / 0x")                                                  ;\
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        PUTH (op2)                                                      ;\
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        PUTS (" = 0x")                                                  ;\
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        PUTH (res)                                                      ;\
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        PUTS (": ")                                                     ;\
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        POP (r4)                                                        ;\
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        CHECK_RES1 (r4, res)                                            ;\
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                                                                        ;\
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        POP (r2)                        /* Retrieve SR */               ;\
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        PUSH (r2)                                                       ;\
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        LOAD_CONST (r4, SPR_SR_CY)      /* The carry bit */             ;\
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        l.and   r2,r2,r4                                                ;\
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        l.sfeq  r2,r4                                                   ;\
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        CHECK_FLAG ("- carry flag set:      ", cy)                      ;\
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                                                                        ;\
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        POP (r2)                        /* Retrieve SR */               ;\
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        LOAD_CONST (r4, SPR_SR_OV)      /* The overflow bit */          ;\
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        l.and   r2,r2,r4                                                ;\
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        l.sfeq  r2,r4                                                   ;\
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        CHECK_FLAG ("- overflow flag set:   ", ov)                      ;\
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                                                                        ;\
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        POP (r2)                        /* Retrieve EPCR */             ;\
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        LOAD_CONST (r4, 50b)            /* The opcode of interest */    ;\
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        l.and   r2,r2,r4                                                ;\
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        l.sfeq  r2,r4                                                   ;\
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        l.bnf   51f                                                     ;\
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                                                                        ;\
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        PUTS ("  - exception triggered: TRUE\n")                        ;\
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        l.j     52f                                                     ;\
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        l.nop                                                           ;\
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                                                                        ;\
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51:     PUTS ("  - exception triggered: FALSE\n")                       ;\
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52:
109
 
110
 
111
/* ----------------------------------------------------------------------------
112
 * Start of code
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 * ------------------------------------------------------------------------- */
114 107 jeremybenn
        .section .text
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        .global _start
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_start:
117 118 jeremybenn
        l.mfspr r3,r0,SPR_SR
118
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
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        l.and   r3,r3,r2
120
        l.mtspr r0,r3,SPR_SR
121
 
122
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
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        l.jal   _puts
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        l.nop
125
 
126
/* ----------------------------------------------------------------------------
127
 * Test of divide signed, l.div
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 * ------------------------------------------------------------------------- */
129 107 jeremybenn
_div:
130
        LOAD_STR (r3, "l.div\n")
131
        l.jal   _puts
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        l.nop
133
 
134 118 jeremybenn
        /* Divide two positive numbers and check rounding. Should set no
135
           flags. */
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        TEST_DIV (l.div, 0x0000000c, 0x00000003,
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                  0x00000004, FALSE, FALSE)
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139
        TEST_DIV (l.div, 0x0000000b, 0x00000003,
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                  0x00000003, FALSE, FALSE)
141
 
142
        /* Divide two negative numbers and check rounding. Should set no
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           flags. */
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        TEST_DIV (l.div, 0xfffffff4, 0xfffffffd,
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                  0x00000004, FALSE, FALSE)
146
 
147
        TEST_DIV (l.div, 0xfffffff5, 0xfffffffd,
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                  0x00000003, FALSE, FALSE)
149
 
150
        /* Divide a negative number by a positive number and check
151
           rounding. Should set no flags. */
152
        TEST_DIV (l.div, 0xfffffff4, 0x00000003,
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                  0xfffffffc, FALSE, FALSE)
154
 
155
        TEST_DIV (l.div, 0xfffffff5, 0x00000003,
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                  0xfffffffd, FALSE, FALSE)
157
 
158
        /* Divide a positive number by a negative number and check
159
           rounding. Should set no flags. */
160
        TEST_DIV (l.div, 0x0000000c, 0xfffffffd,
161
                  0xfffffffc, FALSE, FALSE)
162
 
163
        TEST_DIV (l.div, 0x0000000b, 0xfffffffd,
164
                  0xfffffffd, FALSE, FALSE)
165
 
166
        /* Divide by zero. Should set the overflow flag. */
167
        TEST_DIV (l.div, 0x0000000c, 0x00000000,
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                  0x00000000, TRUE, FALSE)
169
 
170
        TEST_DIV (l.div, 0xfffffff4, 0x00000000,
171
                  0x00000000, TRUE, FALSE)
172
 
173
        /* Check that range exceptions are triggered */
174 107 jeremybenn
        l.mfspr r3,r0,SPR_SR
175 118 jeremybenn
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
176
        l.or    r3,r3,r2
177 107 jeremybenn
        l.mtspr r0,r3,SPR_SR
178 118 jeremybenn
 
179
        LOAD_STR (r3, "  ** OVE flag set **\n")
180
        l.jal   _puts
181
        l.nop
182 107 jeremybenn
 
183 118 jeremybenn
        /* Divide by zero. Should set the overflow flag and trigger an
184
           exception. */
185
        TEST_DIV (l.div, 0x0000000c, 0x00000000,
186
                  0x00000000, TRUE, FALSE)
187
 
188
        TEST_DIV (l.div, 0xfffffff4, 0x00000000,
189
                  0x00000000, TRUE, FALSE)
190 107 jeremybenn
 
191 118 jeremybenn
        /* Finished checking range exceptions */
192
        l.mfspr r3,r0,SPR_SR
193
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
194
        l.and   r3,r3,r2
195
        l.mtspr r0,r3,SPR_SR
196
 
197
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
198
        l.jal   _puts
199
        l.nop
200 107 jeremybenn
 
201 118 jeremybenn
/* ----------------------------------------------------------------------------
202
 * Test of divide unsigned, l.divu
203
 * ------------------------------------------------------------------------- */
204 107 jeremybenn
_divu:
205
        LOAD_STR (r3, "l.divu\n")
206
        l.jal   _puts
207
        l.nop
208
 
209 118 jeremybenn
        /* Divide two positive numbers and check rounding. Should set no
210
           flags. */
211
        TEST_DIV (l.divu, 0x0000000c, 0x00000003,
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                  0x00000004, FALSE, FALSE)
213
 
214
        TEST_DIV (l.divu, 0x0000000b, 0x00000003,
215
                  0x00000003, FALSE, FALSE)
216
 
217
        /* Divide two numbers that would be negative under 2's complement and
218
           check rounding. Should set no flags. */
219
        TEST_DIV (l.divu, 0xfffffff4, 0xfffffffd,
220
                  0x00000000, FALSE, FALSE)
221
 
222
        TEST_DIV (l.divu, 0xfffffff5, 0xfffffffd,
223
                  0x00000000, FALSE, FALSE)
224
 
225
        /* Divide a number that would be negative under 2's complement by a
226
           number that would be positive under 2's complement and check
227
           rounding. Should set no flags. */
228
        TEST_DIV (l.divu, 0xfffffff4, 0x00000003,
229
                  0x55555551, FALSE, FALSE)
230
 
231
        TEST_DIV (l.divu, 0xfffffff5, 0x00000003,
232
                  0x55555551, FALSE, FALSE)
233
 
234
        /* Divide a number that would be positive under 2's complement by a
235
           number that would be negative under 2's complement and check
236
           rounding. Should set no flags. */
237
        TEST_DIV (l.divu, 0x0000000c, 0xfffffffd,
238
                  0x00000000, FALSE, FALSE)
239
 
240
        TEST_DIV (l.divu, 0x0000000b, 0xfffffffd,
241
                  0x00000000, FALSE, FALSE)
242
 
243
        /* Divide by zero. Should set the overflow flag. */
244
        TEST_DIV (l.divu, 0x0000000c, 0x00000000,
245
                  0x00000000, TRUE, FALSE)
246
 
247
        TEST_DIV (l.divu, 0xfffffff4, 0x00000000,
248
                  0x00000000, TRUE, FALSE)
249
 
250
        /* Check that range exceptions are triggered */
251 107 jeremybenn
        l.mfspr r3,r0,SPR_SR
252 118 jeremybenn
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
253
        l.or    r3,r3,r2
254 107 jeremybenn
        l.mtspr r0,r3,SPR_SR
255 118 jeremybenn
 
256
        LOAD_STR (r3, "  ** OVE flag set **\n")
257
        l.jal   _puts
258
        l.nop
259 107 jeremybenn
 
260 118 jeremybenn
        /* Divide by zero. Should set the overflow flag and trigger an
261
           exception. */
262
        TEST_DIV (l.divu, 0x0000000c, 0x00000000,
263
                  0x00000000, TRUE, FALSE)
264
 
265
        TEST_DIV (l.divu, 0xfffffff4, 0x00000000,
266
                  0x00000000, TRUE, FALSE)
267 107 jeremybenn
 
268 118 jeremybenn
        /* Finished checking range exceptions */
269
        l.mfspr r3,r0,SPR_SR
270
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
271
        l.and   r3,r3,r2
272
        l.mtspr r0,r3,SPR_SR
273
 
274
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
275
        l.jal   _puts
276
        l.nop
277 107 jeremybenn
 
278
/* ----------------------------------------------------------------------------
279
 * All done
280
 * ------------------------------------------------------------------------- */
281
_exit:
282
        LOAD_STR (r3, "Test completed\n")
283
        l.jal   _puts
284
        l.nop
285
 
286 118 jeremybenn
        TEST_EXIT

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